EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet ...

JTAG/UART

Micro SD

24-V to 5-VDC/DC

Resetbutton

Mag

netic

s

Input: 24 V(17 to 60 V)

Micro USB

DDR3

Status LEDs

10/100/1000 Mb/s Ethernet

PHY1

DP83867IR RJ45


PHY2

DP83867IR

Sitara PMIC DDR3 P/S

Gigabit PHY P/S

Port 1

25-MHz crystal/clock

24-MHzclock Host processor

Sitara AM3359

Mag

netic

s

Status LEDs

RJ45 Port 2


Boot application firmware from SD-Card

Optional access DP83867IR registers through virtual COM port

Application firmware- IPv4 TCP/IP- UDP- IP address: 192.168.1.10- HTTP webserver example

TI DesignsEMI/EMC-Compliant Industrial Temp Dual-Port GigabitEthernet Reference Design

TI Designs Design FeaturesTI Designs provide the foundation that you need • EMI- and EMC-Compliant Design With Wide Inputincluding methodology, testing and design files to Voltage Range (17 to 60 V) Using Two DP83867IRquickly evaluate and customize the system. TI Designs Gigabit Ethernet PHYs and AM3359 Sitara™help you accelerate your time to market. Processor to Work in Harsh Industrial

EnvironmentsDesign Resources • Exceeds CISPR 11 / EN55011 Class A Radiated

Emission Requirement by > 4.3 dBDesign FolderTIDA-00204

• Exceeds IEC61800-3 EMC ImmunityDP83867IR Product Folder Requirements:LM46002 Product Folder

– ±6-kV ESD CD per IEC 61000-4-2AM3359 Product Folder– ±4-kV EFT per IEC 61000-4-4TPS65910A3 Product Folder

TPS51200 Product Folder – ±2-kV Surge per IEC 61000-4-5LMZ10501 Product Folder • Sitara AM3359 Firmware, Including UDP andTPS720 Product Folder TCP/IP Stack and HTTP Web Server Examples,TPS737 Product Folder Boots From Onboard SD-Card Allowing EasyTPD4E05U06 Product Folder Standalone OperationTPS717 Product Folder • Access to DP83867IR Registers Through USBTPD4S012 Product Folder Virtual COM Port Allows for Custom Specific PHY

Configurations Such as RGMII Delay Mode• Hardware Support for Start-of-Frame (SOF) DetectASK Our E2E Experts Allows Implementation of IEEE 1588 PTPWEBENCH® Calculator Tools

Featured Applications• Industrial Drives• Factory Automation and Control• Industrial Networks• Test and Measurement

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and otherimportant disclaimers and information.

All trademarks are the property of their respective owners.

1TIDU832A–March 2015–Revised April 2015 EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet ReferenceDesignSubmit Documentation Feedback

Copyright © 2015, Texas Instruments Incorporated

http://www.ti.com/tool/TIDA-00204

http://www.ti.com/product/DP83867IR

http://www.ti.com/product/LM46002

http://www.ti.com/product/AM3359

http://www.ti.com/product/TPS65910A3

http://www.ti.com/product/TPS51200

http://www.ti.com/product/LMZ10501



http://www.ti.com/product/TPD4E05U06


http://www.ti.com/product/TPD4S012

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http://e2e.ti.com/support/development_tools/webench_design_center/default.aspx

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JTAG/UART

Micro SD

24-V to 5-VDC/DC

Resetbutton

Mag

netic

s

Input: 24 V(17 to 60 V)

Micro USB

DDR3

Status LEDs


PHY1

DP83867IR RJ45


PHY2

DP83867IR


Gigabit PHY P/S

Port 1



Sitara AM3359

Mag

netic

s

Status LEDs

RJ45 Port 2





System Description www.ti.com

1 System Description

1.1 TI Design OverviewThis TI design supports dual-port Gigabit Ethernet communication through twisted pair copper cable asdefined in IEEE 802.3ab. It is designed to be evaluated for harsh industrial environment with regards tostandard compliance to CISPR 11 / EN55011 Class A radiated immunity requirements and EMC immunityrequirements for ESD according to 61000-4-2, fast transient burst (EFT) according to IEC61000-4-4, andsurge according to IEC61000-4-5.

The design implements dual-port Gigabit Ethernet using two DP83867IR Gigabit Ethernet PHYs, whichare connected through the Reduced Gigabit Media Independent Interface (RGMII) to AM3359 Sitaraprocessor with integrated Ethernet MAC and Switch. It offers a wide input voltage range from 17 to 60 Vwith nominal 24-V input voltage and meets industrial requirements for EMI and EMC.

For easy standalone operation, the host processor is configured to boot the pre-installed applicationfirmware from an onboard SD-Card. The application firmware implements a driver for the DP83867IR,UDP and TCP/IP stack, and HTTP web server examples, based on TI’s SYS/BIOS Industrial SDK and TI’sNetworking Development Kit NDK. A USB virtual COM port offers optional user access to read or write toDP83867IR registers for custom configurations like RGMII Delay Mode, if required. A JTAG interface onthe AM3359 provides the option for custom software development, test, and debug.

Therefore, this design allows for performance evaluation of two DP83867IR Gigabit Ethernet PHYs andAM3359 Sitara processor with integrated Ethernet MAC and Switch.

Figure 1. System Block Diagram of TIDA-00204

2 EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference TIDU832A–March 2015–Revised April 2015Design Submit Documentation Feedback


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www.ti.com System Description

1.2 Gigabit Ethernet OverviewEthernet has heavily expanded usage over the years. Ethernet became an attractive option for industrialnetworking applications. The opportunity to use open protocols (such as TCP/IP over Ethernet networks)help replace proprietary communications in industrial control and factory automation applications. Whenusing Ethernet, there are several speeds available today: 10 Mb/s, 100 Mb/s (Fast Ethernet), 1000 Mb/s(Gigabit Ethernet), and 10 Gb/s (10-Gigabit Ethernet).

Gigabit Ethernet uses the extended Ethernet MAC layer interface, connected through a Gigabit MediaIndependent Interface (GMII) layer to physical layer entities (PHY sublayers) such as 1000BASE-LX,1000BASE-SX, 1000BASE-CX, and 1000BASE-T. The topology for a 1000-Mb/s full-duplex operation iscomparable to the 100BASE-T full-duplex mode, and the minimum packet transmission time has beenreduced by a factor of ten. The resulting achievable topologies for the half-duplex 1000-Mb/s CSMA/CDMAC are similar to those found in half duplex 100BASE-T.

Table 1. Gigabit Ethernet Standards

IEEE STANDARD NAME MEDIUMIEEE 802.3ab 1000BASE-T Twisted-pair copper cable

1000BASE-SX Fiber optic cableIEEE 802.3z 1000BASE-LX Fiber optic cable

1000BASE-CX Twinax

As previously mentioned. this TI design is using twisted pair copper cables as defined IEEE 802.3ab.



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MDI_1+

MDI_1-

to RJ45to PHY 1:1


1.3 Gigabit Ethernet PHY Interfaces

1.3.1 Medium Dependent Interface: PHY Layer 1000BASE-TThe 1000BASE-T Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and basebandmedium specifications are intended for users who want a 1000-Mb/s performance over balanced twisted-pair cabling systems.

The 1000BASE-T PHY supports full-duplex baseband transmission through four pairs of minimum CAT5balanced cables. The 1000 Mb/s is achieved by transmitting through four wires pairs, each at 250 Mb/s.Using hybrids and cancellers enable full duplex transmission by allowing symbols to be transmitted andreceived on the same wire pairs at the same time. Baseband signaling with a modulation rate of 125 MBdis used on each of the wire pairs. The transmitted symbols are selected from a four-dimensional five-levelsymbol constellation (4D-PAM5). In the absence of data, idle symbols are transmitted.

The IEEE 802.3 specifies specify that a PHY with a MDI that is not a power interface (PI) should provideelectrical isolation between the port device circuits, including frame ground (if any) and all MDI leads. Thiselectrical isolation shall withstand at least one of the following electrical strength tests:• 1500 VRMS at 50 to 60 Hz for 60 s• 2250-V DC for 60 s• A sequence of ten 2400-V impulses of alternating polarity, applied at intervals of not less than 1 s

To meet this requirement transformers are typically used for isolation. The typical transformerconfiguration for 1000BASE-T can be seen in Figure 2 for a one differential pair.

Figure 2. Gigabit Ethernet Transformer (One out of Four Pairs)

Depending on the PHY device, parallel termination might be needed for each of the MDI differential signalpair. The termination impedance is typically 100 Ω differentially. Newer devices like the DP83867IRinclude integrated termination so no external termination resistors are required.



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www.ti.com System Description

1.3.2 Medium Independent Interface: MAC Layer InterfaceFor the MAC layer interface to the Gigabit PHY, there are three different options defined in the IEEE802.3ab standard: The standard Media Independent Interface (MII), the GMII, SGMII, or the RGMII.

1.3.2.1 GMIIThe purpose of GMII is to make various physical media transparent to the MAC layer. The GMII acceptseither GMII or MII data, control, and status signals and routes them either to the 1000BASE-T, 100BASE-TX, or 10BASE-T modules, respectively.

The GMII provides full-duplex operation and is an 8-bit wide transmit and receive data path interfaceclocked at 125 MHz defining speeds up to 1000 Mb/s. GMII is backwards compatible with the MIIspecification, thereby supporting 10 (2.5 MHz) and 100 (25 MHz) Mb/s speeds. Data and delimiters aresynchronous to clock references. It also provides a simple management interface.

The transmit signals are GTX_CLK, TX_CLK, TX_D[7:0], TX_EN, and TX_ER. The GTX_CLK signal issupplied to the PHY when it is operating in Gigabit mode. When this is done, the TX_D, TX_EN, andTX_ER are synchronized to the GTX_CLK signal. For a 10/100-Mb operation, the TX_CLK is supplied tothe MAC, and the TX_CLK signal is used to synchronize the signals (TX_D, TX_EN, and TX_ER). Thereceiver signals are RX_CLK, RX_D[7:0], RX_DV, RX_ER, COL, and CS. The GMII uses in total amaximum of 25 pins.

1.3.2.2 RGMIIThe RGMII is designed to reduce the number of pins required to interconnect the MAC and PHY (12 pinsfor RGMII relative to 24 pins for GMII). With this optimization, the RGMII consists of 12 signals: 6 signalsfor receive, which are RX_CTL, RX_CLK, RX_D[3:0], and 6 for transmit, which are TX_CTL,TX_CLK,TX_D[3:0]. To accomplish this, the data paths and all associated control signals are reduced andare multiplexed. Both rising and trailing edges of the clock are used. The TX_CTL and RX_CTL signalcarries data valid (DV) on the rising edge and DV XOR ERROR on the falling edge, for CTL signals thereis no change between 10/100Mb/s or 1000Mb/s operation.

For a Gigabit operation, the GTX_CLK and RX_CLK clocks are 125 MHz, and for 10- and 100-Mb/soperation, the clock frequencies are 2.5 MHz and 25 MHz, respectively.

1.3.2.3 SGMIIThe SGMII differs from the GMII and RGMII by having a higher clock frequency and the 8b/10b (SerDes)coded interface. It uses differential pairs at a 625-MHz clock frequency double data rate (DDR) for TX andRX data and for TX and RX clock. The transmit and receive path uses one differential pair for data and insome cases one for clock. TX and RX clocks must be generated on device output but are optional ondevice input. With revision 1.8 of the SGMII standard, clock recovery can be used, removing the need forthe clock signal. This means that the SGMII can be a 4- to 8-pin solution.

1.3.3 Serial Management InterfaceThe serial management interface (SMI) consists of a Management Data Clock (MDC) and a ManagementData Input/Output (MDIO) signal. It provides access to the PHY’s internal register space for statusinformation and configuration. The MDC and MDIO signals can be shared amongst several PHYs due tothe serial communication protocol, where an address is used to identify the corresponding PHY slave. TheMDIO has a standard set of registers from 0 to 31 each containing 16 bits. In IEEE 802ah clause 45, anextended register set was defined for extra functionality of the PHYs. The SMI is initially specified at a2.5-MHz clock.



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Processor

MAC

Ethernet PHY

OS

IEEE1588 code(Application layer)

4

3

2

1

Hardware assist


1.4 IEEE 1588v2Precise time information is important, especially for distributed systems like in factory automation. TheIEEE 1588v2 is an IEEE standard for precision clock synchronization protocol for networked measurementand control systems. The protocol is used to synchronize the time and clock frequency. It defines a way toprovide sub-microsecond precision synchronization.

To define this synchronization, the start of package detection is needed. Depending on which applicationlayer this detection happens, the timing error varies. The lower the layer, the smaller the error.

Figure 3. Options 1 to 4 for Time Stamp versus Layer

The closer to the PHY the time stamp is set the better the time reference. The time stamp consists of twosignals the Ingress (RX) and Egress (TX) time stamp. Depending on when the time stamp is done, thedelay can vary from nanoseconds to microseconds.



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www.ti.com Design Features

2 Design FeaturesThis design allows for performance evaluation of two DP83867IR Gigabit Ethernet PHYs and AM3359Sitara™ processors with an integrated Ethernet MAC and Switch. It meets industrial requirements for EMIand EMC, supports industrial temperature grade, and offers a wide input voltage range with a default of 24V.

To allow for easy standalone operation, the AM3359 Sitara boots the application firmware from SD-Card.The application firmware implements the driver for the DP83867IR, UDP and TCP/IP stack, and HTTPweb server examples and is based on TI’s SYS/BIOS Industrial SDK. An additional option is provided toaccess the DP83867IR Gigabit Ethernet PHY registers through USB virtual COM port. A JTAG interfaceoption is also provided to allow for custom software development with that board.

Table 2. TIDA-00204 Hardware Specification

FUNCTION INFO SPECIFICATION COMMENTNumber of ports 2MDI 1000BASE-T (copper)MAC interface RGMIIEMAC and switch Y Integrated with Sitara AM3359Status LED Y

Hardware enabled but notIEEE 1588v2 Y testedGigabit Ethernet IEEE 802.3abOption to place protection

Separate transformer and diodes on either side of theYRJ45 jack magnetics, used for testpurpose

SMI Y (2.5 MHz)Configurable PHY address Y Through strap resistors(SMI)Low power 565 mWIntegrated termination resistors Y

DP83867IRRGMII Delay Mode on RX/TX ProgrammableClock 25 MHz (< 50 ppm)Input voltage 24 V (17 to 60 V)Output voltage 5 V Intermediate voltage

850 mA (nominal), 1.2 AOutput currentPower (maximum)Indicator LED Y For 5 V, 3.3 V and 2.5 V

PMIC for AM3359, 3.3 V (I/O),Point of load for all ICs Y 2.5 V and 1.1 V for PHYsStandalone operation Boot from SD-Card interface Y

Read and write operation toUSB virtual COM port Access to PHY registers Y both registers of PHY

supportedJTAG JTAG header Y

Selected devices supportTemperature range Industrial –40°C to 85°C industrial temperature rangeEMI CISPR 11 / EN55011 Class A radiated emissions

IEC61000-4-2 ±4-kV ESD CD, Shielded Ethernet cableCriterion BIEC61000-4-4 ±2-kV EFT,EMC IEC61800-3 Shielded Ethernet cableCriterion B

IEC61000-4-5 ±1-kV Surge, Shielded Ethernet cable,Criterion B min 20 m



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Design Features www.ti.com

Table 3. TIDA-00204 Firmware Specification (AM3359)

FUNCTION INFO SPECIFICATION COMMENTBoot loader Boot application firmware from SD-Card Y

DDR3 memory Driver for DDR3 YUSB virtual COM port Driver for UART Y

PHY Driver for DP83867IR YRTOS TI SYS/BIOS Y

Based on TI’s AM335xIPv4 protocol support Y industrial SDK and NDKUDP and TCP/IPFixed IP 192.168.1.10

Based on TI’s AM335xHTTP Web server example Y industrial SDK and NDK



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JTAG/UART

Micro SD

24-V to 5-VDC/DC

Resetbutton

Mag

netic

s

Input: 24 V(17 to 60 V)

Micro USB

DDR3

Status LEDs


PHY1

DP83867IR RJ45


PHY2

DP83867IR


Gigabit PHY P/S

Port 1



Sitara AM3359

Mag

netic

s

Status LEDs

RJ45 Port 2





www.ti.com Block Diagram

3 Block DiagramFigure 4 shows the system block diagram. The major building blocks are the DP83867IR Gigabit EthernetPHY, the AM3359 Sitara Host Processor, and the power supplies.

Figure 4. System Block Diagram of TIDA-00204



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Strap (GPIO)

VDDIO

RHI

RLO

Circuit Design and Component Selection www.ti.com

4 Circuit Design and Component Selection

4.1 DP83867IR 10/100/1000-Mb/s Gigabit Ethernet PHYThe DP83867IR was selected due to following features:• IEEE 802.3ab 1000BASE-T compliant• Operating temperature range –40°C to 85°C• 8-kV IEC 61000-4-2 ESD protection (direct contact)• RGMII with software (register) programmable and hardware configurable (strap resistors) clock skew• Integrated termination resistors• Low power: 565 mW• SOF detect for IEEE 1588 time stamp

In addition to the above features, the DP83867IR also offers the following features:• Low deterministic TX and RX latency• Wake on LAN (WoL)• Synchronized clock output to synchronize multiple PHYs using one crystal (or clock)

4.1.1 DP83867IR Gigabit Ethernet PHY ConfigurationWhen configuring the DP83867IR, this can be done using either a SMI or a strap configuration through thefour-level strap pins. A pull-up resistor and a pull-down resistor of suggested values may be used to setthe voltage ratio of the four-level strap pin input and the supply to select one of the possible selectedmodes. The device should feature four-level strap pins, each supporting at least four selectable options,as shown in Figure 5 and Table 4. Strap resistors with 1% tolerance are recommended.

Figure 5. Strap Circuit

Table 4. Four-Level Strap Resistor Ratios

MODE RESISTOR RHI (kΩ) RESISTOR RLO (kΩ)1 OPEN OPEN2 11 2.493 6.04 2.494 2.49 OPEN

Because this design employs two DP83867IR, the SMI will have two DP83867IR slaves addresses. Thismeans that the SMI address of the two DP83867IR have to differ to ensure a valid communication. To setthe DP83867IR SMI address a strap configuration option can be used on one DP83867IR to change thedefault address from 0x00. In this design, it was chosen to use the pin RX_D4 to set the SMI address, asthis pin is not used for the RGMII.



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LED

_1

LED

_0

VDDIO

GND

Mod

e 4

Mod

e 1

2.49 N��

470 ��

470 ��

RGMII2_RXD0

RGMII2_RXD1

RGMII2_RXD2

RGMII2_RXD3

RGMII2_RXCLK

RGMII2_RXCTRL

GND

PHY2_RX1588

PHY2_TX1588

Vddio

Vddio

Orange

12

D12

0

R510

R500

R470

R460

R440

R43

560R60

11.0kR49

GND

11.0k

R59

2.49kR62

Vddio

GND

11.0k

R56

2.49kR61

2.49kR57

RGMII2_RXCTRL_R

RGMII2_RXCLK_R

RGMII2_RXD0_R

RGMII2_RXD1_R

RGMII2_RXD2_R

RGMII2_RXD3_R

RESERVED1

RESERVED7

RESERVED9

RESERVED16

RX_CLK43

RX_D044

RX_D145

RX_D246

RX_D347

RX_D4/GPIO48

RX_D5/GPIO49

RX_D6/GPIO50

RX_D7/GPIO51

RX_DV/RX_CTRL53

RX_ER/GPIO54

COL/GPIO55

CRS/GPIO56

DP83867IRPAPR

www.ti.com Circuit Design and Component Selection

A strap configuration option was chosen so the RGMII is always enabled to ensure the RGMII is enabledwhen as the RX_D6 pin is used as input pin on the AM3359 Sitara processor.

As the clock out option of the device is not used by default, RX_D7 strap configuration option was done todisable the clock out of the device. This feature is default on if this strap on is not done and if it needs tobe disabled without strap configuration. It would have to be done using the SMI.

Figure 6. Schematic for DP83867IR Strap Configuration on ETH2

Table 5. DP83867IR Strap on Resistor Chosen

DP83687IR PIN NAME CONFIGURATION MODERX_D4 Strap resistors 2 (PHY_ADD4 = 1, only ETH2)RX_D6 Strap resistors 2 (RGMII enable)RX_D7 Strap resistors 2 (Clock out disable)

When using the strap configuration on a specific pin, ensure that the additional function mapped to this pinis applicable. For example, due to this the TX_D0 to TX_D3 and RX_D0 to RX_D3 pins, which are usedby the RGMII, have not been used for strap configuration. This is because this strap resistor configurationwould have needed to be compensated with trace matching from the other RGMII pins used. Anotherexample is the LED indicator pins: When used with both LED functionality and strap configuration, takecaution on how to connect the LED with regards to the strap resistors. An example for strap mode 0 andstrap mode 4 with indicator LED is shown in Figure 7.

Figure 7. Example Strap Connections With Indicator LEDs for Mode 1 and Mode 4



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4.1.2 MAC Layer InterfaceThe MAC interface of this design was chosen according to minimum number of pins at lowest possibleclock frequency. See Table 6 of the pin definitions.

Table 6. MAC Interface Option Pinout for the Different Standards

DECISION CRITERION GMII RGMII SGMIINumber of MAC interface signals 24 12 4 or 8Clock frequency 125 MHz 125 MHz 625 MHz

With those considerations, the choice was to use the RGMII as it is running at a lower frequency than theSGMII. Therefore, the RGMII allows for easier PCB routing of the signals, and the number of signals isacceptable.

The RGMII signals are not differential but single-ended, and they are referenced to a clock signal of125 MHz. It is crucial that length matching is done properly for all signals to avoid skew due to differentpropagation delay between the clock and the data signals.

For this design, the following length matching was done on the RGMII signals.

Table 7. DP83867 RGMII Trace Length on TIDA-00204 PCB

RGMII SIGNAL TX LENGTH (mm) RX LENGTH (mm)PHY1 CLK 29.9925 29.9984

PHY1 CTRL 29.9944 29.9937PHY1 D0 29.9902 29.9941PHY1 D1 29.9650 29.9918PHY1 D2 29.9860 29.9918PHY1 D3 29.9994 29.9918

PHY2 CLK 32.4950 32.4993PHY2 CTRL 32.4659 32.5294

PHY2 D0 32.4924 32.4958PHY2 D1 32.4877 32.4989PHY2 D2 32.4937 32.4990PHY2 D3 32.4676 32.4990

Here, it can be seen that the PHY1 RGMII traces are length matched with a maximum length difference of0.034 mm, and for PHY2 with a maximum difference of 0.064 mm.

Additional considerations are to place each PHYs RGMII TX and RX on the same layer and add seriestermination resistors close to the corresponding output pins. Because the DP83867IR has an integrated50-Ω series impedance, a 0-Ω series termination has been placed at the DP83867 RGMII RX output pins.This was a test and debug option and the termination resistor (array) can be removed in a productiondesign.

A 22-Ω series termination resistor was placed close to the RGMII1 and RGMII2 TX pins of the AM3359Sitara.



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D1+1

D1-2

NC6

NC7

NC9

NC10

D2+4

D2-5

GND3

GND8

U9

TPD4E05U06DQA

Green

12

D6

MDIO_CLK_1

MDIO_DATA_1

GND

GND

D1+1

D1-2

NC6

NC7

NC9

NC10

D2+4

D2-5

GND3

GND8

U7

TPD4E05U06DQA

PHY1_TD_A_P

PHY1_TD_A_N

PHY1_TD_B_P

PHY1_TD_B_N

PHY1_TD_C_P

PHY1_TD_C_N

PHY1_TD_D_P

PHY1_TD_D_N

PHY1_TD_A_P

PHY1_TD_A_N

PHY1_TD_B_P

PHY1_TD_B_N

GND

GND

PHY1_TD_C_P

PHY1_TD_C_N

PHY1_TD_D_P

PHY1_TD_D_N

PHY_RESETn

PHY1_INTPWDN

PHY1_CLKOUT

2

3

4

1

5

6

7

8

9

10

11

12

J4

43202-8916

Yellow

12

D4Red

12

D5

GND

V18phy

V11phy

PHY1_X_D_P

PHY1_X_D_N

PHY1_X_C_P

PHY1_X_C_N

PHY1_X_B_N

PHY1_X_B_P

PHY1_X_A_P

PHY1_X_A_N

75.0

R24

75.0

R22

75.0

R32

75.0

R37

PHY1_EARTH

1000pFC33

PHY1_EARTH

PHY1_TD_A_P

PHY1_TD_A_N

PHY1_TD_B_P

PHY1_TD_B_N

PHY1_TD_C_P

PHY1_TD_C_N

PHY1_TD_D_P

PHY1_TD_D_N

GND

10.0k

R21

560R25

22

R35DNP

1.00M

R36

560R26

560R27

0.1µF

C27

0.1µF

C28

0.1µF

C29

0.1µF

C30

GND

PHY1_TD_A_P

PHY1_TD_A_N

PHY1_TD_B_N

PHY1_TD_B_P

PHY1_TD_C_P

PHY1_TD_C_N

PHY1_TD_D_P

PHY1_TD_D_N

4.7k

R23

0

R17DNP

0

R18DNP

1000pFC26

1000pFC25

GND

GND

27pFC31

27pFC32

GND GND GND

4.7k

R29Vddio

TCT11

TD1+2

TD1-3

TCT24

TD2+5

TD2-6

TCT37

TD3+8

TD3-9

TCT410

TD4+11

TD4-12

MX4-13

MX4+14

MCT415

MX3-16

MX3+17

MCT318

MX2-19

MX2+20

MCT221

MX1-22

MX1+23

MCT124

T1

HX5008FNL

1 2

25 MHz

Y1

ABM3-25.000MHZ-D2Y-T

1000pF

C34

DNP

GND PHY1_EARTH

TD_P_A2

TD_M_A3

TD_P_B5

TD_M_B6

TD_P_C10

TD_M_C11

TD_M_D14

TD_P_D13

RBIAS15

MDC20

MDIO21

INT/PWDN60

RESET59

XI19

XO18

CLK_OUT22

JTAG_CLK25

JTAG_TDO26

JTAG_TDI28

JTAG_TRSTN24

LED_261

LED_162

LED_063

VDDA1P817

VDDA1P864

VDD1P18

VDD1P129

VDD1P142

VDD1P158

GND65

JTAG_TMS27


4.1.3 Interface From PHY to RJ-45The transformer used in the MDI connection provides DC isolation between local circuitry and the networkcable. The center tap of the isolated winding has a "Bob Smith" termination through a 75-Ω and a 1000-pFcapacitor-to-chassis ground. The termination capacitor should be voltage rated to at least 2 kV. The BobSmith termination reduces noise resulting from common mode current flows.

NOTE: A TVS diode has been placed each between the DP83867IR and the transformer and thetransformer and the RJ45 jack. This was a test and debug option only and the positionbetween the DP83876IR and the magnetics showed slightly better results in EMC and EMI,as shown in Figure 8.

Figure 8. Schematic of Media Dependent Interface of ETH1

The trace length that needs to be considered is from RJ45 to magnetic and from magnetic to DP8867IR,for these signals they are differential pairs. This means that the signals needs to be routed differentially aslong as possible without making the traces longer than necessary. To ensure data integrity, the trace’sdifference should be below 10 mil (0.254 mm).

Table 8. Differential Signal Trace Length From PHY to Magnetic and Magnetic to RJ45 Jack

MEDIA DEPENDENT INTERFACE RJ45 TO MAGNETIC (mm) MAGNETIC TO DP8867IR (mm)PHY1 Differential pair A (N,P) 13.0123 (N), 13.0708 (P) 10.0302 (N), 10.0302 (P)PHY1 Differential pair B (N,P) 13.1709 (N), 13.3115 (P) 10.0223 (N), 10.0223 (P)PHY1 Differential pair C (N,P) 13.1321 (N), 13.0146 (P) 10.0175 (N), 10.0082 (P)PHY1 Differential pair D (N,P) 13.0804 (N), 13.0003 (P) 10.0163 (N), 10.0163 (P)PHY2 Differential pair A (N,P) 12.9469 (N), 13.0056 (P) 13.3910 (N), 13.4938 (P)PHY2 Differential pair B (N,P) 12.9398 (N), 13.0815 (P) 13.1988 (N), 13.1047 (P)PHY2 Differential pair C (N,P) 13.0899 (N), 13.0409 (P) 13.0679 (N), 13.1622 (P)PHY2 Differential pair D (N,P) 13.1864 (N), 13.1063 (P) 13.3252 (N), 13.2272 (P)



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1

2

3

4

5

U11SN74AHC1G08DCK

GND

SYS_RESETn

PHY_RESETn

GND

GPIO_PHY_RESETn

Vddio

10.0kR38

0.01µF

C35


To ensure no unnecessary stubs, all traces are routed on the top layer. The only exception is the pinsD2_P and D2_N. Due to the RJ45 jack pin assignment without integrated transformer, this differential pairchanged the layer to minimize the overall differential trace length of the four pairs.

Table 9. RJ45 Connector Pinout

PIN SIGNAL PIN SIGNAL1 D1_P 5 D3_N2 D1_N 6 D2_N3 D2_P 7 D4_P4 D3_P 8 D4_N

4.1.4 DP83867IR Input Clock SelectionFor the input clock, either a crystal or an external clock source can be used. For both cases, the clockneeds to be 25 MHz with a tolerance of less than ±50 ppm. For more details, refer to the DP83867IRdatasheet, Sections 8.2.1.2 and 8.2.1.3 [1]. For this design, a 25-MHz crystal was chosen (see Section 4.4for more details).

The DP83867IR has a clock out pin CLK_OUT too. This allows to route the 25-MHz clock from oneDP83867IR PHY to the second DP83867IR PHY and eliminates the need for a crystal at the second PHY,reducing costs. The TIDA-00204 design has been prepared for this configuration by adding series 0-Ωresistors.

4.1.5 Power and Ground PinsFor each of the three power rails on the DP83867IR, decoupling capacitors are recommended as follows.A 1-nF capacitor is recommended be placed close to each supply pin of the DP83867IR. A 10-nF and a10-µF capacitor are recommended per supply rail.

4.1.6 PHY RESETThe DP83867IR PHYs are automatically reset after power-up, through signal SYS_RESETn. Additionally,the DP83867IR hardware reset signal PHY_RESETn can be issued by the Sitara AM3359 GPIO pin withthe signal GPIO_PHY_RESETn, which offers a software option to reset the PHYs if needed.

Figure 9. PHY Reset Option During Power Up (SYS_RESETn) and Software Reset (GPIO_PHY_RESETn)



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GND

SYS_BOOT15

SYS_BOOT14

SYS_BOOT13

SYS_BOOT12

SYS_BOOT11

SYS_BOOT10

SYS_BOOT9

SYS_BOOT8

SYS_BOOT7

SYS_BOOT6

SYS_BOOT5

SYS_BOOT4

SYS_BOOT3

SYS_BOOT2

SYS_BOOT1

SYS_BOOT0

Vaux2

10kR83

DNP10kR84

10kR85

DNP10kR86

DNP10kR87

DNP10kR88

DNP10kR89

DNP10kR90

DNP10kR91

DNP10kR92

DNP10kR93

DNP10kR94

10kR95

10kR96

10kR97

DNP10kR98

DNP

100kR101

100kR102

DNP100kR103

100kR104

100kR105

100kR106

100kR107

100kR108

100kR109

100kR110

100kR111

100kR112

DNP100kR113

DNP100kR114

DNP100kR115

100kR116


4.1.7 Not Connected Pins on DP83867

Table 10. DP83867IR Not Connected Pins

PINS REASONTXD4:7 Internal pull-downTX_ER Internal pull-down

TX_CLK OutputCOL Internal pull-downCRS Internal pull-down

Reserved ReservedJTAG (TDI, TMS, TCLK) Internal pull-up

JTAG (TDO) Output

4.2 Host ProcessorThe Sitara AM3359 was chosen as it has a 2-Gb Ethernet MAC with switch layer supporting RGMII toboth DP83867IRs. The MAC switch layer inside the AM3359 is supporting several features of passingmessages from one PHY to the other without the use of the core. To achieve deterministic and very lowtransmit and receive latency, the ICSS/PRU subsystem can be used to capture the start of frame for IEEE1588 time stamp. The TIDA-00204 hardware is provisioned for this feature but not tested.

4.2.1 AM3359 Boot Mode ConfigurationThe AM3359 internal ROM code selects the corresponding peripheral based on the level of the SYSBOOTconfiguration at power on reset of the device. For the full details of this boot procedure, read Sections26.1.5 to 26.1.8 of the Technical Reference Manual of the AM335x Sitara processors.

For easy standalone operation, the AM3359 has been configured to boot from MMC1/SD-Card. Thisconfiguration requires the SYSBOOT[15:0] pins to be "0100 0000 0001 1100". This is achieved by settingthe corresponding pull-up and pull-down resistors as per the schematics in Figure 10.

Figure 10. AM3359 SYSBOOT Pin Configuration for MMC1/SD-Card Boot Mode



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4.2.2 AM3359 GPIO Pin AssignmentWhen using the Sitara before starting the design, ensure that the peripherals functions required for thedesign can be assigned to the specific GPIO pins without a mux conflict. For this purpose, there is a pinmux tool utility for TI processors called PINMUXTOOL-V3. The tool can be downloaded from the TIwebsite (www.ti.com). There are specific versions pending the device, part, and package. This tool is ahuge help for AM3359 pin assignment.

This design uses the following peripherals: EMAC with RGMII1 and RGMII2, UART, MMC0 and MMC1,MDIO, SDRAM/DDR3, I2C, and ECAP.

The pin mux tool was used to find the optimum pin assignment for the different peripherals used in theTIDA-00204 reference design.

Table 11. AM3359 Pin Assignment

SIGNAL PINS (GPIO MODE) AMOUNT OF PINSRGMII1 J16-J18, K15-K18, L15-L18, M16 (Mode 2) 12RGMII2 R13-14, V14-V17, U14-U16, T14-T16 (Mode 2) 12UART G15-G16(Mode 3) 2MMC U9, V9 (Mode 2), U7, V7, R8, T8 (Mode 1) 6MDIO M17-M18 (Mode 0) 2JTAG Fixed pins not available with mux 8 to 11

SDRAM (DDR3) Fixed pins not available with mux 52I2C C16-C17 (Mode 0) 2

ECAP U13 (Mode 5), C15 (Mode 2), C18 (Mode 0), E15 (Mode 4) 4

The remaining pins could be used in GPIO mode or assigned to unused peripherals on the AM3359device.



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IO11

IO22

IO33

NC4

GND5

IO46

IO57

IO68

NC9

VCC10

U18

TPD6E001RSER

MMC1_CLK

MMC1_CMD

MMC1_DAT0

MMC1_DAT1

MMC1_DAT2

MMC1_DAT3

GND

Vmmc

Vmmc

GNDDAT2

1

CD/DAT32

CMD3

VDD4

CLK5

VSS6

DAT07

DAT18

S313

S414

S19

SW11

CD10

S212

J6

502774-0891

MicroSD_case

GND

10kR120

10kR121

10kR122

10kR123

10kR124

10kR125

0.1µFC203

10µFC202

0.01µF

C205

0.1µF

C206

MicroSD_caseGND


4.2.3 MMC1 Micro SD-CardFigure 11 shows the micro SD-Card interface including ESD protection device on the TIDA-00204. TheTPD6E001 is a low-capacitance ±15-kV ESD-protection diode array designed to protect sensitiveelectronics attached to communication lines. Each channel consists of a pair of diodes that steer ESDcurrent pulses to VCC or GND. The TPD6E001 protects against ESD pulses up to ±15-kV human-bodymodel (HBM), ±8-kV contact discharge (CD), and ±15-kV air-gap discharge, as specified inIEC 61000-4-2.

Figure 11. MMC1 Micro SD-Card Interface With ESD Protection

4.2.4 I2C Communication to PMIC and EEPROMThe I2C module 0 is used for communicating with both, the EEPROM, and the Power Management IC(PMIC). The PMIC I2C is hardcoded to the I2C address equal to 0101101 binary or 0x2D in hex.

The EEPROM was given the binary address 1010000 equal to 0x50 in hex. This is done by setting the A2,A1, and A0 pin. This then forms the 7-bit address as "1010A2A1A0".



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4.2.5 DDR3 RAMFor this design, the MT41J128M16JT-125K TR DDR3 RAM was chosen to leverage experience from theTI AM3359 Industrial Communications Engine development platform with part number TMDSICE3359.This memory requires a 1.5-V supply with a rise time better than 200 ms. During this time a VTT supplyneeds to be provided as this rail is a system supply for signal termination resistors. Once powered, thedevice needs to be reset before going into the initialization state. Then the memory is ready for operation.

Due to the speed of the signals to the DDR3 RAM, length matching and termination are important toensure performance. For the data lines, length matching was done by defining different net classes withspecific considerations. The concept of defining different net classes is important when routing high speedsignals, as they can insure timing constraints or timing relationships. When defining these groups, it isimportant to understand the basics of the DDR3 memory signals. For DDR3, the signals can be dividedinto four different groups that have similar requirements.

Table 12. DDR3 Net Class Definitions

NET CLASS SIGNALSData DDR_D[15:0],DDR_DQM[1:0], DDR_DQS0[_P and _N], DDR_DQS1[_P and _N]

Address/Command DDR_A[13:0],DDR_BA[2:0], DDR_CASN, DDR_RASN, DDR_WENControl DDR_CKE, DDR_CSN, DDR_ODT, DDR_RESETNClock DDR_CLK_N,DDR_CLK_P

For the different groups, it is possible with either software or hardware to shift the sampling point. Evenwith this feature of DDR3 RAM, it is still needed to do a timing budget calculation. With this calculation, itis possible to have an estimation of how the length matching needs to be. Length matching is needed dueto the fact that the typical propagation delay for the FR4 PCB is approximately 6.5 ps/mm and so a lengthmismatch would lead to a delay of the signal compared to the other signal lines. As an example the netclass data has been matched as seen in Table 13.

Table 13. DDR3 Trace Length on PCB for Net Class Data

SIGNAL TRACE LENGTH (mm) SIGNAL TRACE LENGTH (mm)DDR_D0 27.4776 DDR_D8 25.3669DDR_D1 27.6777 DDR_D9 25.2680DDR_D2 27.4567 DDR_D10 25.4147DDR_D3 27.2947 DDR_D11 25.6113DDR_D4 27.4070 DDR_D12 25.6584DDR_D5 27.5413 DDR_D13 25.3574DDR_D6 27.4398 DDR_D14 25.5648DDR_D7 27.3044 DDR_D15 25.4486

DDR_DQM0 27.3479 DDR_DQM1 25.4907DDR_DQS0_N 27.4755 DDR_DQS1_N 25.4209DDR_DQS0_P 27.4726 DDR_DQS1_P 25.4285



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Termination was done with parallel termination of 47 Ω to improve performance. Arrays were chosen hereto minimize size.

Further general considerations are:• All nets in the address and command fly-by groups shall have the same number of vias in each length-

matched segment. Ground vias are placed to ensure a proper current return path. Minimize use of viason signal traces as they negatively impact signal integrity.

• The single-ended Address/Command net class and the control net class needs external termination toVTT.

• For the data net class within a byte lane, the data bits can be swapped to simplify routing.• Organize the power, ground, and signal planes to eliminate or significantly reduce the number of split

or cut planes present in the design (no splits are allowed under any DDR3 routes).• Maintain an acceptable level of skew across the entire DDR3 interface (by net class).• It is strongly recommended that all nets be simulated to assure proper design, performance, and signal

integrity.• Take into account the differences in propagation delays between microstrip and stripline nets when

evaluating timing constraints. All long routes should be stripline to reduce EMI and timing skew, andany microstrip routed for BGA breakouts should be as short as possible.

• Routes along the same path and routing segment must have the same number of vias. Vias can beblind, buried, or HDI microvia for improved signal integrity, but are not required for standard data rates.Similarly, back drilling vias is not required for standard data rates but can be used to eliminate viastubs.

• For this design, the DDR3 layout was copied from the TI AM3359 Industrial Communications Enginedevelopment platform with part number TMDSICE3359 to leverage a working and fully tested designwith the peripheral settings for the DDR3 interface.

4.2.6 AM3359 Clocking OptionsFor the clock, either a crystal or a digital clock source can be used. For both cases, the clock needs to be19.2, 24, 25, or 26 MHz with a tolerance of ±50 ppm. For more details, see Section 6.2.2 of the AM3359datasheet [5]. For this design, a 24-MHz crystal was chosen as used with the TMDSICE3359 AM3359Industrial Communications Engine development platform.

4.2.7 Power Supply PinsFor the decoupling capacitors on the different power rails of the AM3359, see Section 5.9 of the AM3359datasheet [5].



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4.2.8 USB Virtual COM Port and JTAG InterfaceAn FTDI chip connects to a micro USB port. This FTDI chip can be used for both JTAG (XDS100) andVirtual COM port functionality. A separate JTAG header is available too.

To use the FTDI chip, the onboard EEPROM, which is connected to the FTDI chip, needs to beprogrammed as follows:• To program the EEPROM connected to the FTDI chip, get the tool "Mprog". To find this tool, go to the

following webpage for the download link.http://processors.wiki.ti.com/index.php/XDS100#How_to_make_an_XDS100

• The EEPROM needs to be programmed in a specific way. To find an example image also called a*.ept file to write in the EEPROM, go to the following webpage:http://processors.wiki.ti.com/index.php/XDS100

A .ept file for the Mprog tool is available for the specific XDS100 version needed. Download a .ept file,which includes both JTAG and Virtual COM port functionality.

To verify the image is programmed correctly, power the board and connect the micro USB to the PC. Nowgo into the start menu and open the menu Devices and Printers for Windows® 7. The following connectionshould now be found (see Figure 12).

Figure 12. XDS100v2 Driver in Windows 7 Devices and Printers Menu

If Figure 12 does not appear, retry the previous steps.

When this is done properly, Code Composer Studio™ v6 can be used to connect to the AM3359 corethrough JTAG using the XDS100v2 driver.



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SW1

SW2

CBOOT3

VCC4

BIAS5

SYNC6

RT7

PGOOD8

FB9

AGND10

SS/TRK11

EN12

VIN13

VIN14

PGND15

PGND16

PAD17

U1

LM46002PWPGND GND GND

GND

GND

GND

GND

4.7µFC13

GNDGND

8.2pFC14

L2

MSS1260-153MLB

GND

453kR2

1.00MR6

249kR7

100kR4

0.022µFC12DNP

0402 footprint

10µFC1

10µFC2

10µFC3

1µFC10

10µFC11

0.47µF

C4

80.6kR5

DC/DC 5 V: LM46002

Host processorVrtc: TPS71718

PMIC: TPS65910A3

Gigabit PHY rails2v5: LMZ105011v1: TPS72011

DDR3 termination regulator

TPS51200

5 V

Enable signal

Gigabit PHY I/O rail 3v3: TPS73733

24-V input

Enable signal

Stage 1

Stage 2Stage 3


4.3 Power SuppliesThe power supplies are realized in three stages. The first stage is a 24-V to 5-V DC/DC to provide anintermediate 5-V rail to the other two stages. The second stage is a PMIC supplying the host processor,and the last stage is supplying the two Gigabit PHYs.

Figure 13. TIDA-00204 Power Supply Stages

4.3.1 24-V to 5-V DC/DC Buck ConverterFor this stage, the LM46002 SIMPLE SWITCHER® regulator was chosen. It is an easy-to-usesynchronous step-down DC-DC converter capable of driving up to 2 A of load current from an inputvoltage ranging from 3.5 to 60 V. The LM46002 provides exceptional efficiency, output accuracy, anddrop-out voltage in a very small solution size. The family requires few external components. Pinarrangement allows for a simple, optimum PCB layout.

An extended family is available in various load current options with pin-to-pin compatible packages,including LM46001.

The schematic of the LM46002 is shown in Figure 14.

Figure 14. Schematic of 24-V to 5-V DC/DC Buck Converter With LM46002



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RIPPLEL peak OUT

II I

2-

= +

( )OUT

RIPPLE

2 sw

INV V DI

L F

- ´=

´

IN OUT OUTmi

In

sw OUT sw OUT

N(V V ) D (V V ) DL

0.4 F I 0.2 F I

- ´ - ´

£ £

´ ´ ´ ´

5

sw

40200R 0.6

F= -


4.3.1.1 Passive Components CalculationsThe first step is to decide and set the switching frequency of the regulator. In the TIDA-00204, theswitching frequency (FSW) is set to 500 kHz thanks to R5. Equation 1 indicates that R5 should be 79.8 kΩ.80.6 kΩ is then used as value for R5.

(1)

with• FSW in kHz and R5 in kΩ

The default frequency is also 500 kHz, due to the internal oscillator precision of 20% it was chosen to usea resistor for the 500-kHz frequency. This gives a 10% precision. Secondly, during EMI test it can beuseful for fine tuning to move the frequency up or down to change the harmonic spectrum of theconverter.

Once the switching frequency is set, the size of inductance needed it chosen. For most buck converters,this value is chosen to achieve the wanted peak-to-peak ripple current that flows in the inductor along withthe DC load current. A higher inductance gives lower ripple current, which then gives a lower outputvoltage ripple with the same output capacitors. An inductance that gives a ripple current of 20% to 40% atthe maximum current is normally a good starting point. The minimum inductor value is calculated basedon input voltage range (17 to 60 V), output voltage (5 V), maximum output current (2 A) and the switchingfrequency (500 kHz) as set in the previous step. The duty cycle (D) can be approximated as D = VOUT/VIN,assuming no loss power conversion.

(2)

The calculation gives that the inductor needs to be between 9 and 23 μH; for this design, 15 μH waschosen.

Besides the inductor size, the rated saturation current needs to be specified as per Equation 4.

(3)

(4)

The inductor peak current is 2.305 A according to Equation 3 and Equation 4. A good practice is to use aninductor with the saturation current around 1.5 to 2 times higher than calculated.

The LM46002 has both valley current limit and peak current limit. During an instantaneous short, the peakinductor current can be high due to a momentary increase in duty cycle. The inductor current rating shouldbe higher than the peak current limit. Select an inductor with a larger core saturation margin andpreferably a softer roll off of the inductance value over load current.

In general, it is preferable to choose lower inductance in switching power supplies, because it usuallycorresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But atoo low inductance can generate too large inductor current ripple such that over current protection at thefull load could be falsely triggered. It also generates more conduction loss because the RMS current isslightly higher relative that with lower current ripple at the same DC current. Larger inductor current ripplealso implies larger output voltage ripple with the same output capacitors. With peak current mode control,it is not recommended to have too small of an inductor current ripple. Enough of an inductor current rippleimproves the signal-to-noise ratio on the current comparator and makes the control loop more immune tonoise.



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14X 6 6 7

1 1C

2 F R (R || R )= ´

´ p ´ ´

X

OUT OUT

4.35f

V C=

´

FB7 6

OUT FB

VR R

V V= ´

-

( )sw OUT

1 D 1ESR 0.5

F C r

- æ ö< ´ +ç ÷´ è ø

( )( ) ( ) ( )( )OUT

sw OUT OUT

1 rC 1 1 D 1 D 1 r

F r V / I 12

æ öæ ö> ´ ´ + - + - ´ +ç ÷ç ÷´ ´ D D è øè ø


The maximum desired output voltage ripple and the transient response to load changes are theparameters to take into account for selecting the value of the output capacitors.

(5)

with• ΔIOUT equal load current (2 A)• ΔVOUT equal target output voltage undershoot (0.5 V)• r the inductor ripple ratio (ΔIL/IOUT)

Equation 5 indicates that COUT should be higher than 10.0 μF. A general guideline would be to pick COUTbetween the minimum required output capacitance, calculated in Equation 6, and multiply this minimumrequired capacitance by 10. Two 10.0 μF in parallel were chosen to fit the COUT requirements.

The second requirement is the maximum ESR of the capacitor, which can be found using Equation 6.

(6)

Equation 6 calculates the maximum ESR of the output capacitor to meet the maximum output ripplerequired. The equivalent ESR of the output capacitors C3 and C4 should be lower than 0.288 Ω.

The LM46002 requires high quality ceramic (X5R or X7R) input decoupling capacitors. The recommendedvalue is between 4.7 to 10 μF. A good practice for ceramic capacitors is to choose a voltage rating oftwice the maximum input voltage. If the placement of the LM46002 additional bulk capacitance is needed,this additional capacitor dampens voltage spikes caused by the lead inductance of the trace. The value isnot critical but it must be rated to fit the voltage requirements.

The output voltage is externally adjusted with a resistor divider network. The divider network is comprisedof top feedback resistor R6 and bottom feedback resistor R7. Equation 7 is used to determine the outputvoltage of the converter.

(7)

R6 is chosen to be 1 MΩ to minimize quiescent current, which improves light load efficiency in thisapplication. With the desired output voltage set to be 5 V and the VFB is equal to 1.01 V, the R7 value canthen be calculated using Equation 7. The equation gives the value 253.4 Ω. The chosen value for thisdesign is a 249-kΩ resistor. For more details on the adjustable output voltage, see the LM46002datasheet [11].

The LM46002 is internally compensated and the internal R-C values are 400 kΩ and 50 pF, respectively.Depending on the VOUT and the frequency FS, if the output capacitor COUT is dominated by low ESR(ceramic types) capacitors, it could result in low-phase margin. To improve the phase boost, an externalfeed forward capacitor C14 can be added in parallel with R6. C14 is chosen such that the phase margin isboosted at the crossover frequency without C14. A simple estimation for the crossover frequency withoutC14 (FX) is shown in Equation 8.

(8)

The following equation for C14 was tested:

(9)

Equation 9 indicates that the crossover frequency is geometrically centered on the zero and polefrequencies caused by the C14 capacitor.

For designs with higher ESR, C14 is not needed. When COUT has medium ESR, C14 calculated fromEquation 9 should be reduced. With Low ESR used the calculated value. Table 2 of the LM46002datasheet can be used as a starting point. The calculated value is 8.2 pF, and an 8.2-pF COG capacitorwas selected for C14.



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( )4 2

UVLO Rising ENH4

R RV V

R-

+= ´

UVLO Falling2 4

ENL

VR 1 R

V

-æ ö= - ´ç ÷

ç ÷è ø

12 ssc ssC I t= ´


The LM46002 needs a bootstrap capacitor C4. The recommended bootstrap capacitor is 0.47 μF and ratedat 6.3 V or higher. The bootstrap capacitor must be a high quality ceramic type with X7R or X5R gradedielectric for temperature stability.

The VCC pin is the output of an internal LDO for the LM46002. The input for this LDO comes from eitherVIN or bias. To ensure stability of the part, place a minimum of a 2.2-μF, 10-V capacitor from this pin toground.

For an output voltage of 3.3 V or higher, the BIAS pin can be connected to the output in order to increaseefficiency. This pin is an input for the VCC LDO. When BIAS is not connected, the input for the VCC LDO willbe internally connected into VIN. Because this is an LDO, the voltage differences between the input andoutput will affect the efficiency of the LDO. If necessary, a capacitor with the value of 1 μF can be addedclose to the BIAS pin as an input capacitor for the LDO.

The soft start capacitor (C12) determines the minimum amount of time it will take the output voltage toreach its programmed value during start up. This also allows limiting the inrush current in the LM46002(current require to charge the output capacitors to the programmed value). If this pin is left unconnected,the soft start time is 4.1 ms typically. Longer soft start times can be set by an external soft start capacitorper Equation 10.

(10)

with• C12 equal the soft start capacitor value (μF)• ISSC the soft start charging current (μA)• tSS equals the desired soft start times

The ISSC current is 2.2 μA, defining a soft start time of 10 ms would equal a soft start capacitor of 0.022 μF.

The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R2 and R4. R2 isconnected between the VIN pin and the EN pin of the device. R4 is connected between the EN pin and theGND pin. The UVLO has two thresholds: one for power up when the input voltage is rising, and one forpower down or brown outs when the input voltage VIN is falling. Use Equation 11 to determine theVUVLO-Falling level.

(11)

The enable falling edge threshold (VENL) for the LM46002 is 1.8 V. R4 was chosen to 100 k to minimizeinput current from the supply. If the desired VIN UVLO falling level is 10 V, the value of R2 can becalculated using Equation 12. That is equal to 455.6 k. R2 was chosen to be 453 k.

(12)

The enable rising edge threshold (VENH) for the LM46002 is 2.1 V. Equation 12 can be used to calculatethe required input voltage to meet the rising threshold to enable the converter. With the above chosenresistors, the LM46002 will enable at 11.6 V.



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Gigabit PHY rails2v5: LMZ105011v1: TPS72011

5 V

Enable signal

Gigabit PHY I/O rail 3v3: TPS73733

Enable signal


4.3.2 Power Supply for Two Gigabit Ethernet PHYsThe PHY power supplies need to provide three power rails. The 3.3-V VDDIO power rail is sequenced fromthe 3.3-V PMIC rail (see Section 4.3.2.1). When the VDDIO power rail is enabled, it will enable theremaining two rails 2.5 V and 1.1 V as seen in Figure 15. The information on the power consumption ofthe Gigabit Ethernet PHY can be seen in Section 6.5 of the DP83867IR datasheet [1].

Figure 15. Power Stage for Two Gigabit Ethernet PHYs

4.3.2.1 DP83867IR Current ConsumptionThe DP83867IR has two power options. One option requires two rails for the core and one rail for theVDDIO. In this setup, the PHY draws 565 mW. For the two-rail option, no sequencing is required. If powerdissipation on the DP83867IR is critical, the second option uses three rails for core and one rail for VDDIO.In this setup, the PHY draws 545 mW. VDDIO can be 3.3, 2.5, or 1.8 V. See its datasheet for more detailson the current consumption per rail and if a voltage other than 3.3 V is used in the VDDIO rail [1].

Table 14. Power Consumption per Voltage Rail

RAIL STANDARD POWER MODE (565 mW) LOW POWER MODE (545 mW)1.1 V 106 mA 106 mA1.8 V N/A 64 mA2.5 V 157 mA 103 mA

VDDIO (3.3, 2.5, or 1.8 V) 31 mA (1.8 V) 31 mA (1.8 V)

For this design, the power supply was designed for the two-rail standard power mode option to fit twoDP83867IR PHYs.

The TPS72011 and LMZ105001 were chosen for the 1.1-V rail and the 2.5-V rail, respectively.

For the VDDIO 3.3 V, the TPS73733 was chosen. This rail is also used as supply rail for other interfaces onboard (for example, for the Gigabit Ethernet PHY LEDs and VDDIO voltage rail, the EEPROM, the debug orJTAG circuitry, reset circuitry, and additional pull up resistors for data communication lines).

These parts were chosen because of their feature of industrial temperature range –40°C to 85°C and thatthey could dissipate the needed power at 85°C. Here it is important to choose the correct package of thedevice; several other part numbers could fit the electrical specification. However, their package would notbe able to dissipate the needed power at the full current and temperature range. Knowing the voltage dropacross the LDO and the power dissipation at 85°C, the maximum current that can be dissipated for thedecided voltage rail can be calculated.

Table 15. 3.3-V and 1.1-V LDO Power Dissipation per Package

MAX POWERDISSIPATIONINPUT OUTPUT VOLTAGE MAX CURRENTDEVICE AT 85°C RɵJAVOLTAGE VOLTAGE DROP AT 85°CAMBIENT

TEMPERATURETPS72011DRV 2.5 V 1.1 V 1.4 V 615 mW 65 K/W 439.29 mATPS73733DCQ 5 V 3.3 V 1.7 V 790 mW (1) 53.1 K/W 464.71 mA (1)

(1) Estimated power dissipation and max current at 85°C using junction-to-ambient thermal resistance.



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OUT

16 14

OUT

VR R

5.875 V V

æ ö= ´ç ÷

ç ÷-è ø

IN1

OUT2

3

NR4

EN5

6

GND

U2

TPS73733DCQ

EN1

VCON2

FB3

SGND4

VOUT5

PGND6

VIN7

VREF8

PAD9

U3

LMZ10501SIL

V5_dc

GND

GND

GND

GND

1µFC16

OUT1

NC2

EN3

BIAS4

GND5

IN6

PAD7

U5

TPS72011DRV

GND

GND GND

V25phy

V11phy

Vddio

Vddio

Vaux2

V5_dc

0

R9

0R15

0R8

0

R12

150kR14

0.1µFC24

0.1µFC22

0.1µFC15

470pFC21

10µFC17

10µFC18

2.2µFC23

110kR16

0R8


The 2.5-V rail at LMZ10501 was chosen due to the fact that an LDO with the current needed would be avery expensive device and would dissipate a significant amount of power. When two PHYs are poweredapproximately 526 mA is required, with margin the 1-A LMZ10501 was chosen.

Figure 16. Schematic of Power Supply for Two DP83867IR Gigabit Ethernet PHYs

Use Equation 13 to calculate the output voltage for the LMZ10501.

(13)

R14 needs to between 80 and 300 kΩ and R16 can be calculated. R14 has to be minimum 80 kΩ to ensurethat the VREF output current loading is not greater than 30 μA and the reference voltage is maintained. Thisdesign needed a 2.5-V output voltage and the R14 was decided to be 150 kΩ and the R16 is now calculatedto 111.1 kΩ. A 110-kΩ resistor was chosen. A small filter capacitor of 470 pF with a voltage rating of 6.3 Vor 10 V is connected in parallel to R16. The input and output capacitors are recommended to be X5R orX7R.



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4.3.3 Power Stage for AM3359 Host ProcessorThe power stage for the AM3359 Sitara is realized using the PMIC TPS65910A3 and a DDR3 terminatorregulator TPS51200. An additional TPS71718 LDO is used for the RTC circuit of the Sitara, as theTPS65910A3 RTC circuit has been turned off.

The TPS65910A3 can be configured through I2C, this interface can be used to set internal registers of thePMIC. For more details on these registers, see the TPS65910A3 user's guide. The TPS65910A3 have thefollowing power sources that can be used, each of the power supplies can be programmed to work atseveral voltages. For the TPS65910A3, there are several boot modes depending on the device that needsto be powered. Because the AM3359 is used, the EEPROM sequence has been chosen boot[1:0] = "10".For more information on this topic, see Section 10.

Table 16. TPS65910A3 Default Voltage Rails per "10" EEPROM Sequence

RAIL NAME TYPE VOLTAGE OPTIONS DEFAULT VOLTAGE POWERVIO SMPS 1.5, 1.8, 2.5, or 3.3 V 1.5 V 1000 mA

0.6 to 1.5 V in 12.5-mV stepsVDD1 SMPS Programmable multiplication factor: ×2, ×3 1.1 V 1500 mA

1.1 V0.6 to 1.5 V in 12.5-mV steps

VDD2 SMPS Programmable multiplication factor: ×2, ×3 1.1 V 1500 mA1.1 V

VDD3 LDO 5 V or OFF N/A 100 mAVDIG1 LDO 1.2, 1.5, 1.8, or 2.7 V 1.8 V 300 mAVDIG2 LDO 1, 1.1, 1.2, or 1.8 V 1.8 V 300 mAVPLL LDO 1.0, 1.1, 1.8, or 2.5 V 1.8 V 50 mAVDAC LDO 1.8, 2.6, 2.8, or 2.85 V 1.8 V 150 mAVAUX1 LDO 1.8, 2.5, 2.8, or 2.85 V 1.8 V 300 mAVAUX2 LDO 1.8, 2.8, 2.9, or 3.3 V 3.3 V 150 mA

VAUX33 LDO 1.8, 2.0, 2.8, or 3.3 V 3.3 V 150 mAVMMC LDO 1.8, 2.8, 3.0, or 3.3 V 3.3 V 300 mAVRTC LDO 1.8 V or OFF OFF OFF

The TPS51200 is used for the DDR3 ram as the sink/source termination regulator. The DDR memorytermination structure determines the main characteristics of the VTT rail, which is to be able to sink andsource current while maintaining acceptable VTT tolerances. The VTT accuracy has a direct impact on thememory signal integrity, it is imperative to understand the tolerance requirements on VTT. The terminationcurrent demand of the DDR3 is less than 1 A of burst current. The TPS51200 ensures the regulator outputvoltage to be between VTTREF – 25 mV < VTT < VTTREF + 25 mV.



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XI CLK_OUT

XO

XI

XO CLK_OUTCXCY

25 M

Hz

25 MHz

DP83867IR (PHY 1) DP83867IR (PHY 2)

X Y L SC C 2 (C C )= = ´ -


4.4 System ClocksThere are several options to apply the clocks. For systems with distributed clocks, a clock distributioncircuit can be used too. The initial design leverages a crystal on each DP83867IR as well as on AM3359Sitara. This was due to initial test and debug to allow individual component testing.

4.4.1 Individual CrystalsThe crystal manufacturers define the load capacitance of their crystal in their datasheet. This loadcapacitance CL is the sum of the PCB parasitic stray capacitance CS and the external load capacitors CXand CY, respectively, as per Equation 14. Assuming that the external load capacitors are the same value,they can be calculated with Equation 14.

(14)

CS is the stray capacitance (device and PCB) this value can be assumed to a few pF as a rule of thumb.

The load capacitors need to be NPO/COG type. Table 17 shows the selected load capacitors per crystaland per device on the TIDA-00204.

Table 17. Parallel Capacitors Needed for Oscillation Circuit

CRYSTAL DEVICE CL CS CX = CY

ABM3-25.000MHZ-D2W-T DP83867IR 18 pF 4 pF 27 pFABM3-24.000MHZ-D2W-T AM3359 18 pF 4 pF 27 pFABM3-12.000MHZ-D2Y-T FT2232HL 18 pF 4 pF 27 pFMC-306 32.7680K-A0:ROHS AM3359 (RTC) 12.5 pF 3 pF 19 pF

In this design, the default configuration is one crystal at each DP83867IR PHY. However, the hardware isprepared thanks to 0-Ω resistors to clock the second DP83867IR PHY from the PHY 1, as shown inFigure 17. If desired, this configuration can be tested.

Figure 17. Crystal Configuration for DP83876IR and Option to Clock the Second DP83867IR PHY From theFirst DP83867IR



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PCB top view PCB bottom view (flipped)

Step 1: Remove the oscillator circuitry used for the two DP83867 PHYs and the AM3359 Sitara as shown in the picture.

Step 2: Place CDCE913 and its supporting components on bottom side, between the PHYs and close to AM3359. This allows short routing distances.

XX

X

25 MHzLVCMOS

24 MHzLVCMOS

to AM3359 Sitara

25 MHzLVCMOS

to DP83867IR PHY 2CDCE913

to DP83867IR PHY 1


4.4.2 Clock Distribution CircuitsAlternatively to the XTAL clocking as implemented on the TIDA-00204 reference design, a more advancedclocking solution is possible. The following section describes how this could be implemented.

Replace XTALs of the PHY and Sitara chips with a CDCE913 clock generator. If the layout allows, alsoadditional clocks on the board could be derived from the clock generator. The CDCE9xx device family isavailable with various output and PLL counts.

The yields several advantages in general:• Smaller component area used for clocking• Possibility to enable spread spectrum (SSC)• Potentially lower cost• Possibility to extend easily

Figure 18 shows how a CDCE913 could be connected and used to provide three reference LVCMOSclocks.

Figure 18. CDCE913 Clock Distribution Circuit Example

This new clocking source could be used to change the component floor plan as shown in Figure 19 withan Altium 3-D PCB simulation.

Figure 19. PCB Component Area Saving With a CDCE913 Clock Generator



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Start

ROM boot from MMC1

micro SD card

Load app file from micro SD card

Launch application ³DSS´

Software Design www.ti.com

5 Software Design

5.1 Sitara AM3359 FirmwareThe goal of the software design was to provide an example application firmware for evaluating GigabitEthernet, which boots from micro SD-Card automatically after the TIDA-00204 is powered. The applicationfirmware implements a driver for the DP83867IR, UDP and TCP/IP stack, and HTTP web serverexamples. A USB virtual COM port offers optional user access to read or write to DP83867IR registers forcustom configurations like RGMII Delay Mode, if required.

5.1.1 Functional OverviewThe host processor Sitara AM3359 is configured to boot from MMC1/SD-Card. The AM3359 copies theTIDA-00204 example application binary file app from the SD-Card to DDR3 RAM and launches theexample application. The flowchart of the SD-Card boot load process is shown in Figure 20.

Figure 20. AM3359 Boot Load Process From MMC1 Micro SD-Card



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Init EMAC, Ethernet Switch,

and UART

Ethernetthread

UARTthread

Init SYS/BIOS and setup UART and Ethernet threads

Start SYS/BIOS

Start

www.ti.com Software Design

The TIDA-00204 example application app consists of three major functional blocks.

The first part initializes the AM3359 peripherals like the Ethernet MAC, Ethernet Switch (CPWS), andUART. Then, the app initializes SYS/BIOS and sets up a UART task thread as well as an Ethernet taskthread. After that, the app starts SYS/BIOS. Then, both the UART thread and the Ethernet thread arescheduled and run accordingly.

Figure 21. AM3359 Initialization

The Ethernet thread initializes the configuration registers of both DP83867IR Gigabit PHYs through SMI.For example, set RGMII mode, autonegotiation, indicator LEDs, and more. Then the thread enables thenetwork layer with fixed IPv4 address 192.168.1.10 and TCP and UDP transport layer. Additionally, aHTTP web server example application is included.

The UART thread enables communication through virtual COM port and offers and additional option toread and write to the individual registers of the DP83867 Gigabit PHYs through SMI. For example, theuser can adjust the RGMII Delay Mode according to the specific hardware, if desired.



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Enable UART access to both

DP83867 devices

Yes

Read register of selected PHY

Select DP83867 PHY MDIO

address

Enter DP83867 PHY Register

address and data

UARTthread

No

Enter specific register address

Write data to DP83867 PHY

register address

Select all addresses0x00 to 0x1F

Print selected register addresses

with data

No

Yes

Port 1 cable connected?

Yes

No

Autonegotiate Ethernet

Ethernet link

Port 1 cable Disconnected

Yes No

Init PHY1 and PHY2 with MDIO interface

GigabitEthernetthread

Port 2 cable connected?

YesAutonegotiate

EthernetEthernet link

Port 2 cable Disconnected

No

No

Yes

Init HTTP

Init IPv4 with static IP192.168.1.10

Init TCP and UDP

Cable connected

Yes

No

Thread

Thread


The flowcharts of both threads are shown in Figure 22 and Figure 23.

Figure 22. AM3359 Gigabit Ethernet Thread Flowchart Figure 23. AM3359 UART Thread Flowchart



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5.1.2 Software ComponentsThe "TIDA-00204 SD-Card Image" consists of two binary files. The AM3359 boot loader binary file called"MLO" and the example application binary file called "app", as described in Section 5.1.1. Both binarieswere compiled in separate CCS 6 projects.

5.1.2.1 "MLO" Binary FileThe TIDA-00204 boot loader binary file "MLO" was developed with the Texas InstrumentsAM335x_SYSBIOS_Industrial_SDK_01_01_00_06 software package. This example project was modifiedto the TIDA-00204 hardware with boot from MMC1/SD-Card. The binary file was renamed aftercompilation to MLO to fit the AM3359 ROM boot loader and is part of theTIDA-00204_Firmware_AM3359_SD-Card_Image.

5.1.2.2 "app" Binary FileThe TIDA-00204 example application binary file app was developed with the following Texas Instrumentssoftware packages:• AM335x_SYSBIOS_Industrial_SDK 01_01_00_06:

http://downloads.ti.com/sitara_indus/esd/AM335x_SYSBIOS_Industrial_SDK/latest/index_FDS.html• SYS/BIOS 6_40_03_39: http://software-

dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_40_03_39/exports/bios_setupwin32_6_40_03_39.exe

• XDCtools 3_30_05_60: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/rtsc/3_30_05_60/index_FDS.html

• NDK 2_24_00_11: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ndk/2_24_00_11/index_FDS.html

• NSP 1_10_02_09 Product Download Page: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ndk/nsp_1_10_02_09/index_FDS.html

The example application uses only a few example projects including the source and header files.



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http://downloads.ti.com/sitara_indus/esd/AM335x_SYSBIOS_Industrial_SDK/latest/index_FDS.html

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_40_03_39/exports/bios_setupwin32_6_40_03_39.exe



http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/rtsc/3_30_05_60/index_FDS.html

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/rtsc/3_30_05_60/index_FDS.html

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ndk/2_24_00_11/index_FDS.html

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ndk/2_24_00_11/index_FDS.html

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ndk/nsp_1_10_02_09/index_FDS.html

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ndk/nsp_1_10_02_09/index_FDS.html



5.1.3 Creating the Micro SD-Card ImageTo create the TIDA-00204_Firmware_AM3359_SD-Card_Image to boot the demo application firmwarefrom the micro SD-Card, the following equipment is required:• A pre-formatted micro SD-Card with FAT file system• A PC with a micro SD-Card reader• Win32 Disk Imager installed on PC

Copy the MLO and app binary file to the micro SD-Card. After that, invoke the Win32 Disk Imager. See anexample of the program shown in Figure 24.

Figure 24. Procedure to Create SD-Card Image With Win32 Disk Imager

Select Read to write the current inserted micro SD-Card into the name image in this example called"test.img". This image was renamed to TIDA-00204_SD-Card_Image_rev1_0 and then included into theTIDA-00204 software package.

5.2 PC Test Software for UDP Packet Transfer Based on TI’s NDKThe tests for the Gigabit Ethernet communication path developed with the Texas Instruments NDK2_24_00_11 software package. From this software package, the following source file was used:• c:\ti\ndk_2_24_00_11\packages\ti\ndk\winapps\testudp.c

For more information on the testudp files, see Section 2.2.3.3 of the NDK document [8].

With original executable testudp.exe, the utilization was around 1%, which was below the needs for thisdesign; therefore, modification was done. The original source was modified adding hyper threading toenable higher utilization. To compile the source file, MinGW was used.

NOTE: To use the hyper threading on a Windows PC, add libwinpthread-1.dll in the same directoryas the executable. The library file libwinpthread-1.dll can be downloaded from the internet.

With hyper threading, 25% utilization was achieved on a single Gigabit Ethernet port and 20% each incase of on dual Gigabit Ethernet port 1 and port 2.

Two variants were generated as explained in the following two sections.



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Receive UDP packet Close thread

Start

Enable Ethernet socket for UDP

Initialize payload with size of 1472 bytes

Send UDP packet to socket

Increase packet counter by 1

Print to consolenumber of packets sent,

time elapsed

Print to console packet counter

Stop UDP packet

transfer

Yes

No

Open thread

Stop

Packetcounter and

0xFFFF = 0?

Yes


5.2.1 UDP Throughput TestThe example UDP test file is called "TIDA-00204_UDP_throughput_test.exe". The software flow of thethroughput example code can be seen in Figure 25.

Figure 25. Flowchart of UDP Throughput Test Software

Figure 26 is an example console output can be seen of the example UDP throughput test software.

Figure 26. Command Prompt UDP Throughput Print



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Start software

Enable Ethernet socket for UDP

Setup predefined packet and size of

packet to send

Send UDP packet to socket;

Increase packet counter by 1

Receive UDP from

TIDA-00204

Compare send and received packet and

count errors

Stop UDP packet

transfer

No

Print to consolenumber of packets sent, time elapsed, total errors

Stop

Print to console packet counter

Print to console error counter

Packetcounter and

0x3FFF = 0?


5.2.2 UDP Packet Error TestThe example UDP test file is called "TIDA-00204_UDP_throughput_test.exe". Figure 27 shows thesoftware flow of the throughput example code can be seen.

Figure 27. Flowchart of UDP Packet Error Test Software

The above example verifies, if the echoed back packets were corrupted. This functionality is neededcheck the signal integrity of the connection. Note that with this functionality enabled on the PC, theutilization of the Gigabit Ethernet connection was 5%.

An example console output of the example UDP packet error test can be seen in Figure 28.

Figure 28. Command Prompt UDP Packet Error Test Print



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24-V to 5-V DC/DC LM46002

Host processorAM3359 Gigabit Ethernet PHY

DP83867IR

PHY P/S2v51v1

Jumpers:J1: 5 V enable J3: PHY P/S enable

Port 1

Port 2MicroSD-card

24-V input

Gigabit Ethernet PHYDP83867IR

Reset button

Ethernet status LEDs

Ethernet status LEDs

LEDs (supply rails)D2 (5 V)D3 (2.5 V)D14 (3.3 V)

Micro USB virtual COM port

www.ti.com Getting Started

6 Getting Started

6.1 PCB OverviewA picture of the PCB with key functional blocks is shown in Figure 29.

Figure 29. TIDA-00204 PCB Picture With Key Functional Blocks

6.2 How to Run the BoardThe next sections show the prerequisites and the steps to quickly start using the board.

6.2.1 PrerequisitesThe following hardware equipment and software is required.

Table 18. Prerequisites

HARDWARE EQUIPMENT OR SOFTWARE REQUIREMENTS24-V output power brick with at least a 250-mA output current24-V power supply Output connector 2.1-mm I.D. × 5.5-mm O.D. × 9.5-mm Female

PC PC or Laptop with USB port and Gigabit Ethernet portEthernet cable Recommended CAT7 twisted pair cableMicro USB cable N/AMicro SD-card Big enough to fit the micro SD-card TIDA-00204 image

Download from web, or use any other terminal program of yourTeraTerm v4.76 or newer choiceWin32 Disk Imager v0.9.5 or newer Download from webXDS100 v2 PC USB driver To get this driver, install CCS 6.xTIDA-00204 software package Download from the TIDA-00204 web pagelibwinpthread-1.dll Download from web



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Getting Started www.ti.com

6.2.2 Jumper Settings

CAUTIONThe following two jumpers need to be set: J1 and J3.

The J1 jumper powers the host processor power stage and the J3 jumper enables the Gigabit EthernetPHY power supply.

6.2.3 Prepare the Micro SD-CardFor easy standalone board operation, a micro SD-Card image is provided. The example image on the SD-Card is configured so the AM3359 reads the boot loader MLO from the micro SD-Card and enables theSitara AM3359 in a mode. The Sitara AM3359 enables the needed peripherals to communicate with thetwo PHYs over the MDI and sets those PHYs in autonegotiate 10/100/1000 mode. It also enables a UARTfunctionality where one can read out the PHY registers from the two DP83867 devices over virtual COMport.

Write the image "TIDA-00204_SD-Card_Image_rev1_0.img" to a micro SD-Card. Use Win32 Disk Imagerto write the image to the SD-Card (see Figure 30).

Figure 30. Win32 Disk Imager Image Showing the Write Function

Select the provided TIDA-00204 firmware image and click Write to flash the image to the micro SD-Card.

CAUTIONEnsure that the micro SD-Card is selected at the Device tab.

If the image is not being written with the onboard PC SD-Card slot, try using an external SD-Card reader.

CAUTIONIf the micro SD-Card is not prepared like above, but the individual binary filesMLO and app are copied to a preformatted micro SD-Card it might be that theAM3359 does not boot properly. For further details on this topic, see theSection 26.1.7.5.2 of the AM335x technical reference manual [6].



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6.2.4 Powering the TIDA-00204 Reference DesignInsert the micro SD-Card with TIDA-00204 firmware image into the TIDA-00204 micro SD-Card cage.

Connect a 24-V power supply with at least a 250-mA output current. After that, the three green LEDs (D2,D3, and D14) will turn on. If the LEDs does not turn on, one of the jumpers J1 and J3 are not connected.

Connect the micro USB cable from the TIDA-00204 reference design to the PC. Now the XDS100 v2 PCUSB driver is installed on the PC. If PC does not find this driver, install CCS 6 to get the driver.

Invoke a terminal program, like TeraTerm that can connect to the virtual COM port. Setup the terminalprogram in Serial Console Mode and set the parameters as seen in Table 19.

Table 19. Terminal Program Serial Console Configuration

BAUD RATE DATA PARITY STOP FLOW CONTROL115200 8-bit None 1-bit None

Afterwards, press the reset button on the board. For the location of the reset button, see Figure 29.

Now on the terminal program, the boot sequence of the TIDA-00204 reference design is printed. SeeFigure 31 for terminal program printout.

Figure 31. Virtual COM Port Connection During Boot



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6.3 Evaluating the TIDA-00204 Dual-Port Gigabit Ethernet Reference DesignWith the board powered up, the next step is to connect the Ethernet link partner.

Connect a link partner to either port 1 or port 2, depending on the link partner autonegotiate will setup10/100/1000 network capability. Now the Ethernet LEDs will light up showing link status and Ethernetspeed.

The status LEDs have the following functionality see Table 20.

Table 20. DP83867 Gigabit PHY Port 1 and Port 2 Status LED Configuration

LED # D7 / D12 D4 / D9 D5 / D10 D6 / D11Not assigned to a Receive or transmit 1000-Mb linkFunction specific function on Link establishedactivity establishedTIDA-00204

The status LEDs are explained from left to right when looking at the board picture.

The reference design is setup to use the IP address 192.168.1.10, that is a static IP. It does not haveDHCP function enabled.

Setup the PC Network connection for static IP in the same address range as the TIDA-00204 referencedesign with subnet mask 255.255.255.0. For example: 192.168.1.30.

To test the Ethernet connection there are several options: ping, provided UDP test software and a HTTPweb server. See examples below.

All Gigabit Ethernet examples demonstrated on both port 1 and port 2.

6.3.1 PingWith the command prompt, the windows ping function can be used for initial connection test, seeFigure 32.

Figure 32. Command Prompt Ping Print



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6.3.2 UDP Test SoftwareThe two PC test programs as part of the TIDA-00204 software package can be used.

Insure that the libwinpthread-1.dll is located in the same folder as the TIDA-00204_throughput_test.exeand TIDA-00204_packet_test.exe. This library can be downloaded from the internet.

To invoke these programs, use a Windows PC with the command prompt, see Figure 33 and Figure 34 forexample print outs.


Figure 34. Command Prompt UDP Packet Error Test Print



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6.3.3 HTTP Web Server ExampleOpen a browser and enter this address: http://192.168.1.10. See Figure 35 for a screenshot of theTIDA-00204 webpage.

Figure 35. TIDA-00204 HTTP Web Server Example



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6.3.4 Access to DP83867IR Registers Through USB Virtual COM PortThe virtual COM port connection can be used to read and write to both DP83867IR registers through SMI.With this, it is possible to configure the DP83867IR registers in a different configuration than default foradditional test options.

CAUTIONAll inputs are in decimal and all outputs are in hexadecimal.

Figure 36 shows an example screenshot for a register read from DP83867IR on Ethernet port 2.

Figure 36. Virtual COM Port Connection for DP83867IR (ETH1) Register Read

To find the Gigabit Ethernet PHY DP83867IR register addresses, see the DP83867IR datasheet [1].



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Test Results www.ti.com

7 Test ResultsFor the TIDA-00204 tests, the following test equipment was used:

Table 21. Test Equipment for the TIDA-00204 Gigabit Ethernet Signal Integrity Tests

TEST EQUIPMENT PART #24-V power brick V-Infinity 3A-621DN24

Power supply Knürr-Heinzinger Polaris 125-5Gigabit Ethernet adapter for PC Digitus – USB 3.0 Ethernet adapter

PC Latitude E6540 with Windows 7 64-bitEthernet cable DRAKA UC900 super screen 27 CAT7 with a CAT6A connector

Tektronix TDS794D, P6339A probesOscilloscope Tektronix TDS2024B, P2220 probesElectronic load Chroma 63103 with Chroma 6314

Multimeter FLUKE 179

7.1 Gigabit Ethernet Signal Integrity Tests

7.1.1 RGMII SignalsThe RGMII signals between the MAC and the PHY are tested with a 1000-Mb connection on both PHY1and PHY 2 RX and TX. Figure 37 through Figure 40 show the clock signal and corresponding RX_D1 andTX_D1 data signal. The other data signals D0, D2, and D3 were measured too and exhibited the samewaveforms. This was expected because the design was optimized for impedance and matched length ofthe clock and data lines.

Figure 37. ETH1 RGMII RX Clock and Data Signal During Figure 38. ETH1 RGMII TX Clock and Data DuringGigabit Ethernet Connection Gigabit Ethernet Connection



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www.ti.com Test Results

Figure 39. ETH2 RGMII RX Clock and Data Signal During Figure 40. ETH2 RGMII TX Clock and Data Signal DuringGigabit Ethernet Connection Gigabit Ethernet Connection

7.1.2 Serial Management Interface (SMI)The maximum clock frequency of the SMI of the Sitara AM3359 is 2.5 MHz. This test does not need tohave an Ethernet connection running. Figure 41 and Figure 42 show the two signals MDC (Clock) andMDIO (I/O) between the Sitara AM3359 and the two DP83867IR for Gigabit Ethernet ETH1 and ETH2.

Figure 41. SMI Clock and Data Signal at 2.5 MHz at Figure 42. SMI Clock and Data Signal at 2.5 MHz atDP83867IR ETH1 DP83867IR ETH2



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Input Voltage (V)

Out

put V

olta

ge (

V)

10 20 30 40 50 604.5

4.6

4.7

4.8

4.9

5

5.1

5.2

5.3

5.4

5.5

D001Load Current (mA)

Out

put V

olta

ge (

V)

500 600 700 800 900 1000 1100 12004.5

4.6

4.7

4.8

4.9

5

5.1

5.2

5.3

5.4

5.5

D002


7.2 Power Supply Tests

7.2.1 24-V to 5-V DC/DC Power SupplyThe LM46002 was configured in this design to work with an input voltage range between 17 and 60 V.

The nominal load current was defined for the following configuration. The Sitara AM3359 running at600 MHz executing the application code from DDR3, with both DP83867IR connected in Gigabit Ethernetmode with continuous UDP packet transfer at 20% network utilization on both ports. The minimum loadcurrent is set to 500 mA, the nominal load to 850 mA, and the maximum load to 1.2 A.

Three tests where done: Output voltage versus input voltage (Figure 43), output voltage versus loadcurrent (Figure 44), and the output voltage ripple (Figure 45).

Figure 43. Output Voltage (VOUT) at 850 mA Nominal Load Figure 44. Load Regulation: VOUT at 24-V Input Voltage atCurrent With Varying Input Voltage (VIN) Varying Loads

Figure 45. VOUT Output Voltage Ripple at 850 mA Load Current and 24-V VIN Input Voltage



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7.2.2 Power Supply for the DP83867IR Gigabit Ethernet PHYs TestsThe voltages have been verified as shown in Table 22. The startup of the 3v3, 2v5, and 1v1 rails areshown in Figure 46.

Table 22. Measured Voltage Rails of the Gigabit Ethernet PHY

SUPPLY NAME PER SCHEMATICS SPECIFIED VOLTAGE MEASURED3v3 3.3 V 3.31 V2v5 2.5 V 2.47 V1v1 1.1 V 1.10 V

Figure 46. PHY Power Supply Voltage Rails During Startup



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7.2.3 PMIC for Sitara AM3359 Host ProcessorThe TPS65910A3 output voltages were verified and compared against the expected voltages based onthe TPS65910A3 EEPROM pin configuration.

Table 23. Measured Voltages on the PMIC TPS65910A3

SIGNAL EXPECTED VOLTAGE MEASURED VOLTAGEVIO 1.5 V 1.52 V

VDD1 1.1 V 1.11 VVDD2 1.1 V 1.11 VVDD3 OFF N/AVDIG1 1.8 V NC. VDIG1 pin was not connected in this design.VDIG2 1.8 V 1.81 VVPLL 1.8 V 1.82 VVDAC 1.8 V 1.80 VVAUX1 1.8 V 1.82 VVAUX2 3.3 V 3.31 V

VAUX33 3.3 V 3.33 VVMMC 3.3 V 3.32 VVRTC OFF N/A

The sequencing has not been tested. Please see TPS65910Ax User's Guide For AM335x Processors forfurther details [7].



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7.3 Gigabit Ethernet Functional TestsThe following functions have been tested: autonegotiate, ping, UDP transfer, and web server.

Table 24. Functional Tests of TIDA-00204 Reference Design

FUNCTION TEST RESULTAutonegotiate PASS

Ping PASSUDP PASS

Web server PASS

7.3.1 AutonegotiateTesting the autonegotiate is done using a network connection which can be programmed into a specificautonegotiate condition. Doing this ensures that the link negotiated is not going into a default settingdefined in the IEEE 802.3ab standard. This can happen if one partner of the link is forced and the other isset to autonegotiate.

The default autonegotiate setting of the DP83867IR is set 10/100/1000-Mb half- or full-duplex mode. TheDP83867IR recognizes the data rate supported by partner and sets the highest data rate supported byboth.

Table 25 shows the different autonegotiate mode results.

Table 25. DP83867IR Autonegotiate Mode Test Results

LINK PARTNER SPEED LINK PARTNER DUPLEX LINK CONNECTIONDP83867IR SETTING MODE SETTING MODE SETTING ESTABLISHED10/100/1000 Full duplex 1000 full duplex10/100/1000 Half duplex 1000 half duplex

10/100 Full duplex 100 full duplexAutonegotiate: 10/100/1000 fullduplex or half duplex 10/100 Half duplex 100 half duplex

10 Full duplex 10 full duplex10 Half duplex 10 half duplex



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7.3.2 PingPing is invoked from the command prompt using the TIDA-00204 static IP address 192.168.1.10.Figure 47 presents a command prompt printout that shows the ping test.

Figure 47. Command Prompt Ping Print

Wireshark was used to log the packet transfer during the ping test. In Figure 48, the Wireshark printoutresult can be seen.

Figure 48. Wireshark Log of TIDA-00204 Ping Test



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7.3.3 UDPThe UDP throughput test is invoked from the command prompt using the TIDA-00204 static IP address192.168.1.10. Figure 49 presents a command prompt printout that shows the UDP throughput test.


Windows Task Manager networking was used to log the packet transfer utilization during the UDPthroughput test. Figure 50 shows the Windows Task Manager printout.

Figure 50. Utilization of One Port Connection With UDP Throughput Test Running

With the throughput test file, it is possible to achieve around 25% utilization of the Gigabit bandwidth. Theslight change in the utilization on the curve is due to other network or CPU tasks.

When running this test on both ports simultaneously, the utilization will be 20% on each port.

For the UDP packet error test, the utilization is 5% independent of how many ports are connected, whichis a limitation of the UDP packet error test software running on the PC.



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7.3.4 HTTP Web ServerTo test the HTTP web page example, the TIDA-00204’s static IP address http://192.168.1.10 is enteredinto a browser (see Figure 51).

Figure 51. HTTP Web Server Example

For this test, Wireshark was used to log the traffic generated by initializing the web server and the loadingof the page.

Figure 52 shows the traffic log from Wireshark.

Figure 52. Wireshark Log of TIDA-00204 HTTP Web Server Example



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7.4 EMC/EMI Test ResultsThe TIDA-00204 TI design has been tested for EMI according to CISPR 11 / EN55011 Class A radiatedemissions. For EMC immunity, the design has been tested according to IEC61800-3 and IEC61000-6-2 forESD, EFT, and Surge with reference to standards IEC61000-4-2, IEC61000-4-4, and IEC61000-4-5,respectively.

The design is compliant to these standards and exceeds the voltage requirements according toIEC61800-3 EMC immunity requirements. A summary is shown in the following tables and more details inthe following sections.

Table 26. CISPR 11 / EN55011 Class A Radiated Emission Requirements for Category 2 andMeasured Level

REQUIREMENTS TIDA-00204 MEASUREMENTSCategory 2 electric field

Phenomenon Basic standard strength component quasi- Measured minimum margin to limit Testpeak dB (µV/m)

CISPR 11 / EN55011 Class 40 (30 to 230 MHz) Horizontal: 10.6 dB (125 MHz)EMI PASSA 47 (230 to 1000 MHz) Vertical: 4.3 dB (125 Mhz)

Table 27. IEC61800-3 and IEC61000-6-2 EMC Immunity Requirements for Second Environment andMeasured Voltage Levels and Class

REQUIREMENTS TIDA-00204 MEASUREMENTSPerformanceBasic PerformancePort Phenomenon Level (acceptance) Level Teststandard Criterioncriterion

±4-kV CD orEnclosure PASSESD IEC61000-4-2 8-kV AD, if CD B ±6-kV CD Bports (EXCEED)not possible±2-kV/5-kHz, PASSEFT IEC61000-4-4 capacitive B ±4 kV B (EXCEED)clampPorts for

control lines ±1-kV; sinceand DC shielded cableauxiliary Surge 1.2/50 >20-m, direct PASSIEC61000-4-5 B ±2 kV A (1)

supplies <60 V µs, 8/20 µs coupling to (EXCEED)shield (2Ω/500 A)

(1) Class A is considered when there are less than two consecutive UDP packet losses and no major drop in network utilization.One UDP packet loss will be tolerated by the system if the following UDP packet is echoed back successfully. The test has beenconducted with a UDP error packet test program at around 5% network bandwidth.

The performance (acceptance) criterion is defined as follows:

Table 28. Performance (Acceptance) Criterion

PERFORMANCE(ACCEPTANCE) DESCRIPTION

CRITERIONA The module shall continue to operate as intended. No loss of function or performance even during the test.

Temporary degradation of performance is accepted. After the test, the module shall continue to operate asB intended without manual intervention.During the test, loss of functions accepted, but no destruction of hardware or software. After the test, theC module shall continue to operate as intended automatically, after manual restart, or power off, or power on.



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7.4.1 Test SetupThe TIDA-00204 TI design has been tested at the testing laboratory of CSA Group Bayern inStrasskirchen, Germany.

The TIDA-00204 with the test equipment is shown in the below picture. Each of the TIDA-00204 GigabitEthernet ports 1 and 2 are connected to a PC or Laptop with an external Gigabit Ethernet to USB3adapter. Two different test programs ran of the laptops.

The first test program "tida-00204_udp_throughput_test.exe" transmits and receives continuous UDPpackages with a payload size of 1472 bytes, yielding the maximum 1514 bytes per IPv4 packet. Thefirmware of the Sitara AM3359 receives the UDP packets and echoes them back. Each of the twoEthernet ports used around 20% of the network.

The second test program "tida-00204_udp_packet_error_test.exe" implements a UDP packet tester. Itcompares the transmitted packet with the received packet (echoed back from Sitara AM3359) for thecorresponding Gigabit Ethernet port on the TIDA-00204. If a packet error is detected, it prints the numberof the packet to the console. The maximum bandwidth/network utilization achievable with this test softwarewas around 5% due to limitation on the PC test software "tida-00204_udp_packet_error_test.exe".

Figure 53. TIDA-00204 Test Equipment Overview for EMI/EMC Tests

The specific test setups for EMI (Section 7.4.2), ESD (Section 7.4.3), EFT (Section 7.4.4), and Surge(Section 7.4.5).



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7.4.2 CISPR 11 / EN55011 Radiated Emission Test ResultsThe TIDA-00204 meets EN55011 / CSPR 11 Class A requirements for category 2 with at least 4.3 dB ofmargin (far-field measurements at 125 MHz, vertical polarization). The minimum margin in horizontalpolarization was 10.6 dB at 125 MHz as well.

An automatic pre-test with near-field measurement (3-m antenna distance to device under test [DuT]) wasused to identify the frequencies of maximum EMI in each horizontal and vertical polarization aspreparation for the final test with a 10-m antenna distance.

Figure 54 shows the test setup of the final measurement with a 10-m antenna distance to DuT.

Figure 54. CISPR 11 / EN55011 Test Setup for Far-Field With 10-m Antenna Distance to TIDA-00204 DuT



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Figure 55 and Figure 56 show the measured spectral density with the final measurement with a 10-mantenna at the critical frequencies identified during the pre-test. As mentioned earlier, the minimum marginwas 4.3 dB in vertical and 10.6 dB in horizontal polarization, each at 125 MHz.

Table 29. Measured EMI Spectrum (Quasi-Peak) According to EN55011;10-m Far-Field, Horizontal Polarization

FREQUENCY READING [dBµV] VALUES [dBµV/m] LIMIT [dBµV/m]CORRECTION (dB) MARGIN [dB] (QP)(MHz) (QP) (QP) (QP)125 18.6 10.8 29.4 40 10.6250 21.1 15.2 36.3 47 10.7375 16.6 18.8 35.4 47 11.6500 12.9 21.8 34.7 47 12.3875 4.9 27.3 32.2 47 14.8

Figure 55. Measured EMI Spectrum (Quasi-Peak) According to EN55011;10-m Far-Field, Horizontal Polarization



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Measured EMI Spectrum (Quasi-Peak) According to EN55011;10-m Far-Field, Vertical Polarization

FREQUENCY READING [dBuV] VALUES [dBuV/m] LIMIT [dBuV/m]CORRECTION (dB) MARGIN [dB] (QP)(MHz) (QP) (QP) (QP)125 24.9 10.8 35.7 40 4.3250 20.4 15.2 35.6 47 11.4375 12.6 18.8 31.4 47 15.6500 8.5 21.8 30.3 47 16.7875 1.2 27.3 28.5 47 18.5

Figure 56. Measured EMI Spectrum (Quasi-Peak) According to EN55011;10-m Far-Field, Vertical Polarization



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7.4.2.1 Pre-Test Results With 3-m Antenna Distance

CAUTIONDue to the shorter distance (3 m instead of 10 m), the threshold for EN55011for radiated EMI is higher by 10 dB as well. The setup is shown in Figure 57.

Figure 57. Automatic Pre-Test Setup for EMI With 3-m Antenna Distance to DuT(Left: Antenna, Right: TIDA-00204 DuT and Box With Shielded Laptops)

A pre-test was done to identify the critical frequencies on each polarization. This test has been done in achamber with a 3-m distance to the antenna.

Table 30. Pre-Test Equipment Setup

TYPE NAMEAntenna A5_VULB9168_24-14-007Cable A5_Cable_50-13-018Cable A5_Cable_50-13-019

Preamplifier Ohm1_MTS TVV-695_50-01-059Receiver Ohm1_FSP7_11-05-002Turntable CO1000



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The measured spectrum of the pre-test is shown in Figure 58 for horizontal and in Figure 59 for vertical polarization.

Figure 58. Measured EMI Spectrum According to EN55011; Figure 59. Measured EMI Spectrum According to EN55011;3-m Near-Field, Horizontal Polarization (Pre-Test) 3-m Near-Field, Vertical Polarization (Pre-Test)



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7.4.3 IEC-61000-4-2 ESD Test ResultsFigure 60 shows the ESD test setup. The ESD strike was applied to the RJ45 case or shield of port 1 andport 2. Both RJ45 cases were electrically connected with a conductive copper foil. During the ESD test,both Gigabit Ethernet ports were connected with a 20-m cable to the far-end laptops. A UDP packettransfer was launched on each Gigabit Ethernet link.

The test program "tida-00204_udp_throughput_test.exe" transmits and receives continuous UDPpackages with a payload size of 1472 bytes, yielding the maximum 1514 bytes per IPv4 packet. Thefirmware of the Sitara AM3359 receives the UDP packets and echoes them back. The network utilizationwas around 20% on each of the two Ethernet ports.

Figure 60. IEC61000-4-2 Test Setup for TIDA-00204 (Picture of 6-kV CD)



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Table 31 shows the complete ESD test results for contact and air discharge (AD) at voltage levels, whichalso exceed the requirements per IEC61800-3. This is marked accordingly.

Table 31. IEC-61000-4-2 ESD Test Results for TIDA-00204

TIDA-00204BASIC PERFORMANCEPHENOMENON LEVEL CONNECTOR COMMENTSTANDARD CRITERION (1)UNDER TEST

ESD IEC61000-4-2 ±4-kV CD RJ45 port 1 and 2 BESD IEC61000-4-2 ±6-kV CD RJ45 port 1 and 2 B Not required per IEC61800-3ESD IEC61000-4-2 ±8-kV CD RJ45 port 1 and 2 C Not required per IEC61800-3ESD IEC61000-4-2 ±8-kV AD RJ45 port 1 and 2 BESD IEC61000-4-2 ±15-kV AD RJ45 port 1 and 2 B Not required per IEC61800-3

(1) See Table 28 for performance descriptions.

Class B was claimed when there was a network utilization reduction, but no link loss. Only for 8-kV ESDCD was the link lost and a power-cycle of the boards was required. Figure 61 shows the networkutilization during the entire ESD test for ±6-kV CD ESD strikes. It can be seen that the network utilizationis reduced due to lost packets, but the link does not drop.

Figure 61. IEC61000-4-2 ±6-kV ESD CD: Network Utilization With UDP Packet Throughput Test on Port 1and Port 2 (Measured on Two Separate Laptops)



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7.4.4 IEC-61000-4-4 EFT Test ResultsFigure 62 shows the EFT test setup. During the EFT test, both Gigabit Ethernet ports where connectedwith a 3-m CAT7 cable to far end laptops. The capacitive clamp can be seen in the foreground ofFigure 62.

Figure 62. IEC61000-4-4 EFT Test Setup for TIDA-00204

During the EFT tests, a UDP packet transfer was launched on each Gigabit Ethernet port. Each test leveland Gigabit Ethernet port was tested with two different PC software programs running on a laptop foranalysis, as described earlier. The test results are shown in Table 32.

Table 32. IEC-61000-4-4 EFT Test Results for TIDA-00204

TIDA-00204 PERFORMANCEPHENOMENON BASIC STANDARD LEVEL CONNECTOR COMMENTCRITERION (1) (2)UNDER TEST

±2-kV/5-kHz,EFT IEC61000-4-4 RJ45 port 1 Bcap clamp±2-kV/5-kHz,EFT IEC61000-4-4 RJ45 port 2 Bcap clamp±4-kV/5-kHz, Not required perEFT IEC61000-4-4 RJ45 port 1 Bcap clamp IEC61800-3±4-kV/5-kHz, Not required perEFT IEC61000-4-4 RJ45 port 2 Bcap clamp IEC61800-3

(1) See Section 7.4.1 for test setup description.(2) See Table 28 for performance descriptions.

To verify the number of packets lost the program during the EFT tests, a UDP packet transfer waslaunched on each Gigabit Ethernet port. Each EFT voltage test level and gigabit Ethernet port was testedwith two different software programs running on the laptop for analysis of throughput and packet errorsduring an EFT event.



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Class B was claimed as there was no significant network utilization reduction, from the average of around20% during the UDP packet throughput test as shown in Figure 63. During the packet error test, thenetwork utilization dropped from 5% to 1% due to a laptop issue when a packet lost was detected.

Figure 63. IEC61000-4-4 ±4-kV EFT: Network Utilization With UDP Throughput Test on Gigabit EthernetPort 1

Figure 64. IEC61000-4-4 ±4-kV EFT: Network Utilization With UDP Packet Error Test on Gigabit EthernetPort 1

During the test, the UDP packet error test program printed the packet number for every packet lost as wellas the total submitted packets. The total number of submitted packets during the EFT event was 60,680packets (1526 bytes each). The number of lost packets was 100. However, there was not a single eventwhere two consecutive packets were lost. Therefore, every lost packet was re-submitted successfully.



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7.4.5 IEC-61000-4-5 Surge Test ResultsFigure 65 shows the surge test setup. During the surge test, both Gigabit Ethernet ports where connected.The port under test with a 20-m CAT7 cable and the other port, not under test with a 3-m cable to far endlaptops, respectively. The surge generator is on the left-hand side outside the picture.

Figure 65. IEC61000-4-5 Surge Test Setup for TIDA-00204

During the surge tests, a UDP packet transfer was launched on each Gigabit Ethernet port. Each test leveland Gigabit Ethernet port was tested with two different PC software programs running on a laptop foranalysis, as described earlier. The test results are shown in Table 33.

Table 33. IEC-61000-4-5 Surge Test Results for TIDA-00204

TIDA-00204BASIC PERFORMANCEPHENOMENON LEVEL CONNECTOR COMMENTSTANDARD CRITERION (1) (2)UNDER TEST

±1-kV, 2-Ω/500-A(20-m shielded Exceeds IEC61800-3,Surge IEC61000-4-5 RJ45 port 1 ACAT7 Ethernet only Class B requiredcable)±1-kV, 2-Ω/500-A(20-m shielded Exceeds IEC61800-3,Surge IEC61000-4-5 RJ45 port 2 ACAT7 Ethernet only Class B requiredcable)±2-kV, 2-Ω/500-A(20-m shieldedSurge IEC61000-4-5 RJ45 port 1 A Exceeds IEC61800-3CAT7 Ethernetcable)±2-kV, 2-Ω/500-A(20-m shieldedSurge IEC61000-4-5 RJ45 port 2 A Exceeds IEC61800-3CAT7 Ethernetcable)

(1) See Section 7.4.1 for test setup description.(2) See Table 28 for performance descriptions.



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Class A is considered when there are less than two consecutive UDP packet losses and no major drop innetwork utilization. One UDP packet loss will be tolerated by the system, if the following UDP packet isechoed back successfully. The test has been conducted with a UDP error packet test program at around5% network bandwidth (see Figure 66).

To verify the number of packets lost the program during the surge tests, a UDP packet transfer waslaunched on each Gigabit Ethernet port. Each surge voltage test level and Gigabit Ethernet port wastested with two different software programs running on the laptop for analysis of throughput and packeterrors during a surge event.

Class A was claimed as there was no significant network utilization reduction, from the average of around20% during the UDP packet throughput test. During the packet error test, the network utilization remained5%. The total number of submitted packets during the surge event was 230,000 packets (1526 byteseach). Only one packet was lost. Higher network utilization may yield more packet error losses; however,this was not tested due to lack of test equipment.

Figure 66. IEC61000-4-5 ±2-kV Surge: Network Utilization With UDP Packet Error Test on Gigabit EthernetPort 1



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Figure 67. IEC61000-4-5 ±2-kV Surge: Packet Error Analysis, Console Printout on Gigabit Ethernet Port 1

Additional tests were done with a modified board that did not have a TVS diode between the PHY andtransformer. During ±1-kV surge (as per IEC61800-3), no significant changes were observed with orwithout TVS diode. However, at ±2-kV (exceeding the level required by IEC61800-3), the packet errorlosses significantly increase by a factor of 10. Therefore, if higher surge immunity is desired the TVS diodeis recommend to be populated between the PHY and the transformer as per the TIDA-00204 schematics.The TVS diode between the transformer and the RJ45 connector on ETH1 (port 1) was an initial testoption and not needed. It is marked DNP (not fitted) on the TIDA-00204 schematics.



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1

3

2

J2

RAPC722X

D1

MBRA160T3G

GND

10

R1

SW1

SW2

CBOOT3

VCC4

BIAS5

SYNC6

RT7

PGOOD8

FB9

AGND10

SS/TRK11

EN12

VIN13

VIN14

PGND15

PGND16

PAD17

U1

LM46002PWPGND GND GND

GND

GND

GND

GND

4.7µFC13

GNDGND

8.2pFC14

L2

MSS1260-153MLB

V5_dc

GND

V5__DC_Sitara

453kR2

1.00MR6

249kR7

100kR4

0.022µFC12DNP

0402 footprint

10µFC1

10µFC2

10µFC3

1 2

J1

PEC02SAAN

V5_dc

Green

12

D2

GND

750R3

1µFC10

1000pFC9

0.1µFC8

1000pFC7

0.1µFC6

L1

LPS3010-102MRB

1µFC5

10µFC11

0.47µF

C4

80.6kR5

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8 Design Files

8.1 SchematicsTo download the schematics, see the design files at TIDA-00204.

Figure 68. 24-V Input Power Supply



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IN1

OUT2

3

NR4

EN5

6

GND

U2

TPS73733DCQ

EN1

VCON2

FB3

SGND4

VOUT5

PGND6

VIN7

VREF8

PAD9

U3

LMZ10501SIL

IN1

2

EN3

NC4

OUT5

GND

U4

TLV70218DBVR

DNP

V5_dc

GND

GND

GND

1µFC19DNP

1µFC20DNP

GND

GND

1µFC16

OUT1

NC2

EN3

BIAS4

GND5

IN6

PAD7

U5

TPS72011DRV

GND

GND GND

V25phy

V18phy

V11phy

Vddio

Vddio

Vaux2

PHY is powered after vddio

V5_dc

0

R11DNP

0

R10

0

R9

0R15

0R8

0

R12

150kR14

0.1µFC24

0.1µFC22

0.1µFC15

470pFC21

10µFC17

10µFC18

2.2µFC23

V25phy

Green

12

D3

GND

360R13

1 2

J3PEC02SAAN

110kR16

1v8 rail only used forinitial test/debug purpose

Design Files www.ti.com

Figure 69. Power Supply for Dual DP83867IR PHYs



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D1+1

D1-2

NC6

NC7

NC9

NC10

D2+4

D2-5

GND3

GND8

U9

TPD4E05U06DQA

Green

12

D6

GNDGND

GND GND

MDIO_CLK_1

MDIO_DATA_1

GND

GND

D1+1

D1-2

NC6

NC7

NC9

NC10

D2+4

D2-5

GND3

GND8

U7

TPD4E05U06DQA

PHY1_TD_A_P

PHY1_TD_A_N

PHY1_TD_B_P

PHY1_TD_B_N

PHY1_TD_C_P

PHY1_TD_C_N

PHY1_TD_D_P

PHY1_TD_D_N

PHY1_TD_A_P

PHY1_TD_A_N

PHY1_TD_B_P

PHY1_TD_B_N

GND

GND

PHY1_TD_C_P

PHY1_TD_C_N

PHY1_TD_D_P

PHY1_TD_D_N

PHY_RESETn

PHY1_INTPWDN

PHY1_CLKOUT

RGMII1_TXCLK

RGMII1_TXCTRL

RGMII1_TXD0

RGMII1_TXD1

RGMII1_TXD2

RGMII1_TXD3

RGMII1_RXD0

RGMII1_RXD1

RGMII1_RXD2

RGMII1_RXD3

RGMII1_RXCLK

RGMII1_RXCTRL

PHY1_RX1588

PHY1_TX1588

2

3

4

1

5

6

7

8

9

10

11

12

J4

43202-8916

Yellow

12

D4Red

12

D5

GND

1

2

3

4

5

U11SN74AHC1G08DCK

GND

SYS_RESETn

PHY_RESETn

GND

GPIO_PHY_RESETn

Vddio

VddioVddio

V25phy

V25phy

V18phy

V18phy

V11phy

V11phy

PHY1_X_D_N

PHY1_X_D_P

PHY1_X_C_N

PHY1_X_C_P

PHY1_X_D_P

PHY1_X_D_N

PHY1_X_C_P

PHY1_X_C_N

PHY1_X_B_N

PHY1_X_B_P

PHY1_X_A_P

PHY1_X_A_N

75.0

R24

75.0

R22

75.0

R32

75.0

R37

PHY1_EARTH

1000pFC33

PHY1_EARTH

PHY1_X_B_N

PHY1_X_B_P

PHY1_X_A_N

PHY1_X_A_P

PHY1_TD_A_P

PHY1_TD_A_N

PHY1_TD_B_P

PHY1_TD_B_N

PHY1_TD_C_P

PHY1_TD_C_N

PHY1_TD_D_P

PHY1_TD_D_N

GND

Place each 1000pF cap close to each supply pin of the PHY

10.0k

R21

560R25

10.0kR38

22

R35DNP

1.00M

R36

560R26

560R27

0.1µF

C27

0.1µF

C28

0.1µF

C29

0.1µF

C30

10µFC51

10µFC40

10µFC36

10µFC45

GND

PHY1_TD_A_P

PHY1_TD_A_N

PHY1_TD_B_N

PHY1_TD_B_P

PHY1_TD_C_P

PHY1_TD_C_N

PHY1_TD_D_P

PHY1_TD_D_N

1000pFC38

1000pFC39

1000pFC42

1000pFC43

1000pFC44

1000pFC47

1000pFC48

1000pFC49

1000pFC50

0.01µFC41

0.01µFC37

0.01µFC46

0.01µFC52

0.01µF

C35

D1+1

D1-2

NC6

NC7

NC9

NC10

D2+4

D2-5

GND3

GND8

U10

TPD4E05U06DQA

DNP

D1+1

D1-2

NC6

NC7

NC9

NC10

D2+4

D2-5

GND3

GND8

U8

TPD4E05U06DQA

DNP

PHY1_X_C_P

PHY1_X_C_N

PHY1_X_D_P

PHY1_X_D_N

PHY1_X_A_P

PHY1_X_A_N

PHY1_X_B_P

PHY1_X_B_N

4.7k

R23

0

R17DNP

0

R18DNP

1000pFC26

1000pFC25

GND

GND

PHY1_EARTH

PHY1_EARTH

27pFC31

27pFC32

Vddio

Orange

12

D7

560R33

GND

11.0k

R30

2.49kR34

Vddio

GND

11.0kR28

2.49kR31

GND GND GND

RGMII1_RXCLK_R

RGMII1_RXD0_R

RGMII1_RXD1_R

RGMII1_RXD2_R

RGMII1_RXD3_R

RGMII1_RXCTRL_R

4.7k

R29Vddio

0

R19

TCT11

TD1+2

TD1-3

TCT24

TD2+5

TD2-6

TCT37

TD3+8

TD3-9

TCT410

TD4+11

TD4-12

MX4-13

MX4+14

MCT415

MX3-16

MX3+17

MCT318

MX2-19

MX2+20

MCT221

MX1-22

MX1+23

MCT124

T1

HX5008FNL

0

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

R20

EXB-2HVR000V

1 2

25 MHz

Y1


1000pF

C34

DNP

GND PHY1_EARTH

TVS diode only used forinitial testing

TVS diode only used forinitial testing

RESERVED1

RESERVED7

RESERVED9

RESERVED16

TD_P_A2

TD_M_A3

TD_P_B5

TD_M_B6

TD_P_C10

TD_M_C11

TD_M_D14

TD_P_D13

RBIAS15

TX_CLK30

TX_D731

TX_D632

TX_D533

TX_D434

TX_D335

TX_D236

TX_D137

TX_D038

TX_ER39

GTX_CLK40

RX_CLK43

RX_D044

RX_D145

RX_D246

RX_D347

RX_D4/GPIO48

RX_D5/GPIO49

RX_D6/GPIO50

RX_D7/GPIO51

TX_EN/TX_CTRL52

RX_DV/RX_CTRL53

RX_ER/GPIO54

COL/GPIO55

CRS/GPIO56

MDC20

MDIO21

INT/PWDN60

RESET59

XI19

XO18

CLK_OUT22

JTAG_CLK25

JTAG_TDO26

JTAG_TDI28

JTAG_TRSTN24

LED_261

LED_162

LED_063

VDDIO23

VDDIO41

VDDIO57

VDDA1P817

VDDA1P864

VDDA2P54

VDDA2P512

VDD1P18

VDD1P129

VDD1P142

VDD1P158

GND65

JTAG_TMS27

U6

DP83867IRPAPR


Figure 70. DP83867IR PHY 1



http://www.ti.com


GNDGND

GND GND

Green

12

D11

MDIO_CLK_2

MDIO_DATA_2

GND

GND

PHY2_TD_A_P

PHY2_TD_A_N

PHY2_TD_B_P

PHY2_TD_B_N

PHY2_TD_C_P

PHY2_TD_C_N

PHY2_TD_D_P

PHY2_TD_D_N

PHY2_INTPWDN

RGMII2_TXCLK

RGMII2_TXCTRL

RGMII2_TXD0

RGMII2_TXD1

RGMII2_TXD2

RGMII2_TXD3

RGMII2_RXD0

RGMII2_RXD1

RGMII2_RXD2

RGMII2_RXD3

RGMII2_RXCLK

RGMII2_RXCTRL

PHY1_CLKOUTGND

PHY2_RX1588

PHY2_TX1588

2 5

1 6

3 4

5V

D13

SRV05-4.TCT

2 5

1 6

3 4

5V

D8

SRV05-4.TCT

Yellow

12

D9Red

12

D10

GND

GND

PHY2_TD_A_P PHY2_TD_A_N

PHY2_TD_B_P PHY2_TD_B_N

PHY2_TD_C_P

PHY2_TD_D_P

PHY2_TD_C_N

PHY2_TD_D_N

GND

V11phy

V11phy V18phy

V25phy

V25phy

Vddio

Vddio

Vddio

Vddio

Orange

12

D12

2

3

4

1

5

6

7

8

9

10

11

12

J5

43202-8916

75.0

R48

75.0

R42

75.0

R58

75.0

R64

PHY2_EARTH

1000pFC59

PHY2_EARTH

PHY2_TD_B_P

PHY2_TD_B_N

PHY2_TD_C_P

PHY2_TD_C_N

PHY2_TD_D_P

PHY2_TD_D_N

GND

0

R510

R500

R470

R460

R440

R43

10.0k

R41

560R60

560R54

560R53

560R52

11.0kR49

1.00M

R65

PHY2_TD_A_P

PHY2_TD_A_N

0.1µF

C55

0.1µF

C56

0.1µF

C57

0.1µF

C58

10µFC78

10µFC67

10µFC72

10µFC63

Place each 1000pF cap close to each supply pin of the PHY

PHY_RESETn

1000pFC65

1000pFC66

1000pFC69

1000pFC70

1000pFC74

1000pFC75

1000pFC76

1000pFC77

1000pFC71

0.01µFC64

0.01µFC73

0.01µFC79

0.01µFC68

PHY2_X_D_P

PHY2_X_D_N

PHY2_X_C_P

PHY2_X_B_P

PHY2_X_A_P

PHY2_X_C_N

PHY2_X_B_N

PHY2_X_A_N

GND4.7k

R45

GND

11.0k

R59

2.49kR62

0

R39DNP

0

R40DNP

1000pFC54

1000pFC53

GND

0

R63DNP

V18phyGND

27pFC60

27pFC61

Vddio

GND

11.0k

R56

2.49kR61

GND GND GND

2.49kR57

RGMII2_RXCTRL_R

RGMII2_RXCLK_R

RGMII2_RXD0_R

RGMII2_RXD1_R

RGMII2_RXD2_R

RGMII2_RXD3_R

4.7k

R55Vddio

TCT11

TD1+2

TD1-3

TCT24

TD2+5

TD2-6

TCT37

TD3+8

TD3-9

TCT410

TD4+11

TD4-12

MX4-13

MX4+14

MCT415

MX3-16

MX3+17

MCT318

MX2-19

MX2+20

MCT221

MX1-22

MX1+23

MCT124

T2

HX5008FNL1 2

25 MHz

Y2 ABM3-25.000MHZ-D2Y-T

1000pF

C62

DNP

GND PHY2_EARTH

RESERVED1

RESERVED7

RESERVED9

RESERVED16

TD_P_A2

TD_M_A3

TD_P_B5

TD_M_B6

TD_P_C10

TD_M_C11

TD_M_D14

TD_P_D13

RBIAS15

TX_CLK30

TX_D731

TX_D632

TX_D533

TX_D434

TX_D335

TX_D236

TX_D137

TX_D038

TX_ER39

GTX_CLK40

RX_CLK43

RX_D044

RX_D145

RX_D246

RX_D347

RX_D4/GPIO48

RX_D5/GPIO49

RX_D6/GPIO50

RX_D7/GPIO51

TX_EN/TX_CTRL52

RX_DV/RX_CTRL53

RX_ER/GPIO54

COL/GPIO55

CRS/GPIO56

MDC20

MDIO21

INT/PWDN60

RESET59

XI19

XO18

CLK_OUT22

JTAG_CLK25

JTAG_TDO26

JTAG_TDI28

JTAG_TRSTN24

LED_261

LED_162

LED_063

VDDIO23

VDDIO41

VDDIO57

VDDA1P817

VDDA1P864

VDDA2P54

VDDA2P512

VDD1P18

VDD1P129

VDD1P142

VDD1P158

GND65

JTAG_TMS27

U12

DP83867IRPAPR


Figure 71. DP83867IR PHY 2



http://www.ti.com


VCC33

SCLSR/EN111

REFGND17

OSC32KOUT21

VBACKUP27

SW135

VCC241

VCC447

PAD49

VCC66

VCCIO13

OSC32KIN20

VPLL24

VFB330

CLK32KOUT38

VFB244

SDASR/EN210

VMMC2

SDA/SDI8

GNDIO15

VDAC22

VCC728

PWRON33

GPIO/CKSYN39

INT145

VDIG25

VFBIO16

BOOT119

TESTV25

SW331

VCC136

SW242

VAUX248

PWRHOLD1

VDIG17

SWIO14

VCC523

VRTC29

GND134

NRESPWRON40

VAUX146

VAUX334

VDDIO12

VREF18

BOOT026

VFB132

SLEEP37

GND243

SCL/SCK9

U13

TPS65910A3A1RSL

V5__DC_Sitara

4.7µFC82

4.7µFC83

4.7µFC84

4.7µFC85

GND

GND

GND

I2C0_SCL

I2C0_SDA

GND

PMIC_Vrtc

PMIC_VrtcGND

PMIC_RESETOUTn

GND

PMIC_PWR_EN

GND

GND

GND

GND

L5

VLCF5020T-2R2N2R6-3

GND

L4

VLCF5020T-2R2N2R6-3

L3

VLCF5020T-2R2N2R6-3

GND

GND

GND

GND

V5__DC_Sitara

V5__DC_Sitara

V5__DC_Sitara

V5__DC_Sitara

V5__DC_Sitara

Vdd1_smps

Vdd2_smps

Vdds_DDR

Vdig2

Vaux2

Vaux1

Vaux33

Vmmc

Vpll

Vdac

OUT1

NR3

EN4

NC5

IN6

2

GND

U14

TPS71718DSER

V5__DC_Sitara

1µFC100

1µFC101

GND

GND

Vrtc

GND

GND

GND

V5__DC_Sitara

GND

GND

4.7µFC87

GND

V5__DC_Sitara

10.0kR67

2.2µFC91

2.2µFC92

2.2µFC93

2.2µFC94

2.2µFC95

2.2µFC96

2.2µFC98

2.2µFC97

Vaux33

Vaux33

Green

12

D14

GND

560R66

0.1µFC99

10µFC80

10µFC81

10µFC86

10µFC88

10µFC90

10µFC89


Figure 72. Sitara AM3359 Power Supply



http://www.ti.com


CAP_VBB_MPUC10

CAP_VDD_RTCD6

CAP_VDD_SRAM_CORED9

CAP_VDD_SRAM_MPUD11

RESERVEDA3

RTC_KALDO_ENB4

VDDA1P8V_USB0N16

VDDA1P8V_USB1R16

VDDA3P3V_USB0N15

VDDA3P3V_USB1R15

VDDA_ADCD8

VDDSE6

VDDSE14

VDDSF9

VDDSK13

VDDSN6

VDDSP9

VDDSP14

VDDSHV1P7

VDDSHV1P8

VDDSHV2P10

VDDSHV2P11

VDDSHV3P12

VDDSHV3P13

VDDSHV4H14

VDDSHV4J14

VDDSHV5K14

VDDSHV5L14

VDDSHV6E10

VDDSHV6E11

VDDSHV6E12

VDDSHV6E13

VDDSHV6F14

VDDSHV6G14

VDDSHV6N5

VDDSHV6P5

VDDSHV6P6

VDDS_DDRE5

VDDS_DDRF5

VDDS_DDRG5

VDDS_DDRH5

VDDS_DDRJ5

VDDS_DDRK5

VDDS_DDRL5

VDDS_OSCR11

VDDS_PLL_CORE_LCDR10

VDDS_PLL_DDRE7

VDDS_PLL_MPUH15

VDDS_RTCD7

VDDS_SRAM_CORE_BGE9

VDDS_SRAM_MPU_BBD10

VDD_COREF6

VDD_COREF7

VDD_COREG6

VDD_COREG7

VDD_COREG10

VDD_COREH11

VDD_COREJ12

VDD_COREK6

VDD_COREK8

VDD_COREK12

VDD_COREL6

VDD_COREL7

VDD_COREL8

VDD_COREL9

VDD_COREM11

VDD_COREM13

VDD_COREN8

VDD_COREN9

VDD_COREN12

VDD_COREN13

VDD_MPUF10

VDD_MPUF11

VDD_MPUF12

VDD_MPUF13

VDD_MPUG13

VDD_MPUH13

VDD_MPUJ13

VDD_MPU_MONA2

VPPM5

VSSA_ADCE8

VSSA_USBM14

VSSA_USBN14

U15C

AM3359BZCZA80

VSSA1

VSSA18

VSSF8

VSSG8

VSSG9

VSSG11

VSSG12

VSSH6

VSSH7

VSSH8

VSSH9

VSSH10

VSSH12

VSSJ6

VSSJ7

VSSJ8

VSSJ9

VSSJ10

VSSJ11

VSSK7

VSSK9

VSSK10

VSSK11

VSSL10

VSSL11

VSSL12

VSSL13

VSSM6

VSSM7

VSSM8

VSSM9

VSSM10

VSSM12

VSSN7

VSSN10

VSSN11

VSSV1

VSSV18

U15D

AM3359BZCZA80

GND GND

GND GND_osc0

GND

GND

GND

GND

GNDGND

GND

GND GND

GND

150 ohm

L7

GNDGNDA_ADC

Vdd2_smps

Vdd1_smps

Vdig2

Vdig2

Vdds_DDR

Vaux33

Vaux1

Vaux2

Vdig2

Vrtc

Vaux2

Vaux2

Vaux2

Vmmc

Vmmc

Vdds_DDR

Vdd1_smps_am335x

Vdd1_smps_am335xVdd2_smps_am335x

Vdd2_smps_am335x

GND

Vdac

150 ohm

L6Vpll

GNDA_ADC

10.0kR68

VDDA_ADC

10µFC126

10µFC116

10µFC113

10µFC110

10µFC104

10µFC131

10µFC107

10µFC149

10µFC148

10µFC170

10µFC171

10µFC185

Vdig2

1µFC145

0.1µFC150

1µFC139

1µFC140

1µFC141

0.1µFC151

0.1µFC152

0.1µFC153

0.1µFC154

0.1µFC155

0.1µFC156

0.1µFC157

0.1µFC158

0.1µFC159

0.1µFC160

0.1µFC161

0.1µFC162

0.1µFC163

0.1µFC164

0.1µFC165

0.1µFC166

0.1µFC167

0.1µFC168

0.1µFC169

0.01µFC187

0.01µFC186

0.01µFC189

0.01µFC188

0.01µFC190

0.01µFC172

0.01µFC173

0.01µFC174

0.01µFC175

0.01µFC176

0.01µFC177

0.01µFC178

0.01µFC179

0.01µFC180

0.01µFC181

0.01µFC182

0.01µFC183

0.01µFC184

0.01µFC146

0.01µFC147

0.01µFC143

0.01µFC144

0.01µFC132

0.01µFC133

0.01µFC134

0.01µFC135

0.01µFC136

0.01µFC137

0.01µFC138

0.01µFC127

0.01µFC128

0.01µFC129

0.01µFC130

0.01µFC117

0.01µFC118

0.01µFC119

0.01µFC120

0.01µFC121

0.01µFC122

0.01µFC123

0.01µFC124

0.01µFC125

0.01µFC114

0.01µFC115

0.01µFC111

0.01µFC112

0.01µFC102

0.01µFC103

0.01µFC105

0.01µFC106

0.01µFC108

0.01µFC109

0.01µFC142

Place each 0.1uF cap close to each supply pin of the Sitara DDR I/F

Place each 0.01uF cap close to each supply pin of the Sitara


Figure 73. Sitara AM3359 Supply Pins



http://www.ti.com


GPMC_A0R13

GPMC_A1V14

GPMC_A2U14

GPMC_A3T14

GPMC_A4R14

GPMC_A5V15

GPMC_A6U15

GPMC_A7T15

GPMC_A8V16

GPMC_A9U16

GPMC_A10T16

GPMC_A11V17

GPMC_AD0U7

GPMC_AD1V7

GPMC_AD2R8

GPMC_AD3T8

GPMC_AD4U8

GPMC_AD5V8

GPMC_AD6R9

GPMC_AD7T9

GPMC_AD8U10

GPMC_AD9T10

GPMC_AD10T11

GPMC_AD11U12

GPMC_AD12T12

GPMC_AD13R12

GPMC_AD14V13

GPMC_AD15U13

GPMC_ADV_ALER7

GPMC_BE0_CLET6

GPMC_BE1U18

GPMC_CLKV12

GPMC_CS0V6

GPMC_CS1U9

GPMC_CS2V9

GPMC_CS3T13

GPMC_OEN_RET7

GPMC_WAIT0T17

GPMC_WEU6

GPMC_WPU17

XTALINV10

XTALOUTU11

VSS_OSCV11

RTC_XTALINA6

RTC_XTALOUTA4

VSS_RTCA5

DDR_A0F3

DDR_A1H1

DDR_A2E4

DDR_A3C3

DDR_A4C2

DDR_A5B1

DDR_A6D5

DDR_A7E2

DDR_A8D4

DDR_A9C1

DDR_A10F4

DDR_A11F2

DDR_A12E3

DDR_A13H3

DDR_A14H4

DDR_A15D3

DDR_BA0C4

DDR_BA1E1

DDR_BA2B3

DDR_CASF1

DDR_CKD2

DDR_CKEG3

DDR_CKD1

DDR_CS0H2

DDR_D0M3

DDR_D1M4

DDR_D2N1

DDR_D3N2

DDR_D4N3

DDR_D5N4

DDR_D6P3

DDR_D7P4

DDR_D8J1

DDR_D9K1

DDR_D10K2

DDR_D11K3

DDR_D12K4

DDR_D13L3

DDR_D14L4

DDR_D15M1

DDR_DQM0M2

DDR_DQM1J2

DDR_DQS0P1

DDR_DQS1L1

DDR_DQS0P2

DDR_DQS1L2

DDR_ODTG1

DDR_RASG4

DDR_RESETG2

DDR_WEB2

EMU0C14

EMU1B14

TCKA12

TDIB11

TDOA11

TMSC11

TRSTB10

PWRONRSTB15

RTC_PWRONRSTB5

WARMRSTA10

XDMA_EVENT_INTR0A15

XDMA_EVENT_INTR1D14

DDR_VREFJ4

DDR_VTPJ3

EXTINTB18

MMC0_CMDG18

MMC0_CLKG17

MMC0_DAT0G16

MMC0_DAT1G15

MMC0_DAT2F18

MMC0_DAT3F17

U15A

AM3359BZCZA80

LCD_AC_BIAS_ENR6

LCD_DATA0R1

LCD_DATA1R2

LCD_DATA2R3

LCD_DATA3R4

LCD_DATA4T1

LCD_DATA5T2

LCD_DATA6T3

LCD_DATA7T4

LCD_DATA8U1

LCD_DATA9U2

LCD_DATA10U3

LCD_DATA11U4

LCD_DATA12V2

LCD_DATA13V3

LCD_DATA14V4

LCD_DATA15T5

LCD_HSYNCR5

LCD_PCLKV5

LCD_VSYNCU5

AIN0B6

AIN1C7

AIN2B7

AIN3A7

AIN4C8

AIN5B8

AIN6A8

AIN7C9

MII1_RX_DVJ17

MII1_TX_ENJ16

MII1_RX_ERJ15

MII1_RX_CLKL18

MII1_TX_CLKK18

MII1_COLH16

MII1_CRSH17

MII1_RXD0M16

MII1_RXD1L15

MII1_RXD2L16

MII1_RXD3L17

MII1_TXD0K17

MII1_TXD1K16

MII1_TXD2K15

MII1_TXD3J18

EXT_WAKEUPC5

PMIC_POWER_ENC6

VREFNA9

VREFPB9

USB1_VBUST18

USB0_VBUSP15

UART0_TXDE16

UART0_CTSE18

UART0_RXDE15

UART0_RTSE17

I2C0_SDAC17

I2C0_SCLC16

SPI0_SCLKA17

SPI0_CS0A16

SPI0_CS1C15

SPI0_D0B17

SPI0_D1B16

USB0_CEM15

USB0_DMN18

USB0_DRVVBUSF16

USB0_IDP16

USB0_DPN17

USB1_CEP18

USB1_IDP17

USB1_DPR17

USB1_DRVVBUSF15

USB1_DMR18

ECAP0_IN_PWM0_OUTC18

RMII1_REF_CLKH18

MDCM18

MDIOM17

MCASP0_FSXB13

MCASP0_ACLKRB12

MCASP0_AHCLKRC12

MCASP0_AHCLKXA14

MCASP0_ACLKXA13

MCASP0_FSRC13

MCASP0_AXR0D12

MCASP0_AXR1D13

UART1_TXDD15

UART1_RXDD16

UART1_RTSD17

UART1_CTSD18

U15B

AM3359BZCZA80

RGMII1_RXD0

RGMII1_RXD1

RGMII1_RXD2

RGMII1_RXD3

RGMII1_RXCLK

RGMII1_RXCTRL

RGMII2_TXCLK

RGMII2_TXCTRL

RGMII2_TXD0

RGMII2_TXD1

RGMII2_TXD2

RGMII2_TXD3

RGMII2_RXD0

RGMII2_RXD1

RGMII2_RXD2

RGMII2_RXD3

RGMII2_RXCLK

RGMII2_RXCTRL

MDIO_CLK_1

MDIO_DATA_1

DDR_VREF

GNDGND

GND

0

R71SYS_WARMRESETn

SYS_RESETn

SYS_WARMRESETn

RTC_PORZ

RTC_PORZ

GND

GND

GNDGND

PMIC_RESETOUTn

GND

PMIC_PWR_EN

GPIO_PHY_RESETn

GND

SYS_BOOT15

SYS_BOOT14

SYS_BOOT13

SYS_BOOT12

SYS_BOOT11

SYS_BOOT10

SYS_BOOT9

SYS_BOOT8

SYS_BOOT7

SYS_BOOT6

SYS_BOOT5

SYS_BOOT4

SYS_BOOT3

SYS_BOOT2

SYS_BOOT1

SYS_BOOT0

Vaux2

Vaux2

Vrtc

Vrtc

SYS_BOOT0

SYS_BOOT15

SYS_BOOT14

SYS_BOOT13

SYS_BOOT12

SYS_BOOT11

SYS_BOOT10

SYS_BOOT9

SYS_BOOT8

SYS_BOOT7

SYS_BOOT6

SYS_BOOT5

SYS_BOOT4

SYS_BOOT3

SYS_BOOT2

SYS_BOOT1

PHY1_TX1588

PHY1_RX1588

PHY2_TX1588

PHY2_RX1588

I2C0_SDA

I2C0_SCL

FTDI_UART3_TXD

FTDI_UART3_RXD

MMC1_CLK

MMC1_CMD

MMC1_DAT0

MMC1_DAT1

MMC1_DAT2

MMC1_DAT3

DDR_CLK_P

DDR_CLK_N

DDR_A12

DDR_BA1

DDR_A13

DDR_BA0

DDR_A9

DDR_A11

DDR_A8

DDR_A10

DDR_A0

DDR_A2

DDR_A5

DDR_A4

DDR_A1

DDR_A3

DDR_A7

DDR_A6

DDR_BA2

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

DDR_ODT

DDR_RESETn

DDR_CKE

DDR_DQM1

DDR_DQM0

DDR_DQS0_P

DDR_DQS0_N

DDR_DQS1_P

DDR_DQS1_N

DDR_D12

DDR_D15

DDR_D13

DDR_D14

DDR_D9

DDR_D11

DDR_D8

DDR_D10

DDR_D0

DDR_D2

DDR_D5

DDR_D4

DDR_D1

DDR_D3

DDR_D7

DDR_D6

GND_osc0

1

4DNC

3DNC

2

32.768kHz

Y4

MC-306 32.7680K-A0:ROHS

GND_rtc

PHY1_INTPWDN

PHY2_INTPWDN

JTAG_EMU1

JTAG_EMU0

JTAG_TRSTn

JTAG_TMS

JTAG_TDI

JTAG_TDO

JTAG_TCK

EMU2_GPIO0_19

EMU3_GPIO0_20

EMU4

DDR_VTT_EN

Vaux2

I2C0_SDAI2C0_SCL

10kR70

10kR83

DNP

2.2kR117

2.2kR118

10kR84

10kR85

DNP 10kR86

DNP 10kR87

DNP 10kR88

DNP 10kR89

DNP 10kR90

DNP 10kR91

DNP 10kR92

DNP 10kR93

DNP 10kR94

10kR95

10kR96

10kR97

DNP 10kR98

DNP

100kR101

100kR102

DNP100kR103

100kR104

100kR105

100kR106

100kR107

100kR108

100kR109

100kR110

100kR111

100kR112

DNP100kR113

DNP100kR114

DNP100kR115

100kR116

49.9R99

GNDA_ADC

VDDA_ADC

0.1µFC199

0.01µFC191

0.01µFC195

0.01µFC196

1000pFC197

0.01µFC200

22R74

22R72

2.2µFC201

18pF

C198

18pF

C194

27pF

C192

27pF

C193

21

S1

B3U-1000P1.00k

R100

100kR119

22R82

22R77

22R8122R8022R7922R78

RGMII1_TXD0

RGMII1_TXD1

RGMII1_TXD2

RGMII1_TXD3

RGMII1_TXCLK

RGMII1_TXCTRL

RGMII2_TXCTRL_R

RGMII2_TXD3_R

RGMII2_TXD2_R

RGMII2_TXD1_R

RGMII2_TXD0_R

RGMII2_TXCLK_R

RGMII1_TXCTRL_R

RGMII1_TXD3_R

RGMII1_TXD2_R

RGMII1_TXD1_R

RGMII1_TXD0_R

RGMII1_TXCLK_R

5

6

3

84

U16BSN74AUP2G08DCU

2

7

1

84

U16ASN74AUP2G08DCU

22R73MDIO_CLK_2

22R75MDIO_DATA_2

Vddio2.2k

R76

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

22

R69

EXB-2HV220JV

12

24 MHz

Y3ABM3-24.000MHZ-D2Y-T

Connected H16 to J16 forinitial test/debug purpose


Figure 74. Sitara AM3359 Signal Pins



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REFIN1

VLDOIN2

VO3

PGND4

VOSNS5

REFOUT6

EN7

GND8

PGOOD9

VIN10

EP11

U20

TPS51200DRCR

IO11

IO22

IO33

NC4

GND5

IO46

IO57

IO68

NC9

VCC10

U18

TPD6E001RSER

GND

GND

DDR_VREFDDR_VTT_EN

TP1

TP2

GND GND GND GND

DDR_CLK_P DDR_CLK_N

Vdds_DDR Vdds_DDR

Vdds_DDR

Vdds_DDRVtt_DDR

Vaux33

Vaux33

Vdds_DDR

Vtt_DDR

MMC1_CLK

MMC1_CMD

MMC1_DAT0

MMC1_DAT1

MMC1_DAT2

MMC1_DAT3

GND

Vmmc

Vmmc

GNDDAT2

1

CD/DAT32

CMD3

VDD4

CLK5

VSS6

DAT07

DAT18

S313

S414

S19

SW11

CD10

S212

J6

502774-0891

VDDQA1

DQ13A2

DQ15A3

DQ12A7

VDDQA8

VSSA9

VSSQB1

VDDB2

VSSB3

UDQSB7

DQ14B8

VSSQB9

VDDQC1

DQ11C2

DQ9C3

UDQSC7

DQ10C8

VDDQC9

VSSQD1

VDDQD2

UDMD3

DQ8D7

VSSQD8

VDDD9

VSSE1

VSSQE2

DQ0E3

LDME7

VSSQE8

VDDQE9

VDDQF1

DQ2F2

LDQSF3

DQ1F7

DQ3F8

VSSQF9

VSSQG1

DQ6G2

LDQSG3

VDDG7

VSSG8

VSSQG9

VREFDQH1

VDDQH2

DQ4H3

DQ7H7

DQ5H8

VDDQH9

NCJ1

VSSJ2

RASJ3

CKJ7

VSSJ8

NCJ9

ODTK1

VDDK2

CASK3

CKK7

VDDK8

CKEK9

NCL1

CSL2

WEL3

A10/APL7

ZQL8

NCL9

VSSM1

BA0M2

BA2M3

NCM7

VREFCAM8

VSSM9

VDDN1

A3N2

A0N3

A12/BCN7

BA1N8

VDDN9

VSSP1

A5P2

A2P3

A1P7

A4P8

VSSP9

VDDR1

A7R2

A9R3

A11R7

A6R8

VDDR9

VSST1

RESETT2

A13T3

NCT7

A8T8

VSST9

U17

MT41J128M16JT-125K TR

MicroSD_case

GND

GND

Vddio

I2C0_SDA

I2C0_SCL

DDR_CLK_P

DDR_CLK_N

GND GND

DDR_DQM1

DDR_DQM0

DDR_DQS0_P

DDR_DQS0_N

DDR_DQS1_P

DDR_DQS1_N

DDR_D12

DDR_D15

DDR_D13

DDR_D14

DDR_D9

DDR_D11

DDR_D8

DDR_D10

DDR_D0

DDR_D2

DDR_D5

DDR_D4

DDR_D1

DDR_D3

DDR_D7

DDR_D6

Vdds_DDR

DDR_A12

DDR_BA1

DDR_A13

DDR_BA0

DDR_A9

DDR_A11

DDR_A8

DDR_A10

DDR_A0

DDR_A2

DDR_A5

DDR_A4

DDR_A1

DDR_A3

DDR_A7

DDR_A6

DDR_BA2

GND

DDR_ODT

DDR_RESETn

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

Vdds_DDR

A01

A12

A23

VSS4

SDA5

SCL6

WP7

VCC8

U19

CAT24C256WI-GT3

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

47

R128

EXB-2HV470JV

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

47

R130

EXB-2HV470JV

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

47

R133

EXB-2HV470JV

47

R134

DDR_A0

DDR_A1

DDR_A12

DDR_BA1

DDR_A4

DDR_WEn

DDR_A8

DDR_A6

DDR_A11

DDR_A10

DDR_A9

DDR_A13

DDR_A7

DDR_CSn

DDR_ODT

DDR_BA0

DDR_A3

DDR_CASn

DDR_A5

DDR_A2

DDR_BA2

DDR_RASn

Vtt_DDR

49.9R127

49.9R126

240R132

1.00kR129

10kR131

10kR120

10kR121

10kR122

10kR123

10kR124

10kR125

10.0kR136

10.0kR138

10kR137

10kR135

4.7µFC233

0.1µFC209

0.1µFC204

0.1µFC203

1000pFC210

10µFC212

10µFC211

10µFC226

10µFC225

10µFC232

10µFC231

10µFC202

0.1µF

C207

DDR_VREF

0.1µFC213

0.1µFC214

0.1µFC215

0.1µFC216

0.1µFC217

0.1µFC218

0.1µFC219

0.1µFC220

0.1µFC221

0.1µFC222

0.1µFC223

0.1µFC224

0.1µFC228

0.1µFC229

0.1µFC230

0.01µF

C205

10µFC227

0.1µF

C206

MicroSD_caseGND

0.1µFC208


Figure 75. Sitara DDR3, E2PROM, and SD-Card Memory



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NC1

A2

GND3

Y4

VCC5

U24

SN74LVC1G06DCK

GND

GND

FT_sRESET SYS_RESETn

D+1

D-2

ID3

GND4

NC5

VBUS6

U21

TPD4S012DRYRGND

4.7µFC234

GND

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15

17

19

16

18

20

J8

TFM-110-02-S-D-A-K-TR

DNP

JTAG_TMS

JTAG_TDI

JTAG_TDO

RTCK

TCK

JTAG_EMU0

EMU_RSTn

EMU2R

EMU4R

JTAG_TRSTn

TDIS

JTAG_EMU1

EMU3R

GND

2 3

41

L8

ACM2012H-900-2P-T00

1

2

3

4

5

MH1MP1

MH2MP2

MH3MP3

MH4MP4

J7

10104111-0001LF

GND

USBD_FT_P

USBD_FT_N

VSS2

DI3

VCC6

CS5

CLK4

DO1

U23

93LC56B-I/OT

GND

USB_case

150 ohm

L10

USB_caseGND

Vdc_USBVdc_USB

Vdc_USB

Vdc_USB

Vddio

Vddio

Vddio

12

12MHz

Y5


ACBUS026

ACBUS127

ACBUS228

ACBUS329

ACBUS430

ACBUS532

ACBUS633

ACBUS734

ADBUS016

ADBUS117

ADBUS218

ADBUS319

ADBUS421

ADBUS522

ADBUS623

ADBUS724

AGND10

BCBUS048

BCBUS152

BCBUS253

BCBUS354

BCBUS455

BCBUS557

BCBUS658

BCBUS759

BDBUS038

BDBUS139

BDBUS240

BDBUS341

BDBUS443

BDBUS544

BDBUS645

BDBUS746

DM7

DP8

EECLK62

EECS63

EEDATA61

GND1

GND5

GND11

GND15

GND25

GND35

GND47

GND51

OSCI2

OSCO3

PWREN60

RESET14

REF6

SUSPEND36

TEST13

VCCIO20

VCCIO31

VCCIO42

VCCIO56

VCORE12

VCORE37

VCORE64

VPHY4

VPLL9

VREGIN50

VREGOUT49

U22

FT2232HL-REEL

GND GND

USBD_FT_P

USBD_FT_N

Vddio

GND

GND

GND

Vdc_USB

FTDI_UART3_TXD

FTDI_UART3_RXD

0

R139

0

R140

0

R141

0

R142

0

R143

0

R144

0

R145

0

R147JTAG_EMU1

JTAG_EMU0

JTAG_TRSTn

JTAG_TMS

JTAG_TDI

JTAG_TDO

JTAG_TCK

Vddio

JTAG_TCK

RTCK

TCK0

R160DNP

0

R159DNP

GND

Vddio

FT_sRESET

GND

Vddio

Vddio

FT_Vdd1v8

FT_Vdd1v8

GND

4.7µFC251

GND

150 ohm

L12

150 ohm

L11150 ohm

L9

Vddio

0

R161DNP

0

R162DNP

0

R163DNP

0

R164DNP

EMU2R

EMU4R

EMU3R

EMU_RSTn

GND

EMU2_GPIO0_19

EMU3_GPIO0_20

EMU4

SYS_RESETn

10kR149

10kR148

10kR150

10.0kR158

2.2kR154

2.2k

R156

4.75kR155

4.7kR146

4.7kR152 4.7k

R151DNP

4.7kR153

12.1k

R157

4.7kR165

GND

0.1µFC239

0.1µFC236

0.1µFC237

0.1µFC244

0.1µFC245

0.1µFC246

0.1µFC247

0.1µFC248

0.1µFC249

0.1µFC250

0.1µFC242DNP

0.01µFC235

0.01µF

C238

DNP

0.01µFC243

USBD_P

USBD_N

27pFC240

27pFC241


Figure 76. USB Virtual COM Port and JTAG Interface

space

space

space

space



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8.2 Bill of MaterialsTo download the bill of materials (BOM), see the design files at TIDA-00204.

Table 34. BOM

MANUFACTURERQTY REFERENCE PART DESCRIPTION MANUFACTURER PCB FOOTPRINT NOTEPARTNUMBERC1, C2, C3, C17, C18,C36, C40, C45, C51,C63, C67, C72, C78,C80, C81, C86, C88,C89, C90, C104, C107, CAP, CERM, 10 µF, 25 V, +/- 20%,39 C110, C113, C116, TDK C1608X5R1E106M080AC 0603 FittedX5R, 0603C126, C131, C148,C149, C170, C171,C185, C202, C211,C212, C225, C226,C227, C231, C232

CAP, CERM, 0.47 µF, 100 V, +/- 10%,1 C4 MuRata GRM21BR72A474KA73L 0805_HV FittedX7R, 0805CAP, CERM, 1 µF, 100 V, +/- 10%,1 C5 TDK C2012X7S2A105K125AB 0805_145 FittedX7S, 0805CAP, CERM, 0.1 µF, 100 V, +/- 10%,2 C6, C8 MuRata GRM188R72A104KA35D 0603 FittedX7R, 0603CAP, CERM, 1000 pF, 100 V, +/-2 C7, C9 MuRata GRM188R72A102KA01D 0603 Fitted10%, X7R, 0603CAP, CERM, 1 µF, 25 V, +/- 10%,1 C10 MuRata GRM188R71E105KA12D 0603 FittedX7R, 0603CAP, CERM, 10 µF, 100 V, +/- 20%,1 C11 TDK C5750X7S2A106M 2220 FittedX7S, 2220

C13, C82, C83, C84, CAP, CERM, 4.7 µF, 16 V, +/- 10%,9 C85, C87, C233, C234, MuRata GRM188R61C475KAAJ 0603 FittedX5R, 0603C251CAP, CERM, 8.2 pF, 25 V, +/- 5%,1 C14 MuRata GRM1555C1E8R2CA01D 0402 FittedC0G/NP0, 0402

C15, C22, C27, C28, CAP, CERM, 0.1 µF, 16 V, +/- 10%,11 C29, C30, C55, C56, MuRata GRM155R71C104KA88D 0402 FittedX7R, 0402C57, C58, C206CAP, CERM, 1 µF, 10 V, +/- 10%,3 C16, C100, C101 MuRata GRM188R71A105KA61D 0603 FittedX7R, 0603CAP, CERM, 470 pF, 50 V, +/- 10%,1 C21 MuRata GRM155R71H471KA01D 0402 FittedX7R, 0402

C23, C91, C92, C93, CAP, CERM, 2.2 µF, 10 V, +/- 10%,10 C94, C95, C96, C97, MuRata GRM188R71A225KE15D 0603 FittedX7R, 0603C98, C201



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Table 34. BOM (continued)MANUFACTURERQTY REFERENCE PART DESCRIPTION MANUFACTURER PCB FOOTPRINT NOTEPARTNUMBER

C24, C99, C199, C203,C204, C207, C209,C236, C237, C239, CAP, CERM, 0.1 µF, 10 V, +/- 10%,17 MuRata GRM155R71A104KA01D 0402 FittedC244, C245, C246, X7R, 0402C247, C248, C249,C250C25, C26, C38, C39,C42, C43, C44, C47,C48, C49, C50, C53, CAP, CERM, 1000 pF, 16 V, +/- 10%,24 MuRata GRM033R71C102KA01D 0201 FittedC54, C65, C66, C69, X7R, 0201C70, C71, C74, C75,C76, C77, C197, C210C31, C32, C60, C61, CAP, CERM, 27 pF, 50 V, +/- 5%,8 C192, C193, C240, MuRata GRM1555C1H270JA01D 0402 FittedC0G/NP0, 0402C241

CAP, CERM, 1000 pF, 2000 V, +/-2 C33, C59 Johanson Technology 202R18W102KV4E 1206_190 Fitted10%, X7R, 1206_190C35, C37, C41, C46,C52, C64, C68, C73,C79, C102, C103, C105,C106, C108, C109,C111, C112, C114,C115, C117, C118,C119, C120, C121,C122, C123, C124,C125, C127, C128,C129, C130, C132,C133, C134, C135, CAP, CERM, 0.01 µF, 10 V, +/- 10%,69 MuRata GRM033R71A103KA01D 0201 FittedC136, C137, C138, X7R, 0201C142, C143, C144,C146, C147, C172,C173, C174, C175,C176, C177, C178,C179, C180, C181,C182, C183, C184,C186, C187, C188,C189, C190, C191,C195, C196, C200,C205, C235, C243C139, C140, C141, CAP, CERM, 1 µF, 10 V, +/- 20%,4 Samsung CL03A105MP3NSNC 0201 FittedC145 X5R, 0201



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C150, C151, C152,C153, C154, C155,C156, C157, C158,C159, C160, C161,C162, C163, C164,C165, C166, C167, CAP, CERM, 0.1 µF, 10 V, +/- 10%,36 Samsung CL03A104KP3NNNC 0201 FittedC168, C169, C208, X5R, 0201C213, C214, C215,C216, C217, C218,C219, C220, C221,C222, C223, C224,C228, C229, C230

CAP, CERM, 18 pF, 50 V, +/- 5%,2 C194, C198 MuRata GRM1555C1H180JA01D 0402 FittedC0G/NP0, 04021 D1 Diode, Schottky, 60V, 1A, SMA ON Semiconductor MBRA160T3G SMA Fitted5 D2, D3, D6, D11, D14 LED, Green, SMD OSRAM LG L29K-G2J1-24-Z LG L29K_GREEN Fitted2 D4, D9 LED, Yellow, SMD OSRAM LY L29K-J1K2-26-Z LY L29K_Yellow Fitted2 D5, D10 LED, Red, SMD OSRAM LS L29K-G1J2-1-Z LS L29K_Red Fitted2 D7, D12 LED, Orange, SMD OSRAM LO L29K-J2L1-24-Z LO L29K_Orange Fitted2 D8, D13 Diode, TVS, Bi, 5 V, 300 W, SOT-23-6 Semtech SRV05-4.TCT SOT-23-6 Fitted

Machine Screw, Round, #4-40 x 1/4,4 H1, H2, H3, H4 B&F Fastener Supply NY PMS 440 0025 PH NY PMS 440 0025 PH FittedNylon, Philips panhead4 H5, H6, H7, H8 Standoff, Hex, 0.5"L #4-40 Nylon Keystone 1902C Keystone_1902C Fitted2 J1, J3 Header, 100mil, 2x1, Tin, TH Sullins Connector Solutions PEC02SAAN CONN_PEC02SAAN Fitted1 J2 Power Jack, mini, 2.1mm OD, R/A, TH Switchcraft RAPC722X CONN_RAPC722X Fitted

Modular Jack(Shielded), Gold, R/A,2 J4, J5 Molex 43202-8916 Molex_43202-8916 FittedTHConncetor, micro SD Card, 1.1 mm,1 J6 Molex 502774-0891 Molex_502774-0891 FittedR/A, SMTReceptacle, 0.65 mm, 5x1, Gold, R/A,1 J7 FCI 10104111-0001LF FCI_10104111-0001LF FittedSMTInductor, Shielded Drum Core, Ferrite,1 L1 Coilcraft LPS3010-102MRB LPS3010 Fitted1 µH, 1.5 A, 0.085 ohm, SMDInductor, Shielded Drum Core, Ferrite,1 L2 Coilcraft MSS1260-153MLB MSS1260 Fitted15 µH, 3.5 A, 0.03 ohm, SMDInductor, Shielded, Ferrite, 2.2 µH,3 L3, L4, L5 TDK VLCF5020T-2R2N2R6-3 VLCF5020 Fitted2.62 A, 0.043 ohm, SMD

L6, L7, L9, L10, L11, Ferrite Bead, 150 ohm @ 100 MHz, Laird-Signal Integrity6 LI0805H151R-10 0805_HV FittedL12 0.8 A, 0805 Products



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Common Mode Filter, 90 Ohm, 61 L8 TDK ACM2012H-900-2P-T00 TDK_ACM2012H-900-2P-T00 FittedGHz, SMD1 R1 RES, 10 ohm, 5%, 0.25W, 0603 Vishay-Dale CRCW060310R0JNEAHP 0603 Fitted1 R2 RES, 453 k, 1%, 0.063 W, 0402 Vishay-Dale CRCW0402453KFKED 0402 Fitted1 R3 RES, 750, 5%, 0.063 W, 0402 Vishay-Dale CRCW0402750RJNED 0402 Fitted2 R4, R119 RES, 100 k, 1%, 0.063 W, 0402 Vishay-Dale CRCW0402100KFKED 0402 Fitted1 R5 RES, 80.6 k, 1%, 0.063 W, 0402 Vishay-Dale CRCW040280K6FKED 0402 Fitted3 R6, R36, R65 RES, 1.00 M, 1%, 0.063 W, 0402 Vishay-Dale CRCW04021M00FKED 0402 Fitted1 R7 RES, 249 k, 1%, 0.063 W, 0402 Vishay-Dale CRCW0402249KFKED 0402 Fitted

R8, R9, R10, R12, R15,R71, R139, R140, R141,14 RES, 0, 5%, 0.1 W, 0603 Vishay-Dale CRCW06030000Z0EA 0603 FittedR142, R143, R144,R145, R147

1 R13 RES, 360, 5%, 0.063 W, 0402 Vishay-Dale CRCW0402360RJNED 0402 Fitted1 R14 RES, 150 k, 1%, 0.063 W, 0402 Vishay-Dale CRCW0402150KFKED 0402 Fitted1 R16 RES, 110 k, 1%, 0.063 W, 0402 Vishay-Dale CRCW0402110KFKED 0402 Fitted

R19, R43, R44, R46,7 RES, 0, 5%, 0.063 W, 0402 Vishay-Dale CRCW04020000Z0ED 0402 FittedR47, R50, R51RES, 0, 5%, 0.0625 W, Resistor Array1 R20 Panasonic EXB-2HVR000V RESCAXS_EXB-2HV Fitted- 8x1

R21, R38, R41, R67,8 RES, 10.0 k, 1%, 0.063 W, 0402 Vishay-Dale CRCW040210K0FKED 0402 FittedR68, R136, R138, R158R22, R24, R32, R37,8 RES, 75.0, 1%, 0.1 W, 0603 Vishay-Dale CRCW060375R0FKEA 0603 FittedR42, R48, R58, R64R23, R29, R45, R55,

8 R146, R152, R153, RES, 4.7 k, 5%, 0.063 W, 0402 Vishay-Dale CRCW04024K70JNED 0402 FittedR165R25, R26, R27, R33,

9 R52, R53, R54, R60, RES, 560, 5%, 0.063 W, 0402 Vishay-Dale CRCW0402560RJNED 0402 FittedR66R28, R30, R49, R56,5 RES, 11.0 k, 1%, 0.063 W, 0402 Vishay-Dale CRCW040211K0FKED 0402 FittedR59R31, R34, R57, R61,5 RES, 2.49 k, 1%, 0.063 W, 0402 Vishay-Dale CRCW04022K49FKED 0402 FittedR62

RES, 22, 5%, 0.0625 W, Resistor1 R69 Panasonic EXB-2HV220JV RESCAXS_EXB-2HV FittedArray - 8x1



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R70, R84, R94, R95,R96, R120, R121, R122,

17 R123, R124, R125, RES, 10 k, 5%, 0.063 W, 0402 Vishay-Dale CRCW040210K0JNED 0402 FittedR131, R135, R137,R148, R149, R150R72, R73, R74, R75,

10 R77, R78, R79, R80, RES, 22, 5%, 0.063 W, 0402 Vishay-Dale CRCW040222R0JNED 0402 FittedR81, R82R76, R117, R118, R154,5 RES, 2.2 k, 5%, 0.063 W, 0402 Vishay-Dale CRCW04022K20JNED 0402 FittedR156

3 R99, R126, R127 RES, 49.9, 1%, 0.063 W, 0402 Vishay-Dale CRCW040249R9FKED 0402 Fitted2 R100, R129 RES, 1.00 k, 1%, 0.063 W, 0402 Vishay-Dale CRCW04021K00FKED 0402 Fitted

R101, R103, R104,R105, R106, R107,12 RES, 100 k, 5%, 0.063 W, 0402 Vishay-Dale CRCW0402100KJNED 0402 FittedR108, R109, R110,R111, R115, R116

RES, 47, 5%, 0.0625 W, Resistor3 R128, R130, R133 Panasonic EXB-2HV470JV RESCAXS_EXB-2HV FittedArray - 8x11 R132 RES, 240, 5%, 0.063 W, 0402 Vishay-Dale CRCW0402240RJNED 0402 Fitted1 R134 RES, 47, 5%, 0.063 W, 0402 Vishay-Dale CRCW040247R0JNED 0402 Fitted1 R155 RES, 4.75 k, 1%, 0.063 W, 0402 Vishay-Dale CRCW04024K75FKED 0402 Fitted1 R157 RES, 12.1 k, 1%, 0.063 W, 0402 Vishay-Dale CRCW040212K1FKED 0402 Fitted

SWITCH TACTILE SPST-NO 0.05A Omron Electronic1 S1 B3U-1000P SW_B3U-1000P Fitted12V Components2 T1, T2 Transformer, 325 uH, SMT Pulse Engineering HX5008FNL PULSE_HX5008FNL Fitted

3.5V to 60V 2A Synchronous Step-1 U1 Texas Instruments LM46002PWP PWP0016A_N FittedDown Voltage Regulator, PWP0016ASingle Output LDO, 1 A, Fixed 3.3 VOutput, 2.2 to 5.5 V Input, with

1 U2 Reverse Current Protection, 6-pin Texas Instruments TPS73733DCQ DCQ0006A_N FittedSOT-223 (DCQ), -40 to 125 degC,Green (RoHS & no Sb/Br)1A SIMPLE SWITCHER® Nano

1 U3 Module with 5.5V Maximum Input Texas Instruments LMZ10501SIL SIL0008A FittedVoltage, SIL0008A350mA, Ultra-Low VIN, RF Low-

1 U5 Dropout Linear Regulator with Bias Texas Instruments TPS72011DRV DRV0006A FittedPin, DRV0006A



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Robust, Low Power 10/100/10002 U6, U12 Ethernet Physical Layer Transceiver, Texas Instruments DP83867IRPAPR PAP0064M_N Fitted

PAP0064M1, 4, 6 CHANNEL PROTECTIONSOLUTION FOR SUPER-SPEED (UP2 U7, U9 Texas Instruments TPD4E05U06DQA DQA0010A FittedTO 6 GBPS) INTERFACE,DQA0010ASingle 2-Input Positive-AND Gate,1 U11 Texas Instruments SN74AHC1G08DCK DCK0005A_N FittedDCK0005AIntegrated Power-Management Unit1 U13 Texas Instruments TPS65910A3A1RSL RSL0048A FittedTop Specification, RSL0048ASingle Output High PSRR LDO, 150mA, Fixed 1.8 V Output, 2.5 to 6.5 V

1 U14 Input, with Low IQ, 6-pin WSON Texas Instruments TPS71718DSER DSE0006A Fitted(DSE), -40 to 125 degC, Green (RoHS& no Sb/Br)

1 U15 Sitara Processors, ZCZ0324A Texas Instruments AM3359BZCZA80 ZCZ0324A FittedLOW-POWER DUAL 2-INPUT1 U16 Texas Instruments SN74AUP2G08DCU DCU0008A_N FittedPOSITIVE-AND GATE, DCU0008A

1 U17 2GBIT DDR3 SDRAM, 96-FBGA Micron Technology MT41J128M16JT-125K TR 96-FBGA FittedLow-Capacitance + / - 15 kV ESDProtection Array for High-Speed Data

1 U18 Interfaces, 6 Channels, -40 to +85 Texas Instruments TPD6E001RSER RSE0010A FitteddegC, 10-pin UQFN (RSE), Green(RoHS & no Sb/Br)256 kb I2C CMOS Serial EEPROM,1 U19 ON Semiconductor CAT24C256WI-GT3 SOIC-8 FittedSOIC-8Single Output LDO, 3 A, 2.375 to 3.5V Input, with DDR Termination, 10-pin1 U20 Texas Instruments TPS51200DRCR DRC0010A FittedSON (DRC), -40 to 85 degC, Green(RoHS & no Sb/Br)USB ESD Solution with Power Clamp,4 Channels, -40 to +85 degC, 6-pin1 U21 Texas Instruments TPD4S012DRYR DRY0006A FittedSON (DRY), Green (RoHS & noSb/Br)Dual High Speed USB To

1 U22 Multipurpose UART/FIFO IC, LQFP- FTDI FT2232HL-REEL LQFP64_N Fitted642K Microwire Compatible Serial1 U23 Microchip 93LC56B-I/OT SOT-23-6 FittedEEPROM, SOT-23-6Single Inverter Buffer/Driver With1 U24 Texas Instruments SN74LVC1G06DCK DCK0005A_N FittedOpen-Drain Output, DCK0005A



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2 Y1, Y2 Crystal, 25 MHz, 18 pF, SMD Abracon Corportation ABM3-25.000MHZ-D2Y-T XTAL_ABM3 Fitted1 Y3 Crystal, 24 MHz, 18 pF, SMD Abracon Corportation ABM3-24.000MHZ-D2Y-T XTAL_ABM3 Fitted1 Y4 Crystal, 32.768kHz, 12.5pF, SMD Epson MC-306 32.7680K-A0:ROHS XTAL_MC-306 Fitted1 Y5 Crystal, 12 MHz, 18 pF, SMD Abracon Corportation ABM3-12.000MHZ-D2Y-T XTAL_ABM3 Fitted

CAP, CERM, 0.022 µF, 50 V, +/- 10%,0 C12 MuRata GRM155R71H223KA12D 0402 Not FittedX7R, 0402CAP, CERM, 1 µF, 10 V, +/- 10%,0 C19, C20 MuRata GRM188R71A105KA61D 0603 Not FittedX7R, 0603CAP, CERM, 1000 pF, 2000 V, +/-0 C34, C62 AVX 1812GC102KA1 1812 Not Fitted10%, X7R, 1812CAP, CERM, 0.01 µF, 10 V, +/- 10%,0 C238 MuRata GRM033R71A103KA01D 0201 Not FittedX7R, 0201CAP, CERM, 0.1 µF, 10 V, +/- 10%,0 C242 MuRata GRM155R71A104KA01D 0402 Not FittedX7R, 0402CONN SHRD HDR HDR 20 POS0 J8 Samtec TFM-110-02-S-D-A-K-TR Samtec_TFM-110-02-S-D-A-K Not Fitted1.27MM SLDR ST SMD

R11, R159, R160, R161,0 RES, 0, 5%, 0.1 W, 0603 Vishay-Dale CRCW06030000Z0EA 0603 Not FittedR162, R163, R164R17, R18, R39, R40,0 RES, 0, 5%, 0.063 W, 0402 Vishay-Dale CRCW04020000Z0ED 0402 Not FittedR63

0 R35 RES, 22, 5%, 0.063 W, 0402 Vishay-Dale CRCW040222R0JNED 0402 Not FittedR83, R85, R86, R87,

0 R88, R89, R90, R91, RES, 10 k, 5%, 0.063 W, 0402 Vishay-Dale CRCW040210K0JNED 0402 Not FittedR92, R93, R97, R98R102, R112, R113,0 RES, 100 k, 5%, 0.063 W, 0402 Vishay-Dale CRCW0402100KJNED 0402 Not FittedR114

0 R151 RES, 4.7 k, 5%, 0.063 W, 0402 Vishay-Dale CRCW04024K70JNED 0402 Not FittedSingle Output LDO, 300 mA, Fixed 1.8V Output, 2 to 5.5 V Input, with Low0 U4 Texas Instruments TLV70218DBVR DBV0005A_N Not FittedIQ, 5-pin SOT-23 (DBV), -40 to 125degC, Green (RoHS & no Sb/Br)1, 4, 6 CHANNEL PROTECTIONSOLUTION FOR SUPER-SPEED (UP0 U8, U10 Texas Instruments TPD4E05U06DQA DQA0010A Not FittedTO 6 GBPS) INTERFACE,DQA0010A



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8.3 Layer PlotsTo download the layer plots, see the design files at TIDA-00204.

Figure 77. Top Overlay Figure 78. Top Solder Mask

Figure 79. Top Layer Figure 80. Mid Layer 1



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Figure 81. Mid Layer 2 Figure 82. Mid Layer 3

Figure 83. Mid Layer 4 Figure 84. Mid Layer 5



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Figure 85. Mid Layer 6 Figure 86. Bottom Layer

Figure 87. Bottom Solder Mask Figure 88. Bottom Overlay



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Figure 89. Drill Drawing Figure 90. Board Dimensions

8.4 PCB Layout Guidelines

8.4.1 Layer StackEnsure that the differential signal layers have a reference ground and that the PCB differential signaltraces are matched to 100-Ω impedance. For the single-ended traces, the board is matched to 50 Ω.

A layer size of 0.018 mm was chosen for the top and mid layers. This size can be defined as the basethickness. When actually building the board, the mid layers will decrease in size and the outer layers willincrease in size. This means that the expected top layer thickness would be 0.040 mm and a mid layerwould have an expected thickness of 0.012 mm. This decrease and increase in thickness varies on themanufacturer. This variation is why it is very important when working with high-speed differential signals todefine the layer stack and double check with the PCB manufacturer to ensure that the expectedimpedances are achieved.

Figure 91. Layer Stack

For a less complex processor design, the PCB layers for DP83867IR routing can be reduced to fourlayers. See the DP83867IR datasheet for examples [1].



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Termination for RGMII RX on top layer

U12

U15

GND via to ensure GND matching when changing

layers on signals

Length matching for RGMII RX on layer 3

Length matching for RGMII TX on layer 6

Termination for RGMII TX on top layer


8.4.2 Layout RGMII SignalsLooking at the layout, each RX or TX group of the RGMII signals are routed on the same layer withmatched trace length as outlined in Section 4. To aim for routing, the signals minimized the trace length ofboth RGMII1 and RGMII2 interfaces.

A second important point is that when changing layers, a GND via is added next to the signal via toensure a good matching as well offer a current return path close to the signal.

The PCB signals are impedance controlled to 50 Ω, and have series line termination. For the seriestermination at both the PHYs, 0-Ω resistors were chosen due to the DP83867IR internal 50-Ω impedance.These resistors were only added for test and debug. For the AM3359, 22-Ω series termination resistorswere chosen.

Figure 92. Layout Guidelines for RGMII Signals



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TI TVS diode array TPD4E05U06 with easy

routing pinout

T1U6

Clearance between signal lines and GND and Earth/Shield

Differential length matching and routing for signals from

transformer to RJ45

Differential length matching and routing for signals from

PHY to transformer

To ensure shortest routing of the signals a layer change was

done due to pinout of RJ45

J4


8.4.3 Layout for the Differential Gigabit Ethernet SignalsFrom the PHY to the magnetics the differential pairs are routed on the top layer with differentialimpedance control matching of 100 Ω. The reference GND is on mid layer 1. This is achieved by ensuringthat isolation between top layer and mid layer 1 is smaller than the surrounding planes.

From the magnetics to the RJ45 the differential pairs A, C, and D are routed on the top layer while pair Bis routed on mid layer 2. This is due to crossing the signals on the RJ45 Ethernet jack. Again, thedifferential pairs are impedance matched to 100 Ω with reference to GND on mid layer 1. Due to the GNDbeing mid layer 1, there is no need for GND vias added around the B signal.

This routing achieves the minimum possible trace lengths from PHY to magnetics, magnetics to RJ45, andhere a maximum delta of the trace lengths of 1 mm between the differential pairs.

Figure 93. Layout Guidelines for PHY Differential Signals



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GND cut in mid layer 1 around the LMZ10501 device to reduce noise

coupling

T1U6

1v1 power rail of the PHY added as a solid supply plane

below each PHY

Ensure wide traces that provide the 1v1 and 2v5

power rail

Added additional vias to insure the best possible thermal release of LDO

GND cut ring in mid layer 1 around the LDOs to further reduce noise

coupling

GND guard ring in mid layer 1 around the

crystals to further reduce noise coupling


8.4.4 Layout PHY Power SupplyFor the 2.5-V LMZ rail, add a keep-out GND cut in mid layer 1 to decrease noise coupling. To additionalthermal management, add as many vias as possible on the powerPAD of the 1.1-V and 1.8-V LDO andadd an additional thermal release plane on the bottom side of the board.

Ensure wide enough traces when adding the 1.1-V and 2.5-V power rails. The 1.1-V rail is added as asolid supply plane below each PHY. Figure 94 shows the PCB layout of TIDA-00204.

Figure 94. Layout Guidelines for the PHY Power Supply



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GND cut in mid layer 1 around the

LM46002 device to reduce noise coupling

U1

Current loop as small as possibleNoise sensitive signals removed

from noisy ground plane

J1

Vias around the GND cut to reduce noise

coupling


8.4.5 Layout of the 24-V to 5-V DC/DC Buck (LM46002)Follow the layout guidelines from the LM46002 datasheet. Cut out layer 1 under LM46002 to avoidcoupling into other layers. Ensure that current loop of the device is maintained as small as possible. Theexample layout of the LM46002 on TIDA-00204 is shown in Figure 95.

Figure 95. Layout Guidelines for 24-V to 5-V DC/DC Buck With LM46002

8.4.6 Layout Sitara Power SupplyFor the Sitara power supply, the following guidelines were considered.

Routing the power tracks to the Sitara each power track as a GND plane as reference GND, mid layer 4used as supply layer with supply planes for each high current power track. VMMC, VAUX33, and VAUX1power track added in mid layer 2 and VDIG2 and VPLL power track added in mid layer 6.

VDAC intentionally does a u-trace as the DAC functionality is not used. If this functionality is needed, addadditional traces for this power rail.

8.4.7 Layout DDR3Layer 6 is GND reference for DDR3 (90-µm dielectric distance layer to layer). The other layers are 400 µmaway. All DDR3 signals are on one layer.



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8.5 Altium ProjectTo download the Altium project files, see the design files at TIDA-00204.

8.6 Gerber FilesTo download the Gerber files, see the design files at TIDA-00204.



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Software Files www.ti.com

9 Software FilesTo download the software files, see the design files at TIDA-00204.

10 References

1. Texas Instruments, DP83867IR Robust, Low Power 10/100/1000 Ethernet Physical Layer Transceiver,DP83867 Datasheet (SNLS484).

2. Texas Instruments, AN-1469 PHYTER Design & Layout Guide, Application Report (SNLA079).3. Texas Instruments, EN55011-Compliant, Industrial Temperature 10/100-Mbps Ethernet PHY Brick, TI

Design (TIDU515).4. Texas Instruments, PCB Design Guidelines For Reduced EMI, Application Report (SZZA009).5. Texas Instruments, AM335x Sitara™ Processors, AM335x Datasheet (SPRS717).6. Texas Instruments, AM335x Sitara™ Processors, AM335x Technical Reference Manual (SPRUH73).7. Texas Instruments, TPS65910Ax User's Guide For AM335x Processors, TPS65910Ax User’s Guide

(SWCU093).8. Texas Instruments, TI Network Developer's Kit (NDK) v2.24, NDK User’s Guide (SPRU523).9. Texas Instruments, Sitara Wiki Page (http://processors.wiki.ti.com/index.php/Sitara).10. Texas Instruments, AM3359 Industrial Communications Engine, Evaluation Module, Part #

TMDSICE3359 (http://www.ti.com/tool/tmdsice3359).11. Texas Instruments, LM46002 SIMPLE SWITCHER® 3.5 V to 60 V 2 A Synchronous Step-Down

Voltage Converter, LM46002 Datasheet (SNVSA13).12. IEEE, 802.3-2012 – IEEE Standard for Ethernet, Section Three (http://standards.ieee.org).13. HP, Reduced Gigabit Media Independent Interface (RGMII) 4/1/2002 Version 2.0: Reduced Pin-count

Interface for Gigabit Ethernet Physical Layer Devices(http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf).

14. Dirk S. Mohl, IEEE 1588 Precision Time Protocol (http://www.ieee1588.com).15. CISPR11 / EN 55011+A1:2010-01-31, EN 55011: Industrial, scientific and medical equipment - Radio-

frequency disturbance characteristics - Limits and methods of measurement.16. IEC, Adjustable speed electrical power drive systems - Part 3: EMC requirements and specific test

methods, IEC 61800-3 ed2.0: 2004-08-12.17. IEC, Amendment 1 - Adjustable speed electrical power drive systems - Part 3: EMC requirements and

specific test methods, IEC 61800-3-am1 ed2.0: 2011-11-14.18. Micron, TN-41-08: Design Guide for Two DDR3-1066 UDIMM Systems.19. Wireshark, v1.12.3 (http://www.wireshark.org).20. TeraTerm, v4.76 (http://ttssh2.sourceforge.jp/).21. GCD-Printlayout GmbH (http://www.gcd-printlayout.de/).22. MinGW, Minimalist GNU for Windows (http://www.mingw.org/).23. SourceForge, Win32 Disk Imager (http://sourceforge.net/projects/win32diskimager/).

11 About the AuthorsKRISTEN MOGENSEN is a system engineer in the Industrial Systems Motor Drive team at TexasInstruments. Mogensen is responsible for developing reference designs for industrial drives.

MARTIN STAEBLER is a system engineer in the Industrial Systems Motor Drive team at TexasInstruments. Staebler is responsible for developing reference designs for industrial drives.



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http://www.ti.com/lit/pdf/SNLS484

http://www.ti.com/lit/pdf/SNLA079

http://www.ti.com/lit/pdf/TIDU515

http://www.ti.com/lit/pdf/SZZA009

http://www.ti.com/lit/pdf/SPRS717

http://www.ti.com/lit/pdf/SPRUH73

http://www.ti.com/lit/pdf/SWCU093

http://www.ti.com/lit/pdf/SPRU523

http://processors.wiki.ti.com/index.php/Sitara

http://www.ti.com/tool/tmdsice3359

http://www.ti.com/lit/pdf/SNVSA13

http://standards.ieee.org

http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf

http://www.ieee1588.com

http://www.wireshark.org

http://ttssh2.sourceforge.jp/

http://www.gcd-printlayout.de/

http://www.mingw.org/

http://sourceforge.net/projects/win32diskimager/


www.ti.com Revision History

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