Electrostatic Discharge (ESD) - Queen's...

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Electrostatic Discharge (ESD) ELEC 353 – Electronics II Instructor: Prof. C. Saavedra

Transcript of Electrostatic Discharge (ESD) - Queen's...

Page 1: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Electrostatic Discharge (ESD)

ELEC 353 – Electronics II

Instructor: Prof. C. Saavedra

Page 2: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

What is ESD?

• A sudden current flow between two objects that are at different potentials

• ESD currents are large and of short duration

• ESD can damage or destroy electronic circuits, which can lead to broader system‐level failure in complex equipment, machinery or life‐critical applications

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Page 3: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

ESD symbols used in industry

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Page 4: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Causes of ESD events

• ESD events occur when a charge imbalance exists between an IC and another object

• That charge imbalance can be due to:

– Moving IC parts from one place to another during manufacturing and distribution

– Bringing the IC into contact with a person or a moving object

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Page 5: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Effects of ESD

• ESD events can occur throughout a chip’s product life‐span. 

• It begins at the chip fabrication facility, where there are lots of moving objects and ionized chemicals.

• Wafer yield is reduced due to ESD events because:– A discharge can rupture gate oxides and damage p‐n junctions, both of which can result in current leakage

– A discharge erodes the pattern defined on the chrome mask and hence the circuit is printed with a damaged pattern

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Page 6: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Types of ESD Damage

• An ESD event creates high current densities and high electric fields, both of which cause damage.

• Current‐induced damage: 

– metal interconnects, resistors, and other thin films melt due to joule heating, leading to “open circuits” in the chip

– In the case of high‐resistivity polysilicon, if it does not become an open circuit its resistance can noticeably decrease, thereby compromising is reliability

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Page 7: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Consequences of joule heating

http://static‐sol.com

http://allaboutcircuits.com

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Page 8: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Damage due to high electric fields

• Dielectric rupture: it occurs when the field strength is very high and the dielectric breaks down, often at sharp corners where the field intensity is greatest. 

• When a rupture happens, a conducting path is created across the plates of a capacitor or between the gate terminal and the channel of a MOSFET

• The conductive path can be just a tiny filament of   0.1 μm in diameter, but it’s enough compromise the circuit

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Page 9: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

High electric fields can also...

Give electrons enough energy to overcome the oxide‐silicon potential barrier causing charge injection and:

• Shifts in the threshold voltage of a MOSFET• An increase in the base current of a bipolar device, thereby reducing the current‐gain, β

• High leakage currents in reversed‐biased diodes

The effects of charge injection are less dramatic than dielectric breakdown, yet they shouldn’t be ignored

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Page 10: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Towards an ESD event: charge generation

There are 3 major causes of charge generation.

1) Triboelectrification – the charging of a body through contact and then separation. 

Everyday examples: o a person walking across a carpeto rubbing an insulating material against another object

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Page 11: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

From http://www.technick.net11

Page 12: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Relative humidity and charge build‐up

Relative Humidity

Means of Charge Generation 10‐25% 65‐90%

Walking across carpet  35,000V  1,500V 

Walking across vinyl tile  12,000V  250V 

Worker at bench  6,000V  100V 

Poly bag picked up from bench  20,000V  1,200V 

Chair with urethane foam  18,000V  1,500V 

From http://www.technick.net12

Page 13: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Charge generation (cont’d) 

2) Inductive charging – when an object “B” comes into close proximity to a charged object “A” and by momentarily grounding “B” a charge is developed on that object.

Moving away from “A” and grounding “B” a second time releases the stored charge.  This type of ESD event can create very large current pulses.

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Page 14: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

From Vinson & Liou

Example situation ...but induction is not always bad!

http://www.wildcharge.com/

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Page 15: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Charge generation (cont’d)

3) Conductive charging – requires the physical contact of two objects at different potentials.  It is a charge‐balancing process.

From Vinson & Liou

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Page 16: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Equivalent circuits to model ESD events

The human body model (HBM)

From Vinson & Liou

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Page 17: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Equivalent circuits to model ESD events

The Machine Model (MM)

From Vinson & Liou

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Page 18: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

ESD Protection Circuits

Zener Clamp

• A simple protection circuit that does not take up much area• Have an internal series resistance of 100 to 300 Ω, which limits their usefulness

From Hastings

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Page 19: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Two‐stage Zener clamp

ESD Protection Circuits

From Hastings19

Page 20: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Buffered Zener clamp

ESD Protection Circuits

From Hastings

• The NPN transistor reducesthe effective series resistanceof the Zener diode by a largeamount

• This structure can provide upto 2 kV of HBM protectionand 200 V of MM protection

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Page 21: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Anti‐parallel diode clamps

ESD Protection Circuits

From Hastings

• The anti‐parallel topology is of interest when there are multipleground pins on a chip and not all of them are connected to thesubstrate or the same super‐node. 

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Page 22: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Protection circuit for positive and negativevoltage spikes

ESD Protection Circuits

From Wu et al22

Page 23: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Reducing the risk of ESD events

• Using a dissipative mat in the work area will allow the charge to bleed off in a controlled manner. This way, high current spikes are avoided and low voltage levels are maintained.

• A conductive mat disperses the charge more quickly and should be used around extra sensitive equipment.

• Both conductive and dissipative mats should be properly grounded using a strap.

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Page 24: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Dissipative mat Conductive mat

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Page 25: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Reducing the risk of ESD events

An area ionizer is a piece of lab equipment that generates ions and makes the surrounding air more conductive, thereby reducing static build‐up

Example of a work bench with good ESD protection

From Vinson & Liou

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Page 26: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Reducing the risk of ESD events

• Use anti‐static bags and containers to store parts

• Anti‐static bags contain a film of conductive material which functions as a small Faraday cage thus preventing charge build‐up

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Page 27: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

Conclusion

• ESD can cause serious short‐term and long‐term damage to electronic circuits and systems.

• Many factors influence the strength of an ESD event, including the relative humidity in the environment.

• Circuit techniques exist to protect chips when an ESD event happens. 

• While it is unrealistic to totally eliminate ESD events, it is possible to reduce the risk of ESD events by using special containers and working in an ESD‐protected environment, for example.

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Page 28: Electrostatic Discharge (ESD) - Queen's Universitypost.queensu.ca/.../ELEC-353-Electrostatic-Discharge-ESD.pdfA. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River,

References

The information and images used in the previous slides came from the references below and they are fully acknowledged.

J. E. Vinson and J. J. Liou, “Electrostatic Discharge in Semiconductor Devices: An Overview” Proceedings of the IEEE, Vol. 86, No. 2, pp. 399‐418, Feb. 1998.

A. Hastings, The Art of Analog Layout, Prentice Hall: Upper Saddle River, New Jersey, 2001.

C.‐Y. Wu et al, “A New on‐chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI,” IEEE J. Solid‐State Circuits, Vol. 27, No. 3, pp. 274‐280, March 1992.

“The Prevention and Control of Electrostatic Discharge (ESD)”, Mini‐Circuits Application Note # AN‐40‐005.

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