Electronique - Lattice (An6012)Analog Layout and Grounding Techniques

an6012_01 1 September 1999

Analog Layout andGrounding Techniques

-10 to +10

OA1

IA1

IA2

IN1

2.5V OUT1-10 to +10

Figure 1. A Single PACblock

Introduction

When low-level or high-precision circuitry is being de-signed, a lot of care is usually given to the details of thecircuit schematic and how the signal runs are routed. Butthe way the circuitry grounds are handled is as importantas how the signal runs are handled. A small groundingerror in just one location could potentially create long-term headaches once the board is powered up. Carefulrouting and decoupling of the power busses is also veryimportant. This application note discusses a number oftechniques for obtaining optimal performance from aprinted circuit board layout involving analog parts. It isintended to help obtain the best performance possiblefrom the ispPAC™ family of programmable analog cir-cuits. The differential instrumentation-amplifier inputs ofthe ispPAC10 and ispPAC20, and the excellent com-mon-mode rejection that they provide, will be shown toassist in reducing many common layout problems. Theon-chip gain-setting resistors will also prove to be advan-tageous. The guidelines in grounding, power distributionand layout contained in this application note will assistthe reader in improving or alleviating many of theselayout problems.

The topics below will be covered:

• A brief description of the ispPAC device family

• Grounding and ground planes

• Power planes and power decoupling

• Analog runs vs. digital runs

• The advantages of using differential circuitry

• Suggestions for reducing magnetically-induced in-terference.

ispPAC Background

The ispPAC family of Programmable Analog Circuitsfrom Lattice Semiconductor represents a new level ofintegration and flexibility for general-purpose analogsignal processing. It brings the concept of In-SystemProgrammability (ISP™) to the world of analog circuits.Circuits can be designed and simulated using the Win-dows®-based PAC-Designer™ software. Once thesimulated performance is shown to be as desired, thedesign can be downloaded to the ispPAC device. Thedevice’s in-circuit performance, and even its functional-ity, can thus be changed without lifting a soldering iron orchanging any external parts.

The basic ispPAC gain block is shown in Figure 1. Theintegrated programmable analog macrocells in this fig-ure are collectively known as a PACblock™. TheispPAC10 consists of four identical PACblocks, and theispPAC20 includes two of these blocks as well as an 8-bit DAC and two comparators. Each PACblock iscomposed of a differential-output summing amplifier (OA)and two differential-input instrumentation amplifiers (IA)with variable gains of ±1 to ±10 in integer steps. The OA’sfeedback path contains a fixed resistor, which can beswitched in or out, as well as a programmable capacitorarray that allows for more than 120 poles when theispPAC device is used as an active filter. Each PACblockhas the ability to sum two differential signals with inde-pendently selectable gain and inversion settings and toact as a gain element (with the feedback switch closed)or as an integrator (with the feedback switch open).

The gain settings, feedback, capacitor values and inter-connects between PACblocks are configurable throughnonvolatile E2CMOS® cells internal to the ispPAC de-vices. The device configuration is set by software and

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SystemPower

Individualboard or module

Figure 2. “Star” Groundingdownloaded in less than 250 milliseconds via a JTAG-compatible ispDOWNLOAD™ cable. Refer to theispPAC10 Data Sheet for more details on the specifics ofthe device.

The following describes techniques for improving analoglayouts in general and explains the advantages of incor-porating the ispPAC devices.

Grounding and Ground Planes

System “Star” Grounds

In equipment design, there are a number of differentclasses or types of grounds. Two of them are the “systemground,” which is the ground that is shared by all theboards or modules in the system, and the “board ground,”which is the ground as it exists on a given circuit board.The system ground should be connected to the variousboards in a “star” fashion, with each board or modulehaving its own ground or common return lead back to acentral location that is the common reference point of thesystem power supply (Figure 2). These connectionsshould be made with large-diameter buss wire or verywide PCB runs to reduce resistive and inductive losses.This “star” connection (so named because it looks like astar) prevents currents drawn by one board or modulefrom modulating the current drawn by another board. Inmany systems, the grounding of the various boards canbecome somewhat of a problem, since cables runningbetween these boards cause ground conflicts with the“star” ground system. The problems become even moreacute if a number of individual systems or instruments aremounted in a rack, which is itself conductive and will haveits own ground scheme. Cables running between theseinstruments will also cause a system ground conflict dueto multiple, parallel ground connections (including the all-important grounds through the mains power cords). Whilethis paragraph serves as an overview of system-levelgrounding issues, the scope of this application note isdirected more towards individual circuits and boards thantowards a large system.

Board “Local” Grounds

Current Return Paths vs. Ground Planes

The common-return currents or grounding of individualcomponents on a circuit board is the ground that is ofmost interest to circuit designers. It is well known that acircuit board run carrying a signal generates a returncurrent back to the source. This return current follows thepath of least resistance and would prefer to flow in a rundirectly underneath the signal run, for circuits on a printedcircuit board. For this reason, single-layer layouts are

almost always nearly impossible to make clean. Two-layer boards require great care in laying out return pathsas well as signal paths in order to make them clean. Sincewider runs usually have lower impedance, they may bemore appropriate for a return path (the inductance ofnarrow runs can impede current flow, especially at higherfrequencies). The optimum return path for a signal is aplane, where an entire layer is “poured” with copper andserves as a very low-impedance return path. There aremany advantages to using a ground plane instead ofground return traces, including better performance due tothe lower ground impedance and the better EMI/RFIperformance of such boards. But there are some ruleswhich should be followed in order to extract the bestperformance from such boards.

Layout and Ground Plane Rules

A primary layout consideration is that the analog anddigital ground planes should not overlap. To that end,they should both be on the same PC board layer, sepa-rated by at least 0.1 inch. The analog circuitry and thedigital circuitry should likewise be separated, over theirrespective ground planes. Placing analog and digitalcircuitry at opposite ends of a circuit board is an excellentway to begin. Do not surround the analog region withdigital circuits or surround the digital region with analogcircuits; it will be impossible to route clean runs throughthe digital area to the analog circuitry or to keep theanalog and digital runs separated. Power supply circuitsshould be in a centralized area near the edge of the boardso they can feed the digital and analog sections equallywell. A location near the edge of the board allows anyreturn currents generated in this area to return directly tothe main supply without passing through the rest of theboard. The analog and digital ground planes should beconnected together at only one point; either at the local

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on-board power supply circuits or, preferably, where theyleave the board to return to the main power supply. SomeA/D converter manufacturers prefer that the analog anddigital grounds be connected together at the ADCs. Inthis case, make jumpers available to try both choices todetermine which has better overall performance. If thereis more than one A/D converter on the board, makejumpers available at each A/D, as well as at the pointwhere the grounds leave the board, to allow for testing todetermine which connection gives the best results.

Keep Analog and Digital Areas Completely Separateand Non-Overlapping

When placing and routing the analog and digital circuitryover their respective ground planes, there should be nooverlap between any of the analog areas (ground orpower planes or circuitry) and any of the digital areas tominimize induced noise. Do not cross signal runs be-tween the planes unless absolutely necessary, for thesame reason. Return currents will not be able to jump thegap between the planes and will have to travel longdistances to be reunited with the signal currents, usuallypicking up unwanted noise along the way. The bestdesigns have analog power planes and an analog groundplane that exactly overlap, and digital power planes anda digital ground plane that exactly overlap, with the bestperformance usually being obtained when the groundplane is immediately underneath the power supply plane.The large overlap area of these power and groundplanes, combined with their close spacing, makes adistributed capacitance, which will be more effective atsuppressing high frequency noise than individual, lumpedcapacitors. This helps to keep the analog power planesand ground plane quiet.

Ground Pins on Connectors

In order to maintain a low-impedance ground connectionback to the system power supply, it is usually necessaryto use more than one connector pin for ground. In fact,one of the places where many of the board’s runs haveto be run in parallel is at the connectors, and additionalgrounds will provide additional shielding as well as givinga lower-impedance supply ground connection. Therehave been recommendations that 25%-40% of aconnector’s pins be dedicated to ground, with the groundpins being spread out among the connector pins. De-pending on the metal-plating of the connector pins andthe insertion force of the connector, a few pins may beadequate when the board is new but may corrode overtime, increasing the ground resistance and thereby wors-ening the performance of the board. Having at least 25%of the pins dedicated to ground is a reasonable recom-mendation.

Power Planes and Power Distribution

Which Supply to Use and Supply Decoupling

Power leads coming onto the circuit board should bedecoupled to ground at the point where they enter theboard. That way, all return currents from the decouplingcomponents return directly to the power supply withoutpassing through the ground planes of the board. Whileinductive decoupling components (lossy ferrites or in-ductors with parallel damping resistors) or resistivedecoupling components can be effective, the best de-signs route ±18V to ±24V to each board and use smallregulators, along with decoupling, to derive ±12V to ±15Vfor the board or individual devices. The same schemeshould be used for best performance from the single-supply ispPAC devices: route +8V to +15V to the individualboards, with separate +5V regulators and decoupling oneach board. One of the advantages of using ispPACdevices in designs is the fact that they only require asingle +5V supply, without the need to decouple positiveand negative supplies. A/D converters and D/A convert-ers, in particular, need regulators and decoupling close tothem to reduce the possibility of noise coupling from therest of the circuitry, if maximum performance is desired.Most A/D converters also have a low-current digitalsection that needs to be connected to the quiet analogsupply and ground, usually through some decoupling.Having pins marked “DGND” on an A/D converter usuallymeans that they are the IC’s digital ground, not that theyshould be connected to the system’s digital ground. MostA/Ds also specify that even their high-current digitalsections should be connected to an analog supply andground, using higher-power decoupling, to obtain bestperformance. In general, noisy digital supplies and groundneed to be kept away from high-performance A/D con-verters, except in the area where the digital outputs aredeveloped. In order to have analog power and groundson their supplies but digital ground plane underneaththeir digital outputs, most A/D converters should straddlethe split between the grounds in some fashion (see oneexample in Figure 7). Usually the manufacturer of theA/D converter will offer guidance in device layout torealize maximum performance from their part.

IC Decoupling

All analog circuitry needs decoupling on its power leadsto shunt both high-frequency and low-frequency noise toground. It is generally recommended that designers useeither a 0.1 µF or 0.01 µF capacitor to decouple the powerpins of each analog IC to ground. At various distances,place larger value capacitors, usually 10 µF to 47 µF, inparallel with 0.1 µF or 0.01 µF units. In particular, highperformance ICs need to have each supply decoupled to

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0.1µF

Feedthroughvia

Not good0.1µF

viaNot good

Magnifiedview

0.1µF

0.1µF

Feedthrough viasto ground

Power pins atIC’s end

Figure 3. Bypassing and Decoupling of IC Power Pins

ground. The smaller value capacitor should be placed asclose to the IC as possible, on the same layer as the IC(to avoid the inductance of feed-through vias). The leadson these capacitors must be kept very short. The besttechnique is to have the power feed from the power planethrough a via to the capacitor and IC pins, with thecapacitor between the via and the IC. The ground con-nection is particularly important, and should be madewith three to four vias connecting to the capacitor andthus to the IC pins. The inductances of these vias are theneffectively in parallel. See Figure 3 for examples of thistechnique. Surface-mount capacitors are best becausetheir connection pads have almost no lead inductance. Inaddition, surface-mount electrolytic capacitors can beused for the 10 µF to 47 µF units. Both aluminum andtantalum capacitors are available in these values, withtantalum having the lower ESR but also being moreprone to power supply transients or reversal. OS-CONdielectric capacitors have the lowest ESRs but are alsomore expensive than aluminum or tantalum.

Assigning PCB Layers

A typical four-layer board should be laid out with thesignal runs on the outer layers and the power and groundplanes on the inner layers. Many PC boards are thinnerbetween layers 2 and 3, so that power and ground planeson these layers will have higher distributed capacitance(C = εA/d). Placing the signal runs on the outer layers

makes the board easier to work on during prototyping.Having the planes underneath the signal layers alsohelps to provide a lower-impedance surface region andprovides additional shielding between the signal layers.Printed circuit boards with more layers should still keepthe power and ground planes in the center of the board,adjacent to each other.

Analog Runs and Digital Runs

It is almost always necessary to keep digital runs awayfrom analog runs. The fast rise times of digital signalscause them to more easily couple into adjacent runs.With 3.3V or 5V logic, a 0.2V spike from an adjacentdigital signal won’t cause a problem, but that same 0.2Vspike will wreak havoc in an analog circuit. The longer thedistance that two runs are run in parallel, or the closerthey are to each other, the more coupling will occur. Suchruns can even couple through adjacent layers of a circuitboard. It is best to try to keep runs on adjacent layers atroughly right angles to each other. This technique usuallyfacilitates easier layout and reduces crosstalk. Be awarethat sometimes radiation from adjacent circuit boardscan couple into some analog circuits and may requireshielding or more careful layout. It has been shown thatusing copper fill between areas of signal runs reducescrosstalk and radiation if the copper fill is grounded(never leave it ungrounded). Also note that some digitalruns (especially clocks) can couple into the VREF pins of

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Single-EndedInputs

–

+

RF

RISeparated GNDs

cause noiseinjection

Standardop amp

VSIGNAL

Quasi-DifferentialInputs

Very smallground resistance

Differentialinstrumentation

amplifier (IA)such as ispPAC10

VSIGNAL–

+

Full DifferentialInputs

IA such asispPAC10

VSIGNAL–

+

Figure 4. Improvement in Noise Pickup with Differential Connections

some A/D converters, causing “strange lumps” in thespectrum of the noise floor of the A/D. Keep all connec-tions to VREF pins very short and isolated from digitalruns. In some designs, it may be necessary to run parallelsets of runs for long distances. Be sure to design theconfiguration of these conductors carefully to reduce theeffects of crosstalk between the conductors. In somecases, it may be necessary to intersperse some groundruns between other runs to act as shielding. Also remem-ber to terminate and, in some cases, back-terminatedigital runs to control overshoot and undershoot if theruns have significant length (more than a few centime-ters).

Differential Circuitry

Because ispPAC technology utilizes differential tech-niques, it is worth explaining some of the advantages andkey layout aspects of differential circuitry and comparingthem to similar single-ended op amp circuitry. Differentialcircuitry is superior to single-ended circuitry for a numberof reasons. The common-mode rejection of differentialinputs lets balanced circuitry reject common-mode inter-ference, including ground noise, that would be amplifiedby single-ended circuits. Also, a differential circuit’s bal-anced properties usually reduce non-linearities andimprove distortion. In addition, some ICs with differentialoutputs (such as today’s single-supply DACs) have in-herent common-mode output noise that is cancelled if theDAC is followed by a differential-input amplifier or filter.Because a differential signal’s two conductors carry abalanced signal, reduced EMI generation and reducedsusceptibility to magnetic pickup (due to reduced looparea) are additional benefits of differential circuitry. Even

“quasi-differential” circuitry, with its ground taken adja-cent to a single-ended source but shipped to a differentialload as if it were the second half of a differential signal, issuperior to single-ended circuitry. This is because thesmall common-mode interfering currents between thesource and load are still reduced by the differential input.See Figure 4 for examples of these concepts. Note thatthe single-ended connection in Figure 4 is shown as astandard op amp, although it could also apply to single-ended connections into ispPAC gain blocks if theground-referenced signals were instead referred to 2.5volts. The details of the 2.5 volt input reference have beenleft out of Figures 4, 5 and 6 to improve the clarity of thosedrawings.

Figure 5, with more detail, shows how ground noise andother single-ended noise sources are amplified in single-ended circuitry but are rejected as common-mode signalsin differential circuitry. In the figure, VNOISE represents“ground loop” noise injected into the input signal path dueto IGND flowing through the distributed resistance RGND.There are at least three flaws in the single-ended circuit:(1) both VSIGNAL and VNOISE are amplified by the circuit.(2) The gain is actually 1 + RF/(RI + RGND) in the single-ended circuit, causing a slight error. (3) The voltageacross RGND due to IGND (“ground-loop” current) getsadded in series with the input (which is why it getsamplified, causing additional noise at the output). Bycontrast, in the differential-input amplifier circuit,(1) VNOISE is a common-mode signal, which is reducedby the common-mode rejection of the differential input.(2) In the ispPAC devices, the gain is set by resistorsinternal to the amplifier and is unaffected by RGND. (3)The voltage across RGND is now also a common-mode

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Figure 5. Common-Mode Rejection and Ground Resistance

–

+

RF

RI

RGND

IGND

VSIGNAL

VNOISE

Single-Ended Circuit

–

+

RGND

IGND

VSIGNAL

VNOISE

Differential Instrumentation Input

IA, such as ispPAC10

Single-Ended Circuit Differential Instrumentation Input

IA, such as ispPAC10

–

+–

+

smallerloop

RF

RI

RL

RL

Standardop amp

VSIGNALVREF

Loop 1

Loop 3

Loop 2

Figure 6. Magnetically-Coupled Interference

signal that is reduced by the differential input. Theseadvantages are some of the main reasons for the in-creased use of differential circuitry, especially inmixed-signal systems. The ispPAC devices take advan-tage of these principles by using a fully-differentialarchitecture with instrumentation amplifier inputs.

Magnetically-Induced Interference

Differential devices also afford some protection againstmagnetically-induced interference, which can come fromnearby power transformers or coils in switching powersupply circuits or even from magnetically-deflected CRTs.Frequently, the most confusing task in magnetically-coupled interference is identifying the circuit loops whichare picking it up. These loops, while usually uninten-tional, are due to the physical layout of the circuit’s

components. A typical op amp circuit can have threeinductive loops if it is not carefully laid out (Figure 6). Themost significant of the loops is the one that involves theinput circuitry (Loop 1 in Figure 6), because the noise itpicks up is amplified by the circuitry. Noise picked up byLoop 2 and Loop 3 only appears in the output with a gainof one. Since magnetic pickup varies with the loop areaand the number of flux lines crossing the loop, the mostuseful techniques for reducing magnetic interference(short of breaking the loop) are minimizing the loop areaor orienting the loop parallel to the magnetic field. In thedifferential circuit with the ispPAC gain cells, having thefeedback and input resistors on-chip reduces the areasof Loop 2 and Loop 3 to near zero. As mentioned above,differential input devices usually have reduced input looparea, since differential components are usually veryclose to each other. Reducing the loop area of the rest of

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+8 to +12V for Analog(regulate to +5V)

G G +5VDigital

Power Connector

Decouplingcomponents

+5V AnalogRegulator

Bypass anddecoupling

caps

Analog signals in,shields = GND

Bypass anddecoupling

caps

Decouplingcomponents

Gap in GNDs andpower planes

ispDOWNLOAD cableconnector

Powercomponents

(separated GND,except at

“reference” point)

Digital signals,ribbon cable,many GNDs

Common GNDat “reference” GND

of power supply

DigitalCircuitry

Over Digital GNDand

Digital Power

AnalogCircuitry

Over Analog GNDand

Analog Power

Analog/digitalconverter

Analoginputs

Digitaloutputs

ispPAC

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Figure 7. A Layout Using Many of the Points Given in this Application Note

the input circuitry is still an important tool in reducingmagnetically-induced interference. If this does not re-duce the magnetic interference enough, and if the circuitrycannot have its physical orientation changed, it maybecome necessary to use magnetic shielding (steel ormu-metal) between the magnetic source and the board.

Summary

In this application note, techniques to improve circuitboard layout have been discussed, including groundingand ground planes, power planes and decoupling, andcircuit layout techniques. Figure 7 summarizes many ofthe points developed here. The differential nature andinstrumentation-amplifier inputs of the ispPAC deviceshave been shown to make a significant improvement insolving grounding and layout problems. The techniquesmentioned in this application note should prove benefi-cial in laying out a board without grounding orpower-related problems, or in solving such problems infewer board turns.

Technical Support Assistance

Toll Free Hotline: 1-800-LATTICE (Domestic)

International: 1-408-826-6002

E-mail: [email protected]

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Electronique - Lattice (An6012)Analog Layout and Grounding Techniques

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