EEE 348E INTRODUCTION TO IC DESIGN

P.M Dr Othman Sidek (Director of CEDEC)Mr. Arjuna Marzuki (room 2.15, ext: 6021)email: A_Marzuki@ieee.org

Instructor/TutorRuhaifiemail: airr_p@yahoo.com

Learning OutcomesStudents will be able to design and simulate logic circuits at transistor level using schematic entry as well as netlists format.

Students will be able to produce the layout design of a circuit based on the design rules specified.

Students will be able to analyze CMOS transistor characteristics.

Students will be able present their mini project individually in a viva session.

Laboratory (CEDEC Lab)Lab 1, Week3 : Netlist Lab 2, Week4 : Schematic designLab 3, Week5 : Layout designLab 4, Week6 : DRC and LVSWeek7 13 : Mini ProjectWeek14 : Viva & Presentation

CAD ToolsCadence (Linux OS):Text Editor - NetlistSchematic Composer - SchematicVirtuoso - LayoutSpectre- SimulationDIVA DRC- DRCDIVA LVS- LVS

Reading ListsKang, Sung-Mo and Leblebici, Yusuf, CMOS Digital Integrated Circuits- Analysis and Design, McGraw-Hill, 2005 (Text book).

Hodges, David A. et al, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, Mc-Graw-Hill, 2004.

Neil H.E. Weste and Daid Harris, CMOS VLSI Design- A Circuits and Systems Perspective, Prentice Hall, 2005.

Uyemura, J. P., Introduction to VLSI Circuits and Systems, John Wiley, 2002.

Rabaey, J. M. et al, Digital Integrated Circuits A Design Perspective, 2nd Edition, Prentice Hall, 2002.

EvaluationCourse Work 40%Assignments (3): 10%Mini project & Lab : 35%

Final Exam 60%

EXPECTATIONSAttend classes and labs.Find out what youve missed if youre absent.Come earlier than the lecturer/tutors..Ask lecturer/tutor whenever have any problems related with the subject.

WHAT IS IC?ICs on PCBIC PackageInside ICWafer

==IC LayoutIC Schematic

Why VLSI?Integration improves the designLower parasitics = higher speedLower power consumptionPhysically smallerIntegration reduces manufacturing cost - (almost) no manual assembly