EE 534 fall 2003 University of South Alabama

EE534VLSI Design System

Fall 2003

Lecture 21:Chapter 9

Sequential Logic Circuits

EE 534 fall 2003 University of South Alabama

Review: Sequential Definitions

Static versus dynamic storage static uses a bistable element with feedback (regeneration) and

thus preserves its state as long as the power is on static is preferred when updates are infrequent (clock gating) dynamic stores state on parasitic capacitors so only holds the

state for a period of time (milliseconds) and requires periodic refresh

dynamic is usually simpler (fewer transistors), higher speed, lower power

Latch versus flipflop latches are level sensitive with two modes: transparent - inputs

are passed to Q and hold - output stable fliplflops are edge sensitive that only sample the inputs on a clock

transition

EE 534 fall 2003 University of South Alabama

Review: System Timing Constraints

CombinationalLogic

clock

Outputs

Sta

teR

egis

ters

NextState

CurrentState

Inputs

T tc-q + tplogic + tsutcdreg + tcdlogic thold

T (clock period)

EE 534 fall 2003 University of South Alabama

NMOS Dynamic Shift Registers

A shift register can be constructed by the combination of transmission gates and inverters.

If VI=VDD and 1=VDD, then a logic 1=VDD-VTN would exist at VO1.

The CL charges through MN1.

As VO1 goes high, VO2 goes low.

If 2 is high low will transmitted through MN2 and VO4 would be at logic 1. Thus logic 1 shifted from input to output.

In shift register the input signal is transmitted, or shifted, from the input to the output during one clock cycle.

EE 534 fall 2003 University of South Alabama

NMOS Dynamic Shift Registers at various times

Suppose VDD=5V and VTN=1V.

At t=t1 , V1=1=5V, vO2 goes low

At this time MN2 is still in cutoff (2=0)

even though input of MN2 has

been changed. This implies that

vO3 and vO4 depend on the

previous history.

Similarly at t=t3, 2 is high, and logic 0 at vO2 is transmitted to vO3, which force vO4 to 5V. Thus the input information is transmitted to output during one clock cycle.

Transparent mode Hold mode

EE 534 fall 2003 University of South Alabama

Dynamic Shift Registers at Various Times (cont.)

Consider when t=t4, vI=0, and 1=5V, so VO1=0 and VO2=5V.Vo3 and Vo4 depend on previous history

At t=t5, 2=5V, vO3 charges to VDD-VTN=4V and VO4 goes low.

Thus logic 0 is shifted (transmitted) from input to output.

Also note that vO3 and vO4 are depend on previous history of their inputs instead of current inputs (they are having memory).

EE 534 fall 2003 University of South Alabama

NMOS shift register is also dynamic (why?)

The output charged capacitor does not remain constant with time because it is discharge through the transmission gate transistor.

In order to prevent logic errors, the clock signal period T must be small compared to effective RC discharge time constant.

For example at t = t2, VO1=4V, 1=0and MN1 is cutoff.VO1 will start to to decay and VO2 will begin to increase.

EE 534 fall 2003 University of South Alabama

CMOS Dynamic Shift Registers

The operation of the CMOS shift register is similar to the NMOS register except for the voltage levels.

For example, when vI=1=VDD. Then vO1=VDD and vO2=0. when 2 goes high, then vo3 switch to zero, vo4=vDD.

Thus input signal is shifted to the output during one clock cycle.

EE 534 fall 2003 University of South Alabama

Dynamic transmission gate edge-triggered registers (cont.)

T1 T2I1 I2 QQM

D

C1 C2

!clk

clk

clk

!clk

!clk

clk

master transparentslave hold

master holdslave transparent

master slave

tsu =thold =tc-q =

tpd_tx (delay of the TG )zero2 tpd_inv + tpd_tx

The hold time is approximately zero, since the transmission gate is turned off at clock edge.

Propagation delay

EE 534 fall 2003 University of South Alabama

Dynamic transmission gate edge-triggered registers race Conditions

T1 T2I1 I2 QQM

D

C1 C2

!clk

clk

clk

!clk

!clk

clk0-0 overlap race condition toverlap0-0 < tT1 +tI1 + tT2

1-1 overlap race condition toverlap1-1 < thold

(1,1) overlap(0,0) overlap

data must be stable during the high-high overlap period

0-0 race fixed by making sure there is enough delay between D and C2 so that new data sampled by the master does not propagate to the slave

EE 534 fall 2003 University of South Alabama

C2MOS (Clocked CMOS) ET register

clk

!clk

!clk

clk

QM

C1 C2

QD

M1

M3

M4

M2 M6

M8

M7

M5

Master Slave

!clk

clk

master transparentslave hold

master holdslave transparent

on

on

off

offon

onoff

off

A clock-skew insensitive register

EE 534 fall 2003 University of South Alabama

C2MOS register 0-0 Overlap Case

0 0QM

C1 C2

QD

M1

M4

M2 M6

M8

M5

!clk

clk

!clk

clk

Clock-skew insensitive as long as the rise and fall times of the clock edges are sufficiently small

Does any new data sampled during the overlap window propagate to Q (race)?

New data is sampled on QM, but cannot propagate to Q since M7 is off (slave is in hold). Any new data sampled on the falling clock edge is not seen at QFor the clocking on the right – at the end of the overlap period clk = 1 and both M3 and M4 turn off, putting the master in the hold mode (affects setup time as well) Means that the register is slower (slower tc-q time)

For clocking on left – Fat the end of the overlap period !clk = 1 and both M7 and M8 turn off, putting the slave stage in the hold mode

EE 534 fall 2003 University of South Alabama

C2MOS FF 1-1 Overlap Case

1 1

QM

C1 C2

QD

M1

M2 M6

M5

!clk

clk

M3 M7

!clk

clk

1-1 overlap constraint toverlap1-1 < thold

Does any new data sampled during the overlap window (right after the clock goes high) propagate to Q (race)?

New data is sampled on QM, but cannot propagate to Q since M8 is off (slave is in hold). Any new data sampled on the falling clock edge is not seen at QA bit more problematic than 0-0 overlap. Must enforce a hold time on D, so that D changing that makes it to QM is not copied to Q when overlap time is over (and !clk goes to zero turning on M8) - first clocking condition. By imposing a hold time on D - that D must be stable during clock overlap - overcome this problem as wellHowever, if the rise/fall times of the clock are sufficiently slow, have possible race. Works correctly as long as the clock rise/fall times is smaller than approximately five times the propagation delay of the flipflop.

EE 534 fall 2003 University of South Alabama

NORA CMOS Logic (NP domino logic)

EE 534 fall 2003 University of South Alabama

Pipeline system

EE 534 fall 2003 University of South Alabama

True Single phase Clock (TSPC) dynamic CMOS

EE 534 fall 2003 University of South Alabama

Next Lecture and Reminders

Next lecture Semiconductors memories Chapter 6, 7 and 9 home work will be posted soon!