Introduction to CMOS VLSI Design Sequential Circuits.
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Introduction to CMOS VLSI Design Sequential Circuits
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Transcript of Introduction to CMOS VLSI Design Sequential Circuits.
Introduction toCMOS VLSI
Design
Sequential Circuits
Sequential Logic Slide 2CMOS VLSI Design
Outline Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking
Sequential Logic Slide 3CMOS VLSI Design
Sequencing Combinational logic
– output depends on current inputs Sequential logic
– output depends on current and previous inputs– Requires separating previous, current, future– Called state or tokens– Ex: FSM, pipeline
CL
clk
in out
clk clk clk
CL CL
PipelineFinite State Machine
Sequential Logic Slide 4CMOS VLSI Design
Sequencing Cont. If tokens moved through pipeline at constant speed,
no sequencing elements would be necessary Ex: fiber-optic cable
– Light pulses (tokens) are sent down cable– Next pulse sent before first reaches end of cable– No need for hardware to separate pulses– But dispersion sets min time between pulses
This is called wave pipelining in circuits In most circuits, dispersion is high
– Delay fast tokens so they don’t catch slow ones.
Sequential Logic Slide 5CMOS VLSI Design
Sequencing Overhead Use flip-flops to delay fast tokens so they move
through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay
– Called sequencing overhead Some people call this clocking overhead
– But it applies to asynchronous circuits too– Inevitable side effect of maintaining sequence
Sequential Logic Slide 6CMOS VLSI Design
Sequencing Elements Latch: Level sensitive
– a.k.a. transparent latch, D latch Flip-flop: edge triggered
– A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams
– Transparent– Opaque– Edge-trigger
D
Flo
p
Latc
h
Q
clk clk
D Q
clk
D
Q (latch)
Q (flop)
Sequential Logic Slide 7CMOS VLSI Design
Sequencing Elements Latch: Level sensitive
– a.k.a. transparent latch, D latch Flip-flop: edge triggered
– A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams
– Transparent– Opaque– Edge-trigger
D
Flo
p
Latc
h
Q
clk clk
D Q
clk
D
Q (latch)
Q (flop)
Sequential Logic Slide 8CMOS VLSI Design
Latch Design Pass Transistor Latch Pros
+ +
Cons– – – – – –
D Q
Sequential Logic Slide 9CMOS VLSI Design
Latch Design Pass Transistor Latch Pros
+ Tiny+ Low clock load
Cons– Vt drop– nonrestoring– backdriving– output noise sensitivity– dynamic– diffusion input
D Q
Used in 1970’s
Sequential Logic Slide 10CMOS VLSI Design
Latch Design Transmission gate
+
- D Q
Sequential Logic Slide 11CMOS VLSI Design
Latch Design Transmission gate
+ No Vt drop
- Requires inverted clock D Q
Sequential Logic Slide 12CMOS VLSI Design
Latch Design Inverting buffer
+
+
+ Fixes either• •
–
D
XQ
D Q
Sequential Logic Slide 13CMOS VLSI Design
Latch Design Inverting buffer
+ Restoring
+ No backdriving
+ Fixes either• Output noise sensitivity• Or diffusion input
– Inverted output
D
XQ
D Q
Sequential Logic Slide 14CMOS VLSI Design
Latch Design Tristate feedback
+ –
QDX
Sequential Logic Slide 15CMOS VLSI Design
Latch Design Tristate feedback
+ Static– Backdriving risk
Static latches are now essential
QDX
Sequential Logic Slide 16CMOS VLSI Design
Latch Design Buffered input
+
+
QDX
Sequential Logic Slide 17CMOS VLSI Design
Latch Design Buffered input
+ Fixes diffusion input
+ Noninverting
QDX
Sequential Logic Slide 18CMOS VLSI Design
Latch Design Buffered output
+
Q
D X
Sequential Logic Slide 19CMOS VLSI Design
Latch Design Buffered output
+ No backdriving
Widely used in standard cells
+ Very robust (most important)- Rather large- Rather slow (1.5 – 2 FO4 delays)- High clock loading
Q
D X
Sequential Logic Slide 20CMOS VLSI Design
Latch Design Datapath latch
+
-
Q
D X
Sequential Logic Slide 21CMOS VLSI Design
Latch Design Datapath latch
+ Smaller, faster
- unbuffered input
Q
D X
Sequential Logic Slide 22CMOS VLSI Design
Flip-Flop Design Flip-flop is built as pair of back-to-back latches
D Q
X
D
X
Q
Q
Sequential Logic Slide 23CMOS VLSI Design
Enable Enable: ignore clock when en = 0
– Mux: increase latch D-Q delay– Clock Gating: increase en setup time, skew
D Q
Latc
h
D Q
en
en
Latc
hDQ
0
1
en
Latc
h
D Q
en
DQ
0
1
enD Q
en
Flo
p
Flo
p
Flo
p
Symbol Multiplexer Design Clock Gating Design
Sequential Logic Slide 24CMOS VLSI Design
Reset Force output low when reset asserted Synchronous vs. asynchronous
D
Q
Q
reset
D
Q
D
reset
Q
Dreset
reset
reset
Synchronous R
esetA
synchronous Reset
Sym
bol Flo
p
D Q
Latc
h
D Q
reset reset
Q
reset
Sequential Logic Slide 25CMOS VLSI Design
Set / Reset Set forces output high when enabled
Flip-flop with asynchronous set and reset
D
Q
reset
setreset
set
Sequential Logic Slide 26CMOS VLSI Design
Sequencing Methods Flip-flops 2-Phase Latches Pulsed Latches
Flip-F
lopsF
lop
Latc
h
Flo
p
clk
1
2
p
clk clk
Latc
h
Latc
h
p p
1 12
2-Phase T
ransparent LatchesP
ulsed Latches
Combinational Logic
CombinationalLogic
CombinationalLogic
Combinational Logic
Latc
h
Latc
h
Tc
Tc/2
tnonoverlap tnonoverlap
tpw
Half-Cycle 1 Half-Cycle 1
Sequential Logic Slide 27CMOS VLSI Design
Timing Diagrams
Flo
p
A
Y
tpdCombinational
LogicA Y
D Q
clk clk
D
Q
Latc
h
D Q
clkclk
D
Q
tcd
tsetup thold
tccq
tpcq
tccq
tsetup tholdtpcq
tpdqtcdq
tpdLogic Prop. Delay
tcdLogic Cont. Delay
tpcqLatch/Flop Clk-Q Prop Delay
tccqLatch/Flop Clk-Q Cont. Delay
tpdqLatch D-Q Prop Delay
tpcqLatch D-Q Cont. Delay
tsetupLatch/Flop Setup Time
tholdLatch/Flop Hold Time
Contamination and Propagation Delays
Sequential Logic Slide 28CMOS VLSI Design
Max-Delay: Flip-Flops
F1
F2
clk
clk clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tpd
tsetuptpcq
sequencing overhead
pd ct T
Sequential Logic Slide 29CMOS VLSI Design
Max-Delay: Flip-Flops
F1
F2
clk
clk clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tpd
tsetuptpcq
setup
sequencing overhead
pd c pcqt T t t
Sequential Logic Slide 30CMOS VLSI Design
Max Delay: 2-Phase Latches
Tc
Q1
L1
1
2
L2 L3
1 12
CombinationalLogic 1
CombinationalLogic 2
Q2 Q3D1 D2 D3
Q1
D2
Q2
D3
D1
tpd1
tpdq1
tpd2
tpdq2
1 2
sequencing overhead
pd pd pd ct t t T
Sequential Logic Slide 31CMOS VLSI Design
Max Delay: 2-Phase Latches
Tc
Q1
L1
1
2
L2 L3
1 12
CombinationalLogic 1
CombinationalLogic 2
Q2 Q3D1 D2 D3
Q1
D2
Q2
D3
D1
tpd1
tpdq1
tpd2
tpdq2
1 2
sequencing overhead
2pd pd pd c pdqt t t T t
Sequential Logic Slide 32CMOS VLSI Design
Max Delay: Pulsed Latches
Tc
Q1 Q2D1 D2
Q1
D2
D1
p
p p
Combinational LogicL1 L2
tpw
(a) tpw > tsetup
Q1
D2
(b) tpw < tsetup
Tc
tpd
tpdq
tpcq
tpd tsetup
sequencing overhead
max pd ct T
Sequential Logic Slide 33CMOS VLSI Design
Max Delay: Pulsed Latches
Tc
Q1 Q2D1 D2
Q1
D2
D1
p
p p
Combinational LogicL1 L2
tpw
(a) tpw > tsetup
Q1
D2
(b) tpw < tsetup
Tc
tpd
tpdq
tpcq
tpd tsetup
setup
sequencing overhead
max ,pd c pdq pcq pwt T t t t t
Sequential Logic Slide 34CMOS VLSI Design
Min-Delay: Flip-Flops
cdt CL
clk
Q1
D2
F1
clk
Q1
F2
clk
D2
tcd
thold
tccq
Sequential Logic Slide 35CMOS VLSI Design
Min-Delay: Flip-Flops
holdcd ccqt t t CL
clk
Q1
D2
F1
clk
Q1
F2
clk
D2
tcd
thold
tccq
Sequential Logic Slide 36CMOS VLSI Design
Min-Delay: 2-Phase Latches
1, 2 cd cdt t CL
Q1
D2
D2
Q1
1
L1
2
L2
1
2
tnonoverlap
tcd
thold
tccq
Hold time reduced by nonoverlap
Sequential Logic Slide 37CMOS VLSI Design
Min-Delay: 2-Phase Latches
1, 2 hold nonoverlapcd cd ccqt t t t t CL
Q1
D2
D2
Q1
1
L1
2
L2
1
2
tnonoverlap
tcd
thold
tccq
Hold time reduced by nonoverlap
Sequential Logic Slide 38CMOS VLSI Design
Min-Delay: Pulsed Latches
cdt CL
Q1
D2
Q1
D2
p tpw
p
L1
p
L2tcd
thold
tccq
Hold time increased by pulse width
Sequential Logic Slide 39CMOS VLSI Design
Min-Delay: Pulsed Latches
holdcd ccq pwt t t t CL
Q1
D2
Q1
D2
p tpw
p
L1
p
L2tcd
thold
tccq
Hold time increased by pulse width
Sequential Logic Slide 40CMOS VLSI Design
Time Borrowing In a flop-based system:
– Data launches on one rising edge– Must setup before next rising edge– If it arrives late, system fails– If it arrives early, time is wasted– Flops have hard edges
In a latch-based system– Data can pass through latch while transparent– Long cycle of logic can borrow time into next– As long as each loop completes in one cycle
Sequential Logic Slide 41CMOS VLSI Design
Time Borrowing Example
Latc
h
Latc
h
Latc
h
Combinational LogicCombinational
Logic
Borrowing time acrosshalf-cycle boundary
Borrowing time acrosspipeline stage boundary
(a)
(b)
Latc
h
Latc
hCombinational Logic Combinational
Logic
Loops may borrow time internally but must complete within the cycle
1
2
1 1
1
2
2
Sequential Logic Slide 42CMOS VLSI Design
How Much Borrowing?
Q1
L1
1
2
L2
1 2
Combinational Logic 1Q2D1 D2
D2
Tc
Tc/2 Nominal Half-Cycle 1 Delay
tborrow
tnonoverlap
tsetup
borrow setup nonoverlap2cTt t t
2-Phase Latches
borrow setuppwt t t
Pulsed Latches
Sequential Logic Slide 43CMOS VLSI Design
Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time
– Decreases maximum propagation delay– Increases minimum contamination delay– Decreases time borrowing
Sequential Logic Slide 44CMOS VLSI Design
Skew: Flip-Flops
F1
F2
clk
clk clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tskew
CL
Q1
D2
F1
clk
Q1
F2
clk
D2
clk
tskew
tsetup
tpcq
tpdq
tcd
thold
tccq
setup skew
sequencing overhead
hold skew
pd c pcq
cd ccq
t T t t t
t t t t
Sequential Logic Slide 45CMOS VLSI Design
Skew: Latches
Q1
L1
1
2
L2 L3
1 12
CombinationalLogic 1
CombinationalLogic 2
Q2 Q3D1 D2 D3
sequencing overhead
1 2 hold nonoverlap skew
borrow setup nonoverlap skew
2
,
2
pd c pdq
cd cd ccq
c
t T t
t t t t t t
Tt t t t
2-Phase Latches
setup skew
sequencing overhead
hold skew
borrow setup skew
max ,pd c pdq pcq pw
cd pw ccq
pw
t T t t t t t
t t t t t
t t t t
Pulsed Latches
Sequential Logic Slide 46CMOS VLSI Design
Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed Working chips are most important
– Analyzing clock skew difficult An easy way to guarantee hold times is to use 2-
phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2)
Sequential Logic Slide 47CMOS VLSI Design
Safe Flip-Flop Flip-flop with nonoverlapping clocks
– Very slow – nonoverlap adds to setup time– But no hold times
In industry, use a better timing analyzer– Add buffers to slow signals if hold time is at risk
D
X
Q
Q
Sequential Logic Slide 48CMOS VLSI Design
Summary Flip-Flops:
– Very easy to use, supported by all tools 2-Phase Transparent Latches:
– Lots of skew tolerance and time borrowing Pulsed Latches:
– Fast, some skew tol & borrow, hold time risk
