EE353 L03 - PIC24 Family.ppt
Transcript of EE353 L03 - PIC24 Family.ppt
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
1/75
1
Introduction To PIC24Family
Sohaib Majzoub
Lecture Notes 3
EE 353Introduction to Microprocessor
Lecture notes by Dr. Bob Reese, ECE Department, Mississippi State UniversityModified with permission by Dr. Sohaib Majzoub, College of Engineering, King Saud University.
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
2/75
2
Microcontroller (C) vs. Microprocessor
(P) C intended as a singlechip solution, P requires
externalsupport chips(memory, interface)
C has on-chip non-volatile memoryfor programstorage, P does not.
C has moreinterfacefunctions on-chip(serial
interfaces, analog-to-digital conversion, timers, etc.)than P
C does nothave virtual memorysupport (i.e., couldnot run Linux), while P does.
General purpose Psare typically higherperformance(clock speed, data width, instruction set,cache) than Cs
Division between Ps and Cs becomingincreasingly blurred
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
3/75
3
Microchip PIC24 Family C
Features Comments
Instruction width 24 bits
On-chip program memory (non-
volatile, electrically erasable)
PIC24HJ32GP202 has 32Kbytes/11264
instructions, architecture supports
24Mbytes/4M instructions)On-chip Random Access Memory
(RAM) , volatile
PIC24HJ32GP202 has 2048 bytes,
architecture supports up 65536 bytes
Clock speed DC to 80 MHz
16-bit Architecture General purpose registers, 71 instructionsnot including addressing mode variants
On-chip modules Async serial IO, I2C, SPI, A/D, three 16-
bit timers, one 8-bit timer, comparator
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
4/75
4
PIC24 Core (Simplified Block Diagram)
17 x 17 Multipliernot shown
Program Counter
23address
Program Memory,non-volatile, up to4M words (4M x 24)
DOUT
24
ALU
DataMemInst. Reg
16
16
16
Data
16 address
16
16
16The inst ruct ion registercontains themachine code of the instruction currently
being executed.ALU (Arithmetic Logic Unit) is 16 bits wide,can accept as operands working registersor data memory.
16 x 16WorkingReg array
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
5/75
5
Memory Organization
Memory on the PIC24 C family is split into two types:Program Memoryand Data Memory.
PIC24 instructions are stored in program memory,which is non-volatile(contents are retained when poweris lost).
A PIC24 instruction is 24 bitswide (3 bytes).PIC24HJ32GP202 program memory supports 11264instructions; the PIC24 architecture can support up to
4Minstructions.PIC24 data is stored in data memoryand is amaximum size of 65536 x 8. Data memory is volatile(contents are lost when power is lost).
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
6/75
Program Memory
Locations 0x000000- 0x0001FF reserved, User program starts atlocation 0x000200.
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family.
Phantom byte: upper byte ofprogram memory that does notexist. Any read of the phantombyte return 0x00 and a write tothe phantom byte has no effect
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
7/75
7
Data Memory Organization
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family .
Data memory forPIC24HJ32GP202
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
8/75
8
Special Function Registers (SFRs)
Special Function Registers (SFR) are
addressed like data memory locations.
SFRs live in the address range 0x0000 to 0x07FEin data memory. (check datasheet).
They are of two types: Core RegistersandPeripheralSFRs.
Peripheral SFRs are tied to processor
subsystems/peripherals (like the serial interface,or the analog-to-digital converter).
Peripheral SFR are used as control registersand
data registersfor processor subsystems.
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
9/75
9
Special Function Registers (SFRs)
Core Registers are used for storage of temporary
data; they are not used by the processorsubsystems.
These are sometimes referred to as GPRs
(general purpose registers). Sometimes alsoreferred to as file registers.
We typically refer to SFRs by name (W0, T3CON,
STATUS, etc) instead of by address.
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
10/75
8-bit, 16-bit, 32-bit Data
10
We will deal with data that is 8 bits, 16 bits(2 bytes), and 32 bits(4bytes) in size. Initially we will use only 8 bit and 16 bit examples.
Size Unsigned Range
8-bits 0 to 28-1 (0 to 255, 0 to 0xFF)
16-bit 0 to 216
-1 (0 to 65536, 0 to 0xFFFF)32-bit 0 to 232-1 (0 to 4,294,967,295), 0 to
0xFFFFFFFF)
The lower 8bits of a 16-bit value or of a 32-bit value is known as the Least
Significant Byte(LSB).
The upper 8bits of a 16-bit value or of a 32-bit value is known as the MostSignificant Byte(MSB).
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
11/75
Storing Multi-byte Values in Memory
11
16-bit and 32-bit values are stored in memory from least significant byte tomost significant byte, in increasing memory locations (little endianorder).
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24Family.
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
12/75
Data Transfer Instruction
Copiesdata from Source (src) location to Destination (dst)Location:
(src) dst ()read as contents of
This operation uses two operands.
The method by which an operandADDRESSis specified iscalled the addressingmode.
There are many different addressing modesfor the PIC24.
We will use a very limited number of addressing modes in ourinitial examples.
12
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
13/75
Data Transfer Instruction Summary
Key:MOV{.B} #lit8/16, Wnd PIC24 assemblylit Wnd Data transfer
Yellow shows varyingforms of the sameinstruction
f: near memory (08095) fALL: all of memory (065534) 13
8- or 16-bit literal: #lit8 or #lit16
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
14/75
V 0.2 14
MOV{.B } Wso, Wdo InstructionCopy contents of Wso register to Wdo register. General form:
mov{.b} Wso, Wdo (Wso) Wdo
Wso is one of the 16 working registersW0 through W15 (sindicatesWso is an operand sourceregister for the operation).
Wdo is one of the 16 working registers W0 through W15(dindicatesWdo is an operand destinationregister for the operation).
mov W3, W5 (W3) W5 (word operation)mov.b W3, W5 (W3.LSB) W5.LSB (byte operation)
Contents of working register W3copied toworking register W5.
This can either be a wordor byteoperation. The term copyis used
here instead of moveto emphasize that Wso is left unaffectedby theoperation.
The addressing mode used for both the source and destination operands iscalled register direct. The movinstruction supports other addressing modeswhich are not shown.
14
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
15/75
MOV Wso, Wdo Instruction Execution
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family. 15
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
16/75
MOV Wso, Wdo Instruction Format
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family .
16
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
17/75
17
MOV Wns , fA ll Instruction
Copy contents of Wns register to data memory location f.General form:
MOV Wns, fAll (Wns) fAll
fis a memory locationin data memory, Wns is one of the 16 workingregisters W0 through W15 (sindicates Wns is an operand sourceregister for the operation)
MOV W3, 0x1000 (W3) 0x1000
Contents of register W3 copied to data memory location 0x1000.This instruction form onlysupports WORDoperations.
The source operand uses register directaddressing, while the destinationoperand uses file registeraddressing.
File registersis how Microchip refers to data memory.
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
18/75
18
MOV Wns , fAll Instruction Execution
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24Family.
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
19/75
19
MOV Wns , fAllInstruction Format
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family .
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
20/75
20
MOV fAll, Wnd Instruction
Copy contents of data memory location f to register Wnd. General form:
MOV fAll, Wnd (f) Wnd
fis a memory location in data memory, Wnd is one of the 16 workingregisters W0 through W15 (dindicates Wnd is an operand destinationregister for the operation).
MOV 0x1000, W3 (0x1000) W3
Contents of data memory location 0x1000 copied to W3.
() is read as Contents of.
This instruction form onlysupports a word operation.
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
21/75
21
MOV fA ll, Wnd Instruction Execution
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family .
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
22/75
A Note on Instruction Formats
The instruction formats (machine code) ofsome instructions will be presented forinformational purposes However, studying the machine code formatsof
the instructions is not a priority; understanding
instruction functionalitywill be emphasized. Allinstruction formatscan be found in the
dsPIC30F/dsPIC33F Programmers Referencemanual from Microchip
The PIC24 familyis a subset of thedsPIC30F/dsPIC33FF instruction setthe PIC24family does notimplement the DSPinstructions.
22
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
23/75
23
MOV{.B} WREG, f Instruction
Copy content of WREG (default working register) to data memorylocation f. General form:
MOV{.B} WREG, f (WREG) f
This instruction provides upward compatibilitywith earlierPIC C.WREG is register W0, and f is a location within the first 8192 bytes ofdata memory (neardata memory)
MOV WREG, 0x1000 (W0) 0x1000
Contentsof register W0 copied to data memory location0x1000.
Can be used for either WORD or BYTE operations:
MOV WREG, 0x1000 word operation
MOV.B WREG, 0x1001 lower 8-bits of W0 copied to 0x1001
Word copy must be to even (word-aligned) location.
Note: The previouslycovered MOV Wns, f instruction cannotbe used
for byteoperations!
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
24/75
24
MOV.B WREG, f Instruction Execution
A byte copy operation is shown.
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family.
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
25/75
25
MOV{.B} WREG, f Instruction Format
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
26/75
26
MOV{.B } f {,WREG} Instruction
Copy contents of data memory location f to WREG (default workingregister) . General form:
MOV{.B} f, WREG (f) WREG
MOV{.B} f (f) f
This instruction provides upward compatibilitywith earlier PIC C.WREGis register W0, and f is a location within the first 8192 bytes ofdata memory (neardata memory)
Can be used for either WORD or BYTE operations:
MOV 0x1000, WREG word operation
MOV.B 0x1001, WREG only lower 8-bits of W0 are affected.MOV 0x1000 Copies contents of 0x1000 back to
itself, will see usefulness of this later
Wordcopy must be from even (word-aligned) data memory location.
Note: The MOV f,Wnd instruction cannotbe used for byteoperations!
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
27/75
MOV{.B } f {,WREG} Format
27Copyright Delmar Cengage Learning 2008. All Rights Reserved.From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family .
O { } f G I t ti
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
28/75
28
MOV.{B } f, WREG Instruction
Execution
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family .
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
29/75
29
Move a literal into a Working RegisterMoves a literalinto a working register. The #indicates the numeric valueis aliteral, and NOTa memory address.
General form:
MOV #lit16, Wnd lit16 Wnd (word operation)
MOV.B #lit8, Wnd lit8 Wnd.lsb (byte operation)
The source operand in these examples use the immediateaddressing mode.
Examples:
MOV #0x1000, W2 0x1000 W2
MOV.B #0xAB, W3 0xAB W3.lsb
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
30/75
More on Literals
Observe that the following twoinstructions are very different!
MOV #0x1000, W2 after execution, W2=0x1000
after execution, W2 = (0x1000), thecontents of memory location 0x1000
MOV 0x1000,W2
30
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
31/75
MOV Literal Execution
31Copyright Delmar Cengage Learning 2008. All Rights Reserved.From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family .
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
32/75
MOV Literal Instruction Formats
32Copyright Delmar Cengage Learning 2008. All Rights Reserved.From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family .
I di t Add i
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
33/75
Indirect Addressing
MOV with indirectAddressing:
mov{.b} [Wso], [Wdo] ((Wso)) (Wdo)
[](brackets) indicate indirectaddressing.SourceEffective Address(EAs) is the content of Wso, or (Wso).Destination Effective Address(EAd) is the content of Wdo, or (Wdo).
The MOV instruction copies the content of the Source Effective Address to theDestination Effect Address, or:
(EAs) EAd
which is:
((Wso)) (Wdo)
33
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
34/75
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family .
Indirect Addressing
MOV Example
34
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
35/75
Why Indirect Addressing?
35
The instruction:
mov [W0], [W1]
Allowsus to do a memory-memory copywith oneinstruction!
The following is illegal:
mov 0x1000, 0x1002
Instead, would have to do (2 instructions):
mov 0x1000, W0
mov W0, 0x1002
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
36/75
Indirect Addressing Coverage
There are six formsof indirect addressing
The need for indirect addressing makes the mostsense when covered in the context of Cpointers This is done in Chapter 5
At this time, you will only need to understand thesimplestform of indirect addressing, which isregister indirectas shown on the previous twoslides.
Mostinstructions that support register directfor anoperand, also support indirectaddressing as wellfor the same operand However, must check PIC24 datasheet and book to
confirm.
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
37/75
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
38/75
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
39/75
39
SUB{.B } Wb, Ws , Wd Instruction
Three operand subtraction, register-to-register form:
SUB{.B} Wb, Ws, Wd (Wb)(Ws) WdWb, Ws, Wd are any of the 16 working registers W0-W15.
Be careful:
while ADD Wx, Wy, Wz gives the same result as ADD Wy, Wx, Wz
The same is not true for
SUB Wx, Wy, Wz versus SUB Wy, Wx, Wz
SUB W0, W1, W2 (W0)(W1) W2
SUB W1,W0, W2 (W1)(W0) W2
SUB.B W0, W1, W2 Lower 8 bits of W0, W1 aresubtracted and placed in the lower 8-
bits of W2
SUB{ B} Wb Ws Wd Execution
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
40/75
SUB{.B } Wb, Ws, Wd Execution
40
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family.
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
41/75
Subtraction/Addition with Literals
Three operand addition/subtraction with literals:ADD{.B} Wb, #lit5, Wd (Wb) +#lit5 Wd
SUB{.B} Wb, #lit5, Wd (Wb)#lit5 Wd
#lit5 is a 5-bit unsigned literal; the range 0-31. Provides a convenientmethod of adding/subtracting a small constantusing a single instruction
Examples
ADD W0, #4, W2 (W0) + 4 W2
SUB.B W1,#8, W3 (W1)8 W3
ADD W0, #60, W1 illegal, 60 is greater than 31!
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
42/75
42
ADD{.B } f {,WREG} Instruction
Two operand addition form:
ADD{.B} f (f) + (WREG) fADD{.B} f, WREG (f) + (WREG) WREG
WREG is W0, f is limited to first 8192 bytes of memory.
One of the operands, either f or WREG is always destroyed!
ADD 0x1000 (0x1000) + (WREG) 0x1000
ADD 0x1000,WREG (0x1000) + (WREG) WREG
ADD.B 0x1001, WREG (0x1001) + (WREG.lsb) WREG.lsb
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
43/75
ADD{ B} f { WREG} Execution
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
44/75
44
ADD{.B } f {,WREG}Execution
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family .
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
45/75
Increment
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
46/75
V 0.2 46
IncrementIncrement operation, register-to-register form:
INC{.B} Ws, Wd (Ws) +1 Wd
Increment operation, memory to memory/WREG form:
INC{.B} f (f) + 1 f
INC{.B} f, WREG (f) + 1 WREG
(fmust be in first 8192 locations of data memory)
Examples:
INC W2, W4 (W2) + 1 W4
INC.B W3, W3 (W3.lsb) + 1 W3.lsb
INC 0x1000 (0x1000) +1 0x1000
INC.B 0x1001,WREG (0x1001)+1 WREG.lsb
Decrement
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
47/75
V 0.9
DecrementDecrement operation, register-to-register form:
DEC{.B} Ws, Wd (Ws)1 Wd
Increment operation, memory to memory/WREG form:
DEC{.B} f (f)1 f
DEC{.B} f, WREG (f)1 WREG
(fmust be in first 8192 locations of data memory)
Examples:
DEC W2, W4 (W2)1 W4
DEC.B W3, W3 (W3.lsb)1 W3.lsb
DEC 0x1000 (0x1000)1 0x1000
DEC.B 0x1001,WREG (0x1001)1 WREG.lsb
47
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
48/75
How is the instruction register loaded?
17 x 17 Multipliernot shown
Program Counter
23
addressProgram Memory,
non-volatile, up to
4M words (4M x 24)DOUT
24
ALU
DataMemInst. Reg
16
16
16
Data
16 address
16
16
16The Program coun tercontains theprogram memory address of the instruction
that will be loaded into the instructionregister . After reset, the first instructionfetched from location 0x000000inprogram memory, i.e., the program counteris reset to 0x000000.
16 x 16Working
Reg array
48
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
49/75
Program Memory Organization
An instruction is 24 bits (3 bytes). Program memory should be viewed as
words (16-bit addressable), with the upper byte of the upper word of aninstruction always reading as 0. Instructionsmust start on even-wordboundaries. Instructions are addressedby the Program counter(PC).
49Figure adapted with permission of the copyright owner,Microchip Technology, Incorporated. All rights reserved.
Goto location (goto )
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
50/75
50
Goto location (goto)How can the program counter be changed?
A GOTOinstruction is an unconditional jump.Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family .
Valid addressing modes
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
51/75
51
Valid addressing modes.What are valid addressing modes for instructions?
The definitive answer can be found in Table 19-2 of the PIC24H32GP202
datasheet.
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family .
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
52/75
What does Wso, Wsd, Wnetc. mean?
52
Table 19-1: Symbols used in opcode descriptions (partial list)
MOV Wso, Wdo
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
53/75
ADD forms
53
Legal:
ADD W0, W1, W2ADD W0, [W1], [W4]
Illegal:
ADD [W0],W1,W2 ;first operand illegal!
ADD Wb, Ws, Wd
Vid t t i l
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
54/75
54
Video tutorials
A number of videos illustrate important concepts; all are listed on the video pageat http://www.reesemicro.com/site/pic24micro/Home/pic24-video-tutorials-1.
Available tutorials, which cover topics on the following pages of these lecturenotes:
MPLAB IDE introductionathttp://www.ece.msstate.edu/courses/ece3724/main_pic24/videos/mplab_assem/index.htm
A simple assembly language programathttp://www.ece.msstate.edu/courses/ece3724/main_pic24/videos/assem_intro/index.htm
Simulation of this programathttp://www.ece.msstate.edu/courses/ece3724/main_pic24/videos/assem_intro2/index.htm
Converting the program from 8 to 16 bitsathttp://www.ece.msstate.edu/courses/ece3724/main_pic24/videos/assem_intro3/index.htm
A Si l P
http://www.reesemicro.com/site/pic24micro/Home/pic24-video-tutorials-1http://www.ece.msstate.edu/courses/ece3724/main_pic24/videos/mplab_assem/index.htmhttp://www.ece.msstate.edu/courses/ece3724/main_pic24/videos/assem_intro/index.htmhttp://www.ece.msstate.edu/courses/ece3724/main_pic24/videos/assem_intro2/index.htmhttp://www.ece.msstate.edu/courses/ece3724/main_pic24/videos/assem_intro3/index.htmhttp://www.ece.msstate.edu/courses/ece3724/main_pic24/videos/assem_intro3/index.htmhttp://www.ece.msstate.edu/courses/ece3724/main_pic24/videos/assem_intro2/index.htmhttp://www.ece.msstate.edu/courses/ece3724/main_pic24/videos/assem_intro/index.htmhttp://www.ece.msstate.edu/courses/ece3724/main_pic24/videos/mplab_assem/index.htmhttp://www.reesemicro.com/site/pic24micro/Home/pic24-video-tutorials-1 -
8/11/2019 EE353 L03 - PIC24 Family.ppt
55/75
55
A Simple Program
C Program equivalent
#define avalue 100uint8 i,j,k;
i = avalue; // i = 100
i = i + 1; // i++, i = 101
j = i; // j is 101
j = j - 1; // j--, j is 100
k = j + i; // k = 201
In this class, will present programs in Cform, then translate (compile) them toPIC24 C assembly language.
A uint8 variable is 8 bits(1 byte)
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
56/75
56
Where are variables stored?
When writing assembly language, can use any free data memory location tostore values, it your choice.
A logical place to begin storing data in the first free location in data memory,which is 0x0800 (Recall that 0x0000-0x07FF is reserved for SFRs).
Assign ito0x0800,jto 0x0801, and kto 0x0802. Other choices could be made.
C to PIC24 Assembly
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
57/75
57
Cto PIC24 Assembly
Comments: The assembly language program operation is not veryclear. Also, multiple assembly languagestatements are needed forone Clanguage statement. Assembly language is more pr imi t ive(operations less powerful) than C.
Copyright Delmar Cengage Learning 2008. All Rights Reserved.
From: Reese/Bruce/Jones, Microcontrollers: From Assembly to C with the PIC24 Family .
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
58/75
58
PIC24 Assembly to PIC24 Machine Code
Could performthis step manuallybydetermining the instruction formatfor eachinstruction from the data sheet.
Much easier to let a program called anassemblerdo this step automatically
The MPLABIntegrated Design Environment(IDE) is used to assemble PIC24 programsand simulate them Simulate means to execute the program without
actually loading it into a PIC24 microcontroller
.include "p24Hxxxx.inc"l b l t
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
59/75
59
.global __reset
.bss ;reserve space for variablesi: .space 1j: .space 1k: .space 1.text ;Start of Code section__reset: ; first instruction located at __reset label
mov #__SP_init, W15 ;;initialize stack pointermov #__SPLIM_init,W0mov W0,SPLIM ;;initialize Stack limit reg.avalue = 100
; i = 100;mov.b #avalue, W0 ; W0 = 100
mov.b WREG,i ; i = 100; i = i + 1;
inc.b i ; i = i + 1; j = i
mov.b i,WREG ; W0 = imov.b WREG,j ; j = W0
; j = j 1;
dec.b j ; j= j1
; k = j + imov.b i,WREG ; W0 = iadd.b j,WREG ; W0 = W0+j (WREG is W0)mov.b WREG,k ; k = W0
done:goto done ;loop forever
This file can beassembled by the
MPLABassemblerinto PIC24 machinecode and simulated.
Labels used formemory locations
0x0800 (i), 0x0801(j),0x0802(k) to increasecode clarity
mptst_byte.s
I l d fil th t d fi i
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
60/75
60
mptst_byte.s(cont.)
.include "p24Hxxxx.inc"
.global __reset
.bss ;reserve space for variablesi: .space 1
j: .space 1k: .space 1
Include filethat defines variouslabelsfor a particular processor.. includeis an assembler directive.
The .bssassembler directive
indicates the following shouldbe placedin data memory. Bydefault, variables are placedbeginning at the first freelocation, 0x800.
The .spaceassemblerdirectivereserves space inbytesfor the named variables.i, j, k are labels, and labels arecase-sensitive and must be
followed by a :(colon).
An assemb ler direct iveis not a PIC24instruction, but an instruction to theassembler program. Assembler
directives have a leading .period, andare not case sensitive.
Declare the __reset label asglobalit is is needed by linkerfor defining program start
t t b t ( t )
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
61/75
61
mptst_byte.s(cont.)
.text__reset: mov #__SP_init, W15
mov #__SPLIM_init,W0mov W0,SPLIM
avalue = 100
The equal sign is an assembler directivethatequates a labelto a value.
.textis an assembler directivethat says what followsis code.Our first instructionmust belabeled as __reset.
These move instructioninitializes the stack pointer and
stack limit registersthis will bediscussed in a later chapter.
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
62/75
62
mptst_byte.s(cont.)
; i = 100;mov.b #avalue, W0 ; W0 = 100mov.b WREG,i ; i = 100
; i = i + 1;
inc.b i ; i = i + 1; j = i
mov.b i,WREG ; W0 = imov.b WREG,j ; j = W0
; j = j 1;dec.b j ; j= j 1
; k = j + imov.b i,WREG ; W0 = iadd.b j,WREG ; W0 = W0+j (WREG is W0)
mov.b WREG,k ; k = W0
The use of labelsand commentsgreatly improves the clarityof theprogram.
It is hard to over-comment anassembly language program ifyou want to be able tounderstand it later.
Strive for at least a commentevery other line; refer to lines
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
63/75
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
64/75
Clock Cycles vs. Instruction Cycles
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
65/75
65
y yThe clock signal used by a PIC24 C to control instruction execution can begenerated by an off-chip oscillatoror crystal/capacitor network, or by usingthe internal RC oscillator within the PIC24 C.
For the PIC24H family, the maximum clock frequency is 80 MHz.
An instruction cycle (Fcy)is twoclock (Fosc)cycles.
A PIC24 instruction takes 1 or 2instruction (Fcy)cycles, depending on theinstruction (see Table 19-2, PIC24HJ32GP202 data sheet). If an instruction
causes the program counter to change (i.e, GOTO), that instruction takes 2instruction cycles.
An add instruction takes 1 instruction cycle. How much time is this if theclock frequency (Fosc) is 80 MHz ( 1 MHz = 1.0e6 = 1,000,000 Hz)?
1/frequency = period, 1/80 MHz = 12.5 ns (1 ns = 1.0e-9 s)1 Add instruction @ 80 MHz takes 2 clocks * 12.5 ns = 25 ns (or 0.025 us).
By comparison, an Intel Pentium add instruction @ 3 GHz takes 0.33 ns (330 ps).An Intel Pentium could emulate a PIC24HJ32GP202 faster than a PIC24HJ32GP202can execute! But you cant put a Pentium in a toaster, or buy one from Digi-key for
$5.00.
Important!!!!!!!
How long does mptst_byte.s take to execute?
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
66/75
g p _ y
66
InstructionCycles
mov #__SP_init, W15 1
mov #__SPLIM_init,W0 1
mov W0,SPLIM 1
mov.b #avalue, W0
1
mov.b WREG,i 1
inc.b i 1
mov.b i,WREG 1
mov.b WREG,j 1
dec.b j 1
mov.b i,WREG 1
add.b j,WREG 1
mov.b WREG,k 1
Total
12
Beginning at the __reset label, and ignoring the gotoat the end, takes 12instruction cycles, which is 24 clock cycles.
Wh t if d 16 bit i bl
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
67/75
What if we used 16-bit variables
instead of 8-bit variables?
67
C Program equivalent
#define avalue 2047uint16 i,j,k;
i = avalue; // i = 2047
i = i + 1; // i++, i = 2048
j = i; // j is 2048
j = j - 1; // j--, j is 2047
k = j + i; // k = 4095
A uint16 variable is 16bits (1 byte)
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
68/75
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
69/75
An Alternate Solution (16-bit variables)
69
C Program equivalent
#define avalue 2047uint16 i,j,k;
i = avalue; // i = 2047i = i + 1; // i++, i = 2048j = i; // j is 2048j = j - 1; // j--, j is 2047
k = j + i; // k = 4095
;Assign variables to registers;Move variables into registers.;use register-to-register operations forcomputations;
;write variables back to memory
;assign i to W1, j to W2, k to W3
mov #2047,W1 ; W1 (i) = 2047inc W1,W1 ; W1 (i) = W1 (i) + 1mov W1,W2 ; W2 (j) = W1 (i)dec W2,W2 ; W2 (j) = W2 (j) -1add W1,W2,W3 ; W3 (k) = W1 (i) + W2 (j);;write variables to memorymov W1,i ; 0x800 (i) = W1
mov W2,j ; 0x802 (j) = W2mov W3,k ; 0x804 (k) = W3
Previous approach took 9instructions, this one took 8instructions. In this case, this
approach is more efficient!
How long does mptst_word.s take to execute?
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
70/75
70
Instruction
Cycles
mov #__SP_init, W15 1
mov #__SPLIM_init,W0 1
mov W0,SPLIM 1
mov #avalue, W0
1
mov WREG,i 1
inc i 1
mov i,WREG 1
mov WREG,j 1
dec j 1
mov i,WREG 1
add j,WREG 1
mov WREG,k 1
Total
12
Ignoring the gotoat the end, takes 12 instruction cycles, which is 24 clockcycles.
16-bit operations versus 8-bit
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
71/75
16-bit operations versus 8-bit
71
The 16-bit versionof the mptstprogram requires the same number ofinstructionbytesand the samenumber of instruction cyclesas the 8-bitversion.
This is because the PIC24family is a 16-bitmicrocontroller; its naturaloperation size is 16 bits, so 16-bit operationsare handled as efficientlyas 8-bitsoperations.
On an 8-bit processor, like the PIC18family, the 16-bitversion wouldtake roughly doublethe number of instructions and clock cycles as the8-bitversion.
On the PIC24, a 32-bitversion of the mptstprogram will takeapproximately twicethe number of instructions and clock cycles as the16-bit version. We will look at 32-bit operations later in the semester.
Review: Units
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
72/75
72
Review: UnitsIn this class, units are always used for physical quantity:
Time Frequency
milliseconds (ms = 10-3s) kilohertz (kHz = 103Hz)
microseconds (
s = 10-6s) megahertz (MHz = 106Hz)
nanoseconds (ns = 10-9s) gigahertz (GHz = 109Hz)
When a time/frequency/voltage/current quantity is asked for, I will always ask forit in some units. Values for these quantities in datasheets are ALWAYS given inunits.
For a frequency of 1.25 kHz, what is the period in s?
period = 1/f = 1/(1.25 e3) = 8.0 e4 secondsUnit conversion= 8.0e-4 (s) * (1e6 s)/1.0 (s) = 8.0e2 s = 800 s
PIC24H Family
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
73/75
73
PIC24H Family
Microchip has an extensive line of PICmicro
microcontrollers, with the PIC24 familyintroduced in 2005.
The PIC16and PIC18are olderversions of thePICmicrofamily, have been several previous
generations. Do not assumethat because something is
done one way in the PIC24, that it is the mostefficient method for accomplishingthat action.
The datasheet for the PIC24HJ32GP202 isfound on the LMS.
Some PICMicros that we have used
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
74/75
V 0.2 74
Features 16F87x
(Fall 2003)
PIC18F242
(Summer 2004)
PIC24H
(Summer 2008)
Instructionwidth
14 bits 16 bits 24 bits
Program
memory
8K instr. 8K instructions ~10K instructions
DataMemory
368 bytes 1536 bytes 2048 bytes
Clock speed Max 20 MHz, 4
clks=1instr
Max 40 MHz
4 clks=1instr
Max 80 MHz
2 clks=1 instr
Architecture Accumulator, 8-
bit architecture
Accumulator, 8-bit
architecture General purposeregister, 16-bit
architecture
The PIC24H can execute about 6x faster than the PIC18F242 previouslyused in this class.
Wh t d d t k ?
-
8/11/2019 EE353 L03 - PIC24 Family.ppt
75/75
What do you need to know?
Understand the PIC24 basic architecture(program and data memory organization)
Understand the operation of mov, add, sub, inc,dec, goto instructionsand their various
addressing modeforms Be able to convert simple C instruction
sequences to PIC24 assemblylanguage
Be able to assemble/simulate a PIC24 C assembly
language program in the MPLAB IDE
Understand the relationship between instructioncycles and machine cycles