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PRELAB 3 REPORT

EE 271 Group 3

Instructor:Nguyen The Nghia

Student:

-Doan Thanh Thien

- Nguyen Van Trong

- Huynh Minh Hai

Problem: we have to design a system which will control the traffic light at a junction where the

Highway and Country Road intersect each other.

Requirements: we have a sensor in country road which will detect whether the road has cars or not.

When the sensor is activated (detect cars in country road) the light in Highway will change from

green to yellow then to red and the light in country road will change from red to green. There is some

delay time when go from this state to another state and we should can control that delay. In this

project we use 5sec delay for Red Red state and 3sec delay for YellowRed state.

Analysis problem:

- According to the requirements above we see that state machine is the most suitable method forsolving this problem.

- We will divide it into 5 states: State 0(S0): the light in Highway will be green and in Country Road will be Red. State 1(S1): the light in Highway will be changed to yellow and the light in Country Road is

still Red

State 2 (S2): the light in Highway will be Red and the light in Country Road now is changedto Green.

State 3 (S3): the light in Highway is still Red; the light in Country Road now is turned intoYellow.

From all above we can build a truth table:

State HwG HwY HwR FwG FwY FwR

S0 1 0 0 0 0 1

S1 0 1 0 0 0 1

S2 0 0 1 1 0 0

S3 0 0 1 0 1 0

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State Highway Country Road

S0 Green Red

S1 Yellow Red

S2 Red Green

S3 Red Yellow

State Machine Diagram

Algorithm description:

Variables description:

- We will use : 6 L.E.Ds (HwR, HwG, HwY, FwR, FwG, FwY)to display :

+ Highway: Red, Green, Yellow

+ Country Road: Red, Green, Yellow

X: active high, use to detect whether have car in country road or not. Count: 3 bit control time delays (counting depends on clock ) State: 3 bit to save the current and next state. Reset: active high, used to reset program.

CODE:

S0

S1

S2

S3

0

1

1

0

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1/ Clock Design:

module clock_design (clock_in, resetn, clock_out);

input clock_in, resetn;

output clock_out;

wire [31:0] clk;

parameter which_clock = 1;

clock_divider cdiv (clock_in, reset, clk);

assign clock_out = clk[which_clock];

assign reset = ~resetn;

endmodulemodule clock_divider (clock, reset, divided_clocks);

input clock, reset;

output reg [31:0] divided_clocks = 0;

always @(posedge clock, posedge reset) begin

if(reset)divided_clocks

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2/ Delay:

module signal(Time, Active, resetn, clk,Sig, display);

output reg Sig;

output reg [13:0] display;

input clk, resetn, Active;

input [4:0] Time;reg [4:0] count;assign reset = ~resetn;

always @(posedge clk, posedge reset) begin

if(reset || Active == 0) begin // setting the initial value

count = 0;Sig = 0;

display = 0;

end

else begin

if(count < Time - 1) begin

count = count + 1;Sig = 0;

end

else begin

Sig = 1;

count = 0;

end

display[13:7] = (Time - count) / 10; // This is first digit of 7-seg LED

display[6:0] = (Time - count) % 10; // This is second one

end

end

endmodule

//Testbench

//Included : module Display

module delay_tb;wire [0:13] display_tb;

wire clk_out_tb;

wire Sig_tb;

wire [0:6] HEX1_tb, HEX0_tb;

reg [4:0] Time_tb;

reg Active_tb;

reg clk_in_tb;

reg resetn_tb;

//Initialize value of clock

initial begin

clk_in_tb = 1;resetn_tb = 0;

#5 resetn_tb = 1;

Active_tb = 0;

Time_tb = 0;

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#20 Time_tb = 10;

Active_tb = 1;

#50 resetn_tb = 0;

#50 resetn_tb = 1;

#300 Active_tb = 0;

#20 Time_tb = 22;

Active_tb = 1;end

//Clock generator

always begin: CLOCK_GENERATOR

#5 clk_in_tb = ~clk_in_tb; //Toggle clock every 5 ticks

end

clock_design myClock(clk_in_tb, resetn_tb, clk_out_tb);

delay myDelay(Time_tb, Active_tb, resetn_tb, clk_out_tb, Sig_tb, display_tb);

led7segs myLed7segs(display_tb, HEX1_tb, HEX0_tb);

endmodule

3/ Led 7 segments

module led7segs(decimal, HEX1, HEX0);// This module is to display 2 BCD on 2 7-segment LEDs

output reg [0:6] HEX1, HEX0;

input [13:0] decimal;

//Behavior of led7segs HEX[1]

always @(decimal[13:7]) begin

case (decimal[13:7])

4'b0000: HEX1 = 7'b0000001; // 04'b0001: HEX1 = 7'b1001111; // 1

4'b0010: HEX1 = 7'b0010010; // 2

4'b0011: HEX1 = 7'b0000110; // 3

4'b0100: HEX1 = 7'b1001100; // 4

4'b0101: HEX1 = 7'b0100100; // 5

4'b0110: HEX1 = 7'b0100000; // 6

4'b0111: HEX1 = 7'b0001111; // 7

4'b1000: HEX1 = 7'b0000000; // 8

4'b1001: HEX1 = 7'b0000100; // 9

//default: HEX1 = 7'b1111111; // All led off

endcaseend

//Behavior of led7segs HEX[0]

always @(decimal[6:0]) begin

case (decimal[6:0])

4'b0000: HEX0 = 7'b0000001; // 0

4'b0001: HEX0 = 7'b1001111; // 1

4'b0010: HEX0 = 7'b0010010; // 2

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4'b0011: HEX0 = 7'b0000110; // 3

4'b0100: HEX0 = 7'b1001100; // 4

4'b0101: HEX0 = 7'b0100100; // 5

4'b0110: HEX0 = 7'b0100000; // 6

4'b0111: HEX0 = 7'b0001111; // 7

4'b1000: HEX0 = 7'b0000000; // 84'b1001: HEX0 = 7'b0000100; // 9

//default: HEX0 = 7'b1111111; // All led off

endcase

end

endmodule

4/ Traffic:

module Traffic(clk, X, reset, Sig, out,state, Active, numdelay);

input clk, X, reset;

output reg [0:5] out;

output reg [0:1] state;

wire clkin, display;output reg Active;

output reg [0:4] numdelay;

output Sig;

parameter zero=0, one=1, two=2, three=3, delay01 = 7, delay12 = 5, delay23 = 7, delay30 = 5;

//clock_design myclk(clkin, reset, clk);

//delay mydelay(numdelay, Active, reset, clkout, Sig, display);

always @(state)

begin

case (state)

zero:

out = 6'b010100;

one:

out = 6'b001100;

two:

out = 6'b100010;

three:

out = 6'b100001;default:

out = 6'b010100;

endcase

end

always @(negedge reset or posedge clk )

begin

if (reset==0) begin

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state

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numdelay = delay30;

end else begin

state