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IC DesignTrendsIC DesignTrendsand ITRS Design and ITRS Design ChallengesChallenges

[Adopted from Donovan Lee and Tsu-Jae King UC Berkeley and Andrew B. Kahng, UCSD, URL: http://vlsicad.ucsd.eduURL: http://vlsicad.ucsd.edu]

EE1412

New Trends in IC DesignNew Trends in IC Design

Fin FET GHZ Applications NEMFET ITRS Challenges Productivity Gap Design for Manufacturability

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20Ghz +20Ghz +

FinFET has been manufactured to 18nm Still acts as a very good transistor

Simulation shown that it can be scaled to 10nm Quantum effect start to kick in

– Reduce mobility by ~10%

Ballistic transport become significant

– Increase current by about ~20%

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Hybrid Nano-Electro-Mechanical TransistorsHybrid Nano-Electro-Mechanical Transistors Donovan Lee and Tsu-Jae King UC BerkeleyDonovan Lee and Tsu-Jae King UC Berkeley

• Lower power ( better power/performance tradeoff )

• More functionality• Testbed for quantum stiction effects such

as the Casimir Force.• Each NEMFET transistor can be used as a

drop-in non-volatile memory cell, with no change to circuit architecture from current flash designs.

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Design Considerations

• Snapdown of the gate will occur when the displacement is 1/3rd the effective gap thickness.

• This voltage is described by:

• Varying the air gap allows us to therefore design a NEMFET for either snapdown or analog operation.

Ww

kggVVP

0

30

0 27

8)3/2(

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Design Considerations

• Parallel-plate capacitive actuation theory:

• k (spring constant) is a function of the gate dimensions and is proportional to 1/length3, thickness3

and width.

Displacement vs. Voltage

0.00

2.00

4.00

6.00

8.00

10.00

12.00

14.00

16.00

0 0.1 0.2 0.3 0.4 0.5

Vgate [V]

Dis

pla

ce

me

nt

[A]

10A oxide/10Aair, k=0.005N/cm10A oxide/1Aair, k=0.55 N/cm

)(2

02

0

gggWw

kV

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NEMFET as a dynamic Vt logic device

• When gate voltage (input signal) is high, electrostatic attraction drives the mechanical cantilever gate closer to the substrate, resulting in lower Vt (higher current) and higher capacitance. When gate voltage is low, the gate returns to its low Vt position.

• The equivalent permittivity of air results in tair = 3tox, which can be advantageous when creating a snapdown-mode device.

n+ n+p

VD > 0VG = 0

n+ n+p

VD > 0VG > 0

20nm

High Vt Low Vt

air gap

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Power Consumption / Performance

• Static power consumption drastically improved by 85%.

NEMFET vs. Non-mechanical FET's

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 0.1 0.2 0.3 0.4 0.5 0.6

Vg

Id

NEMFET 10A oxide/1A air ANALOGmode

10A Tox Non-mech FET

13A Tox Non-mech FET

NEMFET 10A oxide/10A airSNAPDOWN mode

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Power Consumption / Performance

• Drive current remains same for comparable Drive current remains same for comparable technology lines without mechanical gate and air technology lines without mechanical gate and air gap.gap.

• Analog-mode operation (dark curve) is smooth and Analog-mode operation (dark curve) is smooth and can be modeled easily as a regular MOS with can be modeled easily as a regular MOS with higher swing capabilities.higher swing capabilities.

• Snapdown-mode operation (light blue) can be Snapdown-mode operation (light blue) can be designed to draw less dynamic power during designed to draw less dynamic power during switching than analog-mode NEMFET and snap to switching than analog-mode NEMFET and snap to

full drive just before reaching Vdd.full drive just before reaching Vdd.

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I TRS 2001 Renewal - Work in Progress - Do Not Publish

6

ITRS Roadmap Acceleration Continues...

1998/1999 DRAM Half-Pitch

500

350

250

180

130

100

70

50

35

25

Year of Production

Fe

atu

re S

ize

(n

m)

Te

ch

no

log

y N

od

e -

DR

AM

Ha

lf-P

itc

h (

nm

)

95 97 99 01 04 07 10 13 162001 Renewal Period

95 97 99 01 04 07 10 13 16500

350

250

180

130

100

70

50

35

25

2000 Update, Sc 2.0

MPU/ASIC Gate “In Resist” 1999 ITRS

Technology Node (DRAM Half Pitch)

MPU/ASIC

Gate Length

Minimum

Feature Size

XX90XX65XX45XX32XX22

16

~.7x pertechnologynode (.5xper 2 nodes)

11

8.0

Scenario 2.0/DRAM 3.7/MPU

(2-yr cycle M/ A HP & G.L. <2005; 3yr >2005)

Sc 3.7 MPU/ASIC Half- Pitch (1- year Lag Thru 2002, then equal to DRAM after 2004)

“Most Aggressive” Sc 3.7 = 2- yr<’05; 3- yr >’05: MPU Printed (PrGL) & Physical (PhGL) Gate Length cycle; (ASIC/Lo Power Pr/PhGL 2- year delay from MPU Pr/PhGL)

DRAM Sc 2.0 = 3- yr cycle after 2001

2- Year Node Cycle 1995- 2001

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Req’d Performance for Multi-Media ProcessingReq’d Performance for Multi-Media ProcessingGOPS

0.01 0.1 1 10VideoVideo

AudioAudioVoiceVoice

CommunicationCommunicationRecognitionRecognition

GraphicsGraphics

FAXModem

2D Graphics

3D Graphics

MPEGDolby-AC3

JPEG

MPEG1Extraction

MPEG2 ExtractionMP/ML MP/HLCompression

VoIP Modem

Word Recognition

Sentence Translation

GOPS: Giga Operations Per Second

100

Voice Auto Translation

10Mpps 100Mpps

MPEG4

Face RecognitionVoice Print Recognition

SW Defined Radio

Moving Picture Recognition

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YEAR

TECHNOLOGY NODE

2001 2002 2003 2004 2005 2006 2007

DRAM ½ PITCH (nm) (SC. 2.0) 130 115 100 90 80 70 65

MPU/ASIC ½ PITCH (nm) (SC. 3.7) 150 130 107 90 80 70 65

MPU PRINTED GATE LENGTH (nm) (SC. 3.7) 90 75 65 53 45 40 35

MPU PHYSICAL GATE LENGTH (nm) (SC. 3.7) 65 53 45 37 32 28 25

Conductor effective resistivity(-cm) Cu intermediate wiring*

2.2 2.2 2.2 2.2 2.2 2.2 2.2

Barrier/cladding thickness(for Cu intermediate wiring) (nm)

18 15 13 11 10 9 8

Interlevel metal insulator—effective dielectric constant ()

3.0-3.7 3.0–3.7 2.9–3.5 2.5–3.0 2.5–3.0 2.5–3.0 2.0–2.5

Interlevel metal insulator (minimumexpected)—bulk dielectric constant ()

2.7 2.7 2.7 2.2 2.2 2.2 1.7

Dielectric Permittivity: Near Term YearsDielectric Permittivity: Near Term Years

Bulk and effective dielectric constants described

Porous low-k requires alternative planarization solutions

Cu at all nodes - conformal barriers

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Cu Resistivity vs. Linewidth Without Cu Barrier

1.5

1.6

1.7

1.8

1.9

2

2.1

2.2

2.3

2.4

2.5

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Line Width (um)

Res

isti

vity

(u

oh

m-c

m)

70nm ITRS RequirementWITH Cu Barrier

100nm ITRS RequirementWITH Cu Barrier

Effect Of Line Width On Cu Resistivity

Courtesy of SEMATECH

Conductor resistivity increasesexpected to appear around 100 nm linewidth -will impact intermediate wiring first - ~ 2006

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The Productivity GapThe Productivity Gap

Source: SEMATECHSource: SEMATECH

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Mask CostMask Cost

O(25 mask levels) ~ “$1M mask set” in 130nmBut: average only 500 wafers per mask set !

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0%

20%

40%

60%

80%

100%

1999

2002

2005

2008

2011

2014

% Area Memory

% Area ReusedLogic

% Area New Logic

Percent of die area that must be occupied by memory to maintain SOC design productivity

Design Productivity Gap Design Productivity Gap Low-Value Designs? Low-Value Designs?

Source = Japanese system-LSI industry

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Reduce Back-End Effort ?Reduce Back-End Effort ?

Example: repeating Example: repeating dense wiring fabricdense wiring fabricpattern at minimum pitchpattern at minimum pitch

S SV V SG

SG

SSV

V

SS SSVV VV SSGG

- Eliminates signal integrity, delay uncertainty concerns- Eliminates signal integrity, delay uncertainty concerns- But has at least 60% - 80% density cost- But has at least 60% - 80% density cost

source: MARCO GSRC

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Improve IP Reuse Productivity ?Improve IP Reuse Productivity ?

MacroShells (the Protocol Interface)Communication Channels

MicroShells (the IP Requirements)

P1

P2

P3

P4

P5

P6

P7

Pearls (the IP Processes)

source: MARCO GSRC

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Embedded ProcessorsLP ARM0.5-2 MIPS/mW

ASIPsDSPs

1 V DSP 3 MOPS/mW

QUALITY Problem : > 1000x QUALITY Problem : > 1000x

Energy-Flexibility GapEnergy-Flexibility Gap

DedicatedHW

Flexibility (Coverage)

En

ergy

Eff

icie

ncy

MO

PS

/mW

(or

MIP

S/m

W)

0.1

1

10

100

1000

ReconfigurableProcessor/Logic

10-50 MOPS/mW

100-200 MOPS/mW

Source: Prof. Jan Rabaey, UC Berkeley

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““Keep the Fabs Full”Keep the Fabs Full” Foundry capital cost > $2B Design technology must keep manufacturing

facilities fully utilized with: high-volume parts high-margin parts

What happens when design technology “fails” ? not enough high-value designs the semiconductor industry will find a “workaround”

– reconfigurable logic

– platform-based design

– extract value somewhere other than silicon differentiation

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Optical Proximity Correction (OPC)Optical Proximity Correction (OPC)

Corrective modifications to improve process control improve yield (process window) improve device performance

With OPCNo OPC

Original Layout

OPC Corrections

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Phase Shifting Masks (PSM)Phase Shifting Masks (PSM)conventional mask

glass

Chrome

phase shifting mask

Phase shifter

0 E at mask 0

0 E at wafer 0

0 I at wafer 0

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Field-Dependent AberrationField-Dependent Aberration

Cell A

Cell A

Cell A

(X 1 , Y 1)

(X 0 , Y 0)

(X 2 , Y 2)

F ie ld-dependentaberrationsaffect the fide lityand p lacem entof critica l c ircu itfeatures.

Big C hip

Field-dependent aberrations cause placement errors and distortions

),(A_CELL),(A_CELL),(A_CELL 220011 YXYXYX

Center: Minimal Aberrations

Edge: High Aberrations

Tow

ard

s Le

ns

Wafer Plane

Lens

R. Pack, Cadence

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Optical Lithography is not Going AwayOptical Lithography is not Going Away

Numerical Technologies, Inc.

Process window and yield enhancement: forbidden width-spacing combinations, generally complex “local DRCs”

Lithography equipment choices: forbidden configurations such as wrong-way critical-width doglegs, or diagonal features

Notch rules, critical-feature rules on local metal due to OPC (subresolution assist features, especially)

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P. Buck, Dupont Photomasks – ISMT Mask-EDA Workshop July 2001

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P. Buck, Dupont Photomasks – ISMT Mask-EDA Workshop July 2001

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Out-of-control mask flow

P. Buck, Dupont Photomasks – ISMT Mask-EDA Workshop July 2001

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FO4 INV Delays Per Clock PeriodFO4 INV Delays Per Clock Period

FO4 INV = inverter driving 4 identical inverters (no interconnect) Half of freq improvement has been from reduced logic stages

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Design is Also Part of NRE CostDesign is Also Part of NRE Cost

Design cost model (Gary Smith/Dataquest, 2001) engineer cost per year increases 5% per year

– ($181,568 in 1990)

EDA tool cost per engineer increases 3.9% per year– ($99,301 in 1990)

Productivity due to 8 major design technology innovations: – RTL methodology; In-house P&R; Tall-thin engineer; Small-block

reuse; Large-block reuse; IC implementation suite; Intelligent testbench; ES-level methodology

Matched up against SOC-LP PDA content: SOC-LP PDA design cost = $15M in 2001 Would have been $342M without EDA innovations and the

resulting improvements in design productivity

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SOC Design Cost Model

$3

42

,41

7,5

79

$1

5,0

66

,37

3

$10,000,000

$100,000,000

$1,000,000,000

$10,000,000,000

$100,000,000,000

1985 1990 1995 2000 2005 2010 2015 2020Year

To

tal D

esig

n C

ost

(l

og

sca

le)

RTL Methodology Only

With all Future Improvements

In-H

ouse

P&

R

Tal

l Thi

n E

ngin

eer

Sm

all B

lock

Reu

se

IC Im

plem

enta

tion

tool

s

Larg

e B

lock

Reu

se

Inte

lligen

t Tes

tben

ch

ES

Lev

el M

etho

dolo

gy

Design Cost of SOC-Design Cost of SOC-LP PDA DriverLP PDA Driver

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Technology Trend Over Generations

• Values are from ITRS, BPTM, and industry; red is 3σ

• From ongoing work at UCSD/UCB/Michigan; some values are off (e.g., Rvia)

Technology 180nm 130nm 100nm

Device nmos pmos nmos pmos nmos pmos

Leff (μm) 0.10 ±15% 0.12 ± 15% 0.09 ± 15% 0.09 ± 15% 0.06 ± 15% 0.06 ± 15%

Tox (nm) 40 ± 4% 42 ± 4% 33 ± 4% 33 ± 4% 25 ± 4% 25 ± 4%

Vth0 (V)0.40 ± 12.5%

-0.42 ± 12.5%

0.27 ± 15.5%

-0.35 ± 15.5%

0.26 ± 12.7%

-0.30 ± 12.7%

Rdsw (Ω/) 250 ± 10% 450 ± 10% 200 ± 10% 400 ± 10% 180 ± 10% 300 ± 10%

Interconnect

local global local global local global

ε 3.5 ± 3% 3.2 ± 5% 2.8 ± 5%

w (μm) 0.28 ± 20% 0.80 ± 20% 0.20 ± 20% 0.60 ± 20% 0.15 ± 20% 0.50 ± 20%

s (μm) 0.28 ± 20% 0.80 ± 20% 0.20 ± 20% 0.60 ± 20% 0.15 ± 20% 0.50 ± 20%

t (μm) 0.45 ± 10% 1.25 ± 10% 0.45 ± 10% 1.20 ± 10% 0.50 ± 10% 1.20 ± 10%

ILDh (μm) 0.65 ± 15% 1.80 ± 15% 0.45 ± 15% 1.60 ± 15% 0.30 ± 15% 1.20 ± 15%

Rvia (Ω) 46 ± 20% 50 ± 20% 54 ± 20%

Length (μm) 61.01 1061 45.19 1127 33.90 1247

Wn/Ln (μm) 1.26/0.18 20/0.18 0.91/0.13 15/0.13 0.80/0.10 10/0.10

Dynamic

Temp (oC) 25-100 25/100 25/100

Vdd (V) 1.8 ± 10% 1.5 ± 10% 1.2 ± 10%

Tr (ps) 160 95 60

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YEAR

TECHNOLOGY NODE

2001 2002 2003 2004 2005 2006 2007

DRAM ½ PITCH (nm) (SC. 2.0) 130 115 100 90 80 70 65

MPU/ASIC ½ PITCH (nm) (SC. 3.7) 150 130 107 90 80 70 65

MPU PRINTED GATE LENGTH (nm) (SC. 3.7) 90 75 65 53 45 40 35

MPU PHYSICAL GATE LENGTH (nm) (SC. 3.7) 65 53 45 37 32 28 25

Cu thinning at minimum pitch due to erosion(nm), 10% X height, 50% areal density, 500m square array

28 24 20 18 16 14 13

Cu thinning at minimum intermediate pitchdue to erosion (nm), 10% X height, 50% arealdensity, 500 m square array

36 30 27 23 20 18 18

Cu thinning global wiring due to dishing anderosion (nm), 10% X height, 80% arealdensity, 15 micron wide wire

67 57 50 48 40 35 32

Cu thinning global wiring due to dishing (nm),100 micron wide feature

40 34 30 29 24 21 19

Copper CMP Variability: Near Term YearsCopper CMP Variability: Near Term Years

Combined dishing/erosion metric for global wires

Cu thinning due to dishing for isolated lines/pads

No significant dishing at local levels - thinning due to erosion over large areas (50% areal coverage)

C. Case, BOC Edwards – ITRS-2001 preliminary

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Variation Sensitivities: Local Stage

• Sensitivity is evaluated by the percentage change in performance when there is 3σ variation at the parameter

• Device variations have larger impact on line delay and interconnect variations have stronger impact on crosstalk noise

Del

ay S

ensi

tivi

ty f

or

3σ

Var

iati

on

(%

)

0

5

10

15

20

25

30

Leff

Vth0

w

Vdd

180nm 130nm 100nm

Leff

Vth0

Rdsw

eps

w

t

ILDh

Vdd

0

5

10

15

20

25

180nm 130nm 100nm

No

ise

Sen

sit1

vity

fo

r

3σ

Var

iati

on

(%

)

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Source: Principles of Marketing, Prentice-Hall International Editions, Philip Kotler (1986)

Product Life Cycle

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AMD Processors

0

50

100

150

200

250

300

350

400

450

0 200 400 600 800 1000 1200 1400 1600

Clock Speed (MHz)

Pri

ce (

$)

Athlon MP

Athlon 4 Mobile

Athlon Desktop

Duron

Duron Mobile

Value and Getting to ROIValue and Getting to ROI

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Fiber O

ptic

Techn

ologie

s

Display

Techn

ologie

s

Micr

oelec

tronic

s

Techn

ologie

sPackaging

Technologies

Magnetic/Optical

Storage Technologies

Consumer

Computer

Telecom

Medical

Aerospace

Transportation

USA

Sof

twar

e, A

ppli

cati

ons

Battery Technologies

Product Life Cycle Product Life Cycle applies to every applies to every

product & serviceproduct & service

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Every part needs product Every part needs product development & innovationdevelopment & innovation

Apple® Computer

Nokia® Cellular Phone

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Paradigm ShiftParadigm Shift

0 10 20 30 40 50 6010

100

1,000

10,000

100,00

Sa

les

($M

illio

ns

)

Years in Business

CISCO(81%) SUN

(34%)

SGI(29%)

MICROSOFT

INTEL

ACUSON(60%)

HP(excluding computer

unit) (15%)

HP (all Units)(18%)

Special SC Mfg (PC)

Fabless Mfg

General M

fgInternet

NETSCAPE

SOURCE: Jim Gibbons, Stanford University

High Profit Low Profit

QUALCOMM

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Design Grand Challenges > 65nmDesign Grand Challenges > 65nm Scaling of maximum-quality design implementation

productivity– Overall design productivity must scale at 2x / node– Reuse of design, verification and test effort must scale at > 2x/node– Develop analog and mixed-signal synthesis, verification and test – Embedded software productivity

Power Management– Off-currents increase 10x/node; challenge - maintain constant static

power– Power dissipation for MPU exceeds package limits by 25x in 15 years; – Power optimizations must exploit many degrees of freedom -

multi-Vt, multi-Tox, multi-Vdd in core

Integration of Design technology with other ITRS technology areas

– Die-package co-optimization– Design for Manufacturability (sharing variability burden with Litho and

Interconnect, reduction of system NRE cost)– Design for Test

ITRS-2001 preliminary

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Design Grand Challenges < 65nmDesign Grand Challenges < 65nm Three Grand Challenges from > 65nm, and Noise Management

– Lower noise headroom especially in low-power devices; coupled interconnects; supply voltage IR drop and ground bounce; thermal impact on device off-currents and interconnect resistivities; mutual inductance; substrate coupling; single-event upset (alpha particle); increased use of dynamic logic families

– Modeling, analysis and estimation at all levels of design

Error-Tolerant Design– Relaxing 100% correctness requirement may reduce manufacturing,

verification, test costs

– Both transient and permanent failures of signals, logic values, devices, interconnects

– Novel techniques: adaptive and self-correcting / self-repairing circuits, use of on-chip reconfigurability

ITRS-2001 preliminary

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#1: Design for Value#1: Design for Value**

Mask cost trend Design for Value (DFV)

Design for Value Problem: Given

– Performance measure f– Value function v(f)

– Selling points fi corresponding to various values of f

– Yield function y(f)

Maximize Total Design Value = i y(fi)*v(fi)[or, Minimize Total Cost]

Probabilistic optimization regime* See "Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI", IEEE ASIC/SoC

Conference, September 2002, pp. 411-415.

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#2: Process-Aware Design#2: Process-Aware Design

Anisotropy vs. Vbias

Features in one direction – scanning, raster write, … may be better controllable

than those in the orthogonal direction

Single orientation throughout layout is preferred Dominant (critical-feature) orientation in layout

design should match write direction

Wafer symmetries e.g., etch gradient due to spin-on

Iso-Dense balancing imaging through focus

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#3: Intelligent MDP+Write#3: Intelligent MDP+WriteMDP driven by (write error * MEEF) = wafer

CD error

Partitioning into multiple gray-scale writing passes

Apertures, beam currents, dwell times, shot ordering, …

EDA tools define stripe, major field, subfield boundaries!

Electrical / functional defect criteria

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#4: Mask Write Optimizations#4: Mask Write Optimizations Conflicting goals: resolution, CD control, throughput Resist heating = large contributor to mask CD

variation “Self-Avoiding” Subfield Order for Mask Write

Max48.85CMean27.59C

Sequential schedule

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#5: Fill Parametric Yield Impact#5: Fill Parametric Yield Impact• Performance Impact Limited Fill (PIL-Fill)• Fill adds capacitance, hurts timing and SI closure

• Plain capacitance minimization objective is not sufficient

• CMP modeling layout density vs. dimensions built into RLCX

top view

buffer distance

fill gridpitch

Activelines

wBBAA CC

DD EE

GGFF

1

2

3

4

6

5

Activelines

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#6: Analog Rules#6: Analog Rules We don’t need no $#(*&(! “rules” Given adequate models of MDP, RET and Litho

flows, design tools can and should optimize parametric yield, $/wafer, profits More examples: critical-area reduction by

decompaction, introducing redundancy (vias, wires), …

Automated learning of models and “implicit rules” Current approach: test wafers, test structures,

second-hand understanding Future: machine learning techniques

EE14150

#7: Restricted Layout#7: Restricted Layout “Soft reset” = 1-time hit on Moore’s Law density scaling Restricted Design Rules (“RDR”) can be compensated many ways

embedded 1-T SRAM fabric, stacking, I/O circuit design, … N.B.: Moore’s Law is a “meta” Law!

Opaque

Phase Shifters0

180

Transparent

Checkerboard Islands

First ExposureTrim Mask Exposure

Dual Exposure Result

Dark-Field PSMs

or

0

180 Example: PhasePhirst! (Levenson et al.)

M. D. Levenson, 2003

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#8: Charging and Antennas#8: Charging and Antennas Process steps use plasmas, charged particles

Electrical fields over gate oxides induce damage (Vt shift) or breakdown

Limit antenna ratio = (Apoly + AM1 + …) / Agate-ox AMx = metal(x) area that is electrically connected to node without

using metal (x+1), and not connected to an active area Bridging (break antenna by hopping to higher layer)

– Extra wiring, vias, congestion Reverse-biased diode or source-drain contact near gate

– Leakage, area, timing penalties Will antenna ratios continue to decrease?

High-k gate dielectrics increased physical Tox less leaky, hard failure modes?

Tradeoff unfixed antenna yield penalty for fixed antenna yield loss?

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#9: Pattern Collapse#9: Pattern Collapse Pr(pattern collapse) = f(length)

Length-dependent spacing rules Limits wire AR, packing density

Cao et al. U. Wisconson

• Standardized embedding of long wires for manufacturability and physical reliability

becomes

???

EE14155

#10: Data Compression#10: Data Compression Today: RET + complexity exploding data volume Partitioning of compression and decompression?

Architecture question – where to put engines, I/F’s, storage?

Largely orthogonal to design considerations

Procedural compression largely unexplored? (Ex: Verilog + SP&R binaries + runscripts = representation of layout)

Design for compressibility? What is ROI of relaxing constraints on layout? Of +k bytes

of data? How context-sensitive must patterning be?

Use of lossy compression? What design features can be “lost”? (Ex: dummy fill)

EE14156

Choice of Geometric Compression OperatorsChoice of Geometric Compression Operators Who is using compression, at what stages of design-mfg flow? Is there synergy between manufacturing

flow and GDSII-OASIS-UDM?

TYPE 1 TYPE 2

TYPE 3

equivalent to “GDSII AREF”

TYPE 4

TYPE 5

TYPE 6

TYPE 7

TYPE 8

Other OASIS repetition types

OASIS Format (recent SEMI standard) defines eight repetition types.

A repetition represents an “array” of (polygon) records, enabling compression of layout data.

EE14157

#11: Leakage Management#11: Leakage Management Huge parametric yield loss Subthreshold leakage current varies exponentially

with threshold voltage: I exp(-Vth)

Vth = f(channel length, oxide thickness, doping)

Most affected by variations in gate length

±10% Ld

±100% Isub

Dennis Sylvester, U. Michigan

EE14158

Leakage: Understanding + ControlLeakage: Understanding + Control

Understanding: variation in chip-level leakage due to Leff

variation cost-benefit of controlling

relevant variation sources

Control: Multi-everything (threshold, supply, sizing)

New control: can use selective Lgate bias (~2 nm) to reduce leakage by 60% with no loss in critical path delay

EE14159

ConclusionsConclusions Designer, EDA, and mask communities must co-

evolve to maintain the cost (value) trajectory of Moore’s Law

Basic goal: bidirectional design-mfg data pipe Drivers: cost, value Pass functional intent to mask and foundry flows Pass limits of mask and foundry flows up to design

Several examples given Manufacturability and cost/value optimization Leakage power Restricted layout Intelligent mask data preparation Analog rules

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