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EE121 John Wakerly Lecture #14

Read-only memories (review)

Static read/write memories

Dynamic read/write memories

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Read-Only Memories

• Program storage– Boot ROM for personal computers– Complete application storage for embedded systems.

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Two-dimensional decoding

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Larger example, 32Kx8 ROM

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Typical commercial EEPROMs

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Microprocessor EPROM application

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ROM control and I/O signals

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ROM timing

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Read/Write Memories

• a.k.a. “RAM” (Random Access Memory)• Volatility

– Most RAMs lose their memory when power is removed

– NVRAM = RAM + battery– Or use EEPROM

• SRAM (Static RAM)– Memory behaves like latches or flip-flops

• DRAM (Dynamic Memory)– Memory lasts only for a few milliseconds– Must “refresh” locations by reading or writing

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SRAM

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SRAM operation

• Individual bits are D latches, not edge-triggered D flip-flops.– Fewer transistors per cell.

• Implications for write operations:– Address must be stable before writing cell.– Data must be stable before ending a write.

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SRAM array

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SRAM control lines

• Chip select• Output enable• Write enable

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SRAM read timing

• Similar to ROM read timing

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SRAM write timing

• Address must be stable before and after write-enable is asserted.

• Data is latched on trailing edge of (WE & CS).

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Bidirectional data in and out pins

• Use the same data pins for reads and writes– Especially common on wide devices– Makes sense when used with microprocessor

buses (also bidirectional)

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SRAM devices

• Similar to ROM packages

28-pin DIPs 32-pin DIPs

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Synchronous SRAMs

• Use latch-type SRAM cells internally

• Put registers in front of address and control (and maybe data) for easier interfacing with synchronous systems at high speeds

• E.g., Pentium cache RAMs

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DRAM (Dynamic RAMs)

• SRAMs typically use six transistors per bit of storage.

• DRAMs use only onetransistor per bit:

• 1/0 = capacitorcharged/discharged

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DRAM read operations

– Precharge bit line to VDD/2.

– Take the word line HIGH.– Detect whether current flows into or out of the cell.– Note: cell contents are destroyed by the read!– Must write the bit value back after reading.

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DRAM write operations

– Take the word line HIGH.– Set the bit line LOW or HIGH to store 0 or 1.– Take the word line LOW.

– Note: The stored charge for a 1 will eventually leak off.

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DRAM charge leakage

• Typical devices require each cell to be refreshed once every 4 to 64 mS.

• During “suspended” operation, notebook computers use power mainly for DRAM refresh.

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DRAM-chip internal organization

64K x 1DRAM

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RAS/CAS operation

• Row Address Strobe, Column Address Strobe– n address bits are provided in two steps using n/2

pins, referenced to the falling edges of RAS_L and CAS_L

– Traditional method of DRAM operation for 20 years.– Now being supplanted by synchronous, clocked

interfaces in SDRAM (synchronous DRAM).

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DRAM read timing

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DRAM refresh timing

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DRAM write timing

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Next Time

• CPLDs• FPGAs