Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra...

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Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis
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Transcript of Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra...

Page 1: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Modified from John Wakerly Lecture #2 and #3

CMOS gates at the transistor level

Boolean algebraCombinational-circuit analysis

Page 2: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

CMOS NAND Gates

• Use 2n transistors for n-input gate

Page 3: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

• CMOS NAND -- switch model

Page 4: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

• CMOS NAND -- more inputs (3)

Page 5: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

• Inherent inversion. • Non-inverting buffer:

Page 6: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

• 2-input AND gate:

Page 7: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

CMOS NOR Gates

• Like NAND -- 2n transistors for n-input gate

Page 8: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

NAND vs. NOR

• For a given silicon area, PMOS transistors are “weaker” than NMOS transistors.

NAND NOR

• Result: NAND gates are preferred in CMOS.

Page 9: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Boolean algebra

• a.k.a. “switching algebra”– deals with boolean values -- 0, 1

• Positive-logic convention– analog voltages LOW, HIGH --> 0, 1

• Negative logic -- seldom used• Signal values denoted by variables

(X, Y, FRED, etc.)

Page 10: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Boolean operators

• Complement: X (opposite of X)• AND: X Y• OR: X + Y

• Axiomatic definition: A1-A5, A1-A5

binary operators, describedfunctionally by truth table.

Page 11: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

More definitions

• Literal: a variable or its complement– X, X, FRED, CS_L

• Expression: literals combined by AND, OR, parentheses, complementation– X+Y– P Q R– A + B C– ((FRED Z) + CS_L A B C + Q5) RESET

• Equation: Variable = expression– P = ((FRED Z) + CS_L A B C + Q5)

RESET

Page 12: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Logic symbols

Page 13: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Theorems

• Proofs by perfect induction

Page 14: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

More Theorems

• N.B. T8, T10, T11

Page 15: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Duality

• Swap 0 & 1, AND & OR– Result: Theorems still true

• Why?– Each axiom (A1-A5) has a dual (A1-A5

• Counterexample:X + X Y = X (T9)X X + Y = X (dual)X + Y = X (T3)????????????

X + (X Y) = X (T9)X (X + Y) = X (dual)(X X) + (X Y) = X (T8)X + (X Y) = X (T3)parentheses,operator precedence!

Page 16: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

N-variable Theorems

• Prove using finite induction• Most important: DeMorgan theorems

Page 17: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

DeMorgan Symbol Equivalence

Page 18: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Likewise for OR

• (be sure to check errata!)

Page 19: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

DeMorgan Symbols

Page 20: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Even more definitions (Sec. 4.1.6)

• Product term • Sum-of-products expression• Sum term• Product-of-sums expression• Normal term• Minterm (n variables)• Maxterm (n variables)

Page 21: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Truth table vs. minterms & maxterms

Page 22: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Combinational analysis

Page 23: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Signal expressions

• Multiply out:

F = ((X + Y) Z) + (X Y Z)

= (X Z) + (Y Z) + (X Y Z)

Page 24: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

New circuit, same function

Page 25: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

“Add out” logic function

• Circuit:

Page 26: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Shortcut: Symbol substitution

Page 27: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Different circuit, same function

Page 28: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Another example

Page 29: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Short Review of Exor Logic

• A A = 0 • A A’ = 1 • A 1=A’ • A’ 1=A • A 0=A • A B= B A • A B = B A

• A(B C) = AB AC• A+B = A B AB• A+B = A B when AB = 0 • A (B C) = (A B) C• (A B) C = A (B C)• A+B = A B AB =

A B(1 A) = A BA’

These rules are sufficient to minimize Exclusive Sum of Product expression for small number of variables

We will use these rules in the class for all kinds of reversible, quantum, optical, etc. logic. Try to remember them or put them to your “creepsheet”.

Page 30: Modified from John Wakerly Lecture #2 and #3 CMOS gates at the transistor level Boolean algebra Combinational-circuit analysis.

Challenge Problems for ambitious students• Problem 1.Problem 1. Express

function AB+CD+A’C using only EXORs and AND gates

• Problem 2Problem 2. Prove that

A+B = A B AB• Problem 3Problem 3 . Prove that A+B = A

B when AB = 0

Problem 4. Given are three functions of three inputs:

A = NOT(a), B = NOT(b), C = NOT(c).

You have only two inverters. You can have an arbitrary large set of two-input AND and OR gates.

Realize these three functions with the gates that you have at your disposal. You cannot use other gates. You can use only two inverters. Draw the schematic of the solution