EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate...
Transcript of EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate...
![Page 1: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/1.jpg)
EE101: JFET operation and characteristics
M. B. [email protected]
www.ee.iitb.ac.in/~sequel
Department of Electrical EngineeringIndian Institute of Technology Bombay
M. B. Patil, IIT Bombay
![Page 2: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/2.jpg)
Field-effect transistors
DrainSource
Gate
* A Field-Effect Transistor (FET) has a gate (G) terminal which controls thecurrent flow between the other two terminals, viz., source (S) and drain (D).
* In simple terms, a FET can be thought of as a resistance connected between Sand D, which is a function of the gate voltage VG .
* The mechanism of gate control varies in different types of FETs, e.g., JFET,MESFET, MOSFET, HEMT.
* FETs can be used for analog and digital applications. In each case, the fact thatthe gate is used to control current flow between S and D plays a crucial role.
M. B. Patil, IIT Bombay
![Page 3: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/3.jpg)
Field-effect transistors
DrainSource
Gate
* A Field-Effect Transistor (FET) has a gate (G) terminal which controls thecurrent flow between the other two terminals, viz., source (S) and drain (D).
* In simple terms, a FET can be thought of as a resistance connected between Sand D, which is a function of the gate voltage VG .
* The mechanism of gate control varies in different types of FETs, e.g., JFET,MESFET, MOSFET, HEMT.
* FETs can be used for analog and digital applications. In each case, the fact thatthe gate is used to control current flow between S and D plays a crucial role.
M. B. Patil, IIT Bombay
![Page 4: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/4.jpg)
Field-effect transistors
DrainSource
Gate
* A Field-Effect Transistor (FET) has a gate (G) terminal which controls thecurrent flow between the other two terminals, viz., source (S) and drain (D).
* In simple terms, a FET can be thought of as a resistance connected between Sand D, which is a function of the gate voltage VG .
* The mechanism of gate control varies in different types of FETs, e.g., JFET,MESFET, MOSFET, HEMT.
* FETs can be used for analog and digital applications. In each case, the fact thatthe gate is used to control current flow between S and D plays a crucial role.
M. B. Patil, IIT Bombay
![Page 5: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/5.jpg)
Field-effect transistors
DrainSource
Gate
* A Field-Effect Transistor (FET) has a gate (G) terminal which controls thecurrent flow between the other two terminals, viz., source (S) and drain (D).
* In simple terms, a FET can be thought of as a resistance connected between Sand D, which is a function of the gate voltage VG .
* The mechanism of gate control varies in different types of FETs, e.g., JFET,MESFET, MOSFET, HEMT.
* FETs can be used for analog and digital applications. In each case, the fact thatthe gate is used to control current flow between S and D plays a crucial role.
M. B. Patil, IIT Bombay
![Page 6: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/6.jpg)
Field-effect transistors
DrainSource
Gate
* A Field-Effect Transistor (FET) has a gate (G) terminal which controls thecurrent flow between the other two terminals, viz., source (S) and drain (D).
* In simple terms, a FET can be thought of as a resistance connected between Sand D, which is a function of the gate voltage VG .
* The mechanism of gate control varies in different types of FETs, e.g., JFET,MESFET, MOSFET, HEMT.
* FETs can be used for analog and digital applications. In each case, the fact thatthe gate is used to control current flow between S and D plays a crucial role.
M. B. Patil, IIT Bombay
![Page 7: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/7.jpg)
Junction Field-effect transistors (JFET)
G
G
S D
Cross−sectional view
S D
G
G
Simplified structure
Source Drain
Gate
3D view
L
2an− Si
p+
(Not drawn to scale. Typically, L≫ 2a.)
L
2an− Si
p+Z
L′
* The n-type region between the top and bottom p+ regions offers a resistance tocurrent flow. The resistance depends on VG .
* We will first consider the case, VD = VS = 0 V .
M. B. Patil, IIT Bombay
![Page 8: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/8.jpg)
Junction Field-effect transistors (JFET)
G
G
S D
Cross−sectional view
S D
G
G
Simplified structure
Source Drain
Gate
3D view
L
2an− Si
p+
(Not drawn to scale. Typically, L≫ 2a.)
L
2an− Si
p+Z
L′
* The n-type region between the top and bottom p+ regions offers a resistance tocurrent flow. The resistance depends on VG .
* We will first consider the case, VD = VS = 0 V .
M. B. Patil, IIT Bombay
![Page 9: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/9.jpg)
Junction Field-effect transistors (JFET)
G
G
S D
Cross−sectional view
S D
G
G
Simplified structure
Source Drain
Gate
3D view
L
2an− Si
p+
(Not drawn to scale. Typically, L≫ 2a.)
L
2an− Si
p+Z
L′
* The n-type region between the top and bottom p+ regions offers a resistance tocurrent flow. The resistance depends on VG .
* We will first consider the case, VD = VS = 0 V .
M. B. Patil, IIT Bombay
![Page 10: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/10.jpg)
JFET with VS = VD = 0 V
G
G
DS
G
G
DS
depletedneutral
G
G
DS
0 V 0 V
VG =−2 V
L
0 V 0 V
VG =0 V
a hW
p+
0 V 0 V
VG =−1 V
* The bias across the p-n junction is (VG − VS ), i.e., VG , since VS = VD = 0 V .
* As the reverse bias across the junction is increased (by making VG morenegative), the depletion region widens, and the resistance offered by the n-regionincreases.
* When the reverse bias becomes large enough, the depletion region consumes theentire n-region. The corresponding VG is called the “pinch-off” voltage.
M. B. Patil, IIT Bombay
![Page 11: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/11.jpg)
JFET with VS = VD = 0 V
G
G
DS
G
G
DS
depletedneutral
G
G
DS
0 V 0 V
VG =−2 V
L
0 V 0 V
VG =0 V
a hW
p+
0 V 0 V
VG =−1 V
* The bias across the p-n junction is (VG − VS ), i.e., VG , since VS = VD = 0 V .
* As the reverse bias across the junction is increased (by making VG morenegative), the depletion region widens, and the resistance offered by the n-regionincreases.
* When the reverse bias becomes large enough, the depletion region consumes theentire n-region. The corresponding VG is called the “pinch-off” voltage.
M. B. Patil, IIT Bombay
![Page 12: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/12.jpg)
JFET with VS = VD = 0 V
G
G
DS
G
G
DS
depletedneutral
G
G
DS
0 V 0 V
VG =−2 V
L
0 V 0 V
VG =0 V
a hW
p+
0 V 0 V
VG =−1 V
* The bias across the p-n junction is (VG − VS ), i.e., VG , since VS = VD = 0 V .
* As the reverse bias across the junction is increased (by making VG morenegative), the depletion region widens, and the resistance offered by the n-regionincreases.
* When the reverse bias becomes large enough, the depletion region consumes theentire n-region. The corresponding VG is called the “pinch-off” voltage.
M. B. Patil, IIT Bombay
![Page 13: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/13.jpg)
JFET with VS = VD = 0 V
G
G
DS
G
G
DS
depletedneutral
G
G
DS
0 V 0 V
VG =−2 V
L
0 V 0 V
VG =0 V
a hW
p+
0 V 0 V
VG =−1 V
* The bias across the p-n junction is (VG − VS ), i.e., VG , since VS = VD = 0 V .
* As the reverse bias across the junction is increased (by making VG morenegative), the depletion region widens, and the resistance offered by the n-regionincreases.
* When the reverse bias becomes large enough, the depletion region consumes theentire n-region. The corresponding VG is called the “pinch-off” voltage.
M. B. Patil, IIT Bombay
![Page 14: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/14.jpg)
JFET: pinch-off voltage
G
G
DS
depletedneutral
p+
0 V 0 V
W
ha
* VP = VG for which h = 0, i.e., W = a.
* For a p+-n junction, W =
s2 ε (Vbi − V )
q Nd, where Vbi is the built-in potential of
the junction.
* For pinch-off, W = a =
s2 ε (Vbi − V )
q Nd
⇒ VP = Vbi −q Nd a2
2 ε.
M. B. Patil, IIT Bombay
![Page 15: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/15.jpg)
JFET: pinch-off voltage
G
G
DS
depletedneutral
p+
0 V 0 V
W
ha
* VP = VG for which h = 0, i.e., W = a.
* For a p+-n junction, W =
s2 ε (Vbi − V )
q Nd, where Vbi is the built-in potential of
the junction.
* For pinch-off, W = a =
s2 ε (Vbi − V )
q Nd
⇒ VP = Vbi −q Nd a2
2 ε.
M. B. Patil, IIT Bombay
![Page 16: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/16.jpg)
JFET: pinch-off voltage
G
G
DS
depletedneutral
p+
0 V 0 V
W
ha
* VP = VG for which h = 0, i.e., W = a.
* For a p+-n junction, W =
s2 ε (Vbi − V )
q Nd, where Vbi is the built-in potential of
the junction.
* For pinch-off, W = a =
s2 ε (Vbi − V )
q Nd
⇒ VP = Vbi −q Nd a2
2 ε.
M. B. Patil, IIT Bombay
![Page 17: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/17.jpg)
JFET: pinch-off voltage
G
G
DS
depletedneutral
p+
0 V 0 V
W
ha
* VP = VG for which h = 0, i.e., W = a.
* For a p+-n junction, W =
s2 ε (Vbi − V )
q Nd, where Vbi is the built-in potential of
the junction.
* For pinch-off, W = a =
s2 ε (Vbi − V )
q Nd
⇒ VP = Vbi −q Nd a2
2 ε.
M. B. Patil, IIT Bombay
![Page 18: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/18.jpg)
JFET: pinch-off voltage
G
G
DS
depletedneutral
p+
0 V 0 V
W
ha
* For pinch-off, W = a =
s2 ε (Vbi − V )
q Nd⇒ VP = Vbi −
q Nd a2
2 ε.
* Example: Nd = 2× 1015 cm−3, a = 1.5µm, Vbi = 0.8 V .
W = 0.8− (1.6× 10−19 Coul)(2× 1015 cm−3)((1.5× 10−4)2 cm2)
2× 11.7× 8.85× 10−14 F/cm
= 0.8− 3.48 ≈ −2.7 V .
⇒ If a gate voltage VG =−2.7 V is applied, the n-channel gets pinched off, andthe device resistance becomes very large.
M. B. Patil, IIT Bombay
![Page 19: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/19.jpg)
JFET: pinch-off voltage
G
G
DS
depletedneutral
p+
0 V 0 V
W
ha
* For pinch-off, W = a =
s2 ε (Vbi − V )
q Nd⇒ VP = Vbi −
q Nd a2
2 ε.
* Example: Nd = 2× 1015 cm−3, a = 1.5µm, Vbi = 0.8 V .
W = 0.8− (1.6× 10−19 Coul)(2× 1015 cm−3)((1.5× 10−4)2 cm2)
2× 11.7× 8.85× 10−14 F/cm
= 0.8− 3.48 ≈ −2.7 V .
⇒ If a gate voltage VG =−2.7 V is applied, the n-channel gets pinched off, andthe device resistance becomes very large.
M. B. Patil, IIT Bombay
![Page 20: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/20.jpg)
JFET: pinch-off voltage
G
G
DS
depletedneutral
p+
0 V 0 V
W
ha
* For pinch-off, W = a =
s2 ε (Vbi − V )
q Nd⇒ VP = Vbi −
q Nd a2
2 ε.
* Example: Nd = 2× 1015 cm−3, a = 1.5µm, Vbi = 0.8 V .
W = 0.8− (1.6× 10−19 Coul)(2× 1015 cm−3)((1.5× 10−4)2 cm2)
2× 11.7× 8.85× 10−14 F/cm
= 0.8− 3.48 ≈ −2.7 V .
⇒ If a gate voltage VG =−2.7 V is applied, the n-channel gets pinched off, andthe device resistance becomes very large.
M. B. Patil, IIT Bombay
![Page 21: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/21.jpg)
JFET: pinch-off voltage
G
G
DS
depletedneutral
p+
0 V 0 V
W
ha
* For pinch-off, W = a =
s2 ε (Vbi − V )
q Nd⇒ VP = Vbi −
q Nd a2
2 ε.
* Example: Nd = 2× 1015 cm−3, a = 1.5µm, Vbi = 0.8 V .
W = 0.8− (1.6× 10−19 Coul)(2× 1015 cm−3)((1.5× 10−4)2 cm2)
2× 11.7× 8.85× 10−14 F/cm
= 0.8− 3.48 ≈ −2.7 V .
⇒ If a gate voltage VG =−2.7 V is applied, the n-channel gets pinched off, andthe device resistance becomes very large.
M. B. Patil, IIT Bombay
![Page 22: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/22.jpg)
JFET: pinch-off voltage
G
G
DS
depletedneutral
p+
0 V 0 V
W
ha
* For pinch-off, W = a =
s2 ε (Vbi − V )
q Nd⇒ VP = Vbi −
q Nd a2
2 ε.
* Example: Nd = 2× 1015 cm−3, a = 1.5µm, Vbi = 0.8 V .
W = 0.8− (1.6× 10−19 Coul)(2× 1015 cm−3)((1.5× 10−4)2 cm2)
2× 11.7× 8.85× 10−14 F/cm
= 0.8− 3.48 ≈ −2.7 V .
⇒ If a gate voltage VG =−2.7 V is applied, the n-channel gets pinched off, andthe device resistance becomes very large.
M. B. Patil, IIT Bombay
![Page 23: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/23.jpg)
JFET with VG = constant, VD 6= 0 V
G
G
DS
depletedneutral
G
G
DS
G
G
DS
p+
L
0 V
a hW
VD =0 Vx
0 V 0 V
VD =1 VVD =0.05 VV (x)
W
ha
0 V
1 V
* Consider an n-JFET with VG constant (and not in pinch-off mode).If a positive VD is applied, the potential V (x) inside the channel from S to D(along the dashed line) increases from 0 V to VD .Note that W and h are now functions of x such that, W (x) + h(x) = a.
* Since the p-n junction bias at a given x is (VG − V (x)), the drain end of thechannel has a larger reverse bias than the source end.⇒ the depletion region is wider at the drain.
M. B. Patil, IIT Bombay
![Page 24: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/24.jpg)
JFET with VG = constant, VD 6= 0 V
G
G
DS
depletedneutral
G
G
DS
G
G
DS
p+
L
0 V
a hW
VD =0 Vx
0 V 0 V
VD =1 VVD =0.05 VV (x)
W
ha
0 V
1 V
* Consider an n-JFET with VG constant (and not in pinch-off mode).
If a positive VD is applied, the potential V (x) inside the channel from S to D(along the dashed line) increases from 0 V to VD .Note that W and h are now functions of x such that, W (x) + h(x) = a.
* Since the p-n junction bias at a given x is (VG − V (x)), the drain end of thechannel has a larger reverse bias than the source end.⇒ the depletion region is wider at the drain.
M. B. Patil, IIT Bombay
![Page 25: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/25.jpg)
JFET with VG = constant, VD 6= 0 V
G
G
DS
depletedneutral
G
G
DS
G
G
DS
p+
L
0 V
a hW
VD =0 Vx
0 V 0 V
VD =1 VVD =0.05 VV (x)
W
ha
0 V
1 V
* Consider an n-JFET with VG constant (and not in pinch-off mode).If a positive VD is applied, the potential V (x) inside the channel from S to D(along the dashed line) increases from 0 V to VD .
Note that W and h are now functions of x such that, W (x) + h(x) = a.
* Since the p-n junction bias at a given x is (VG − V (x)), the drain end of thechannel has a larger reverse bias than the source end.⇒ the depletion region is wider at the drain.
M. B. Patil, IIT Bombay
![Page 26: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/26.jpg)
JFET with VG = constant, VD 6= 0 V
G
G
DS
depletedneutral
G
G
DS
G
G
DS
p+
L
0 V
a hW
VD =0 Vx
0 V 0 V
VD =1 VVD =0.05 VV (x)
W
ha
0 V
1 V
* Consider an n-JFET with VG constant (and not in pinch-off mode).If a positive VD is applied, the potential V (x) inside the channel from S to D(along the dashed line) increases from 0 V to VD .Note that W and h are now functions of x such that, W (x) + h(x) = a.
* Since the p-n junction bias at a given x is (VG − V (x)), the drain end of thechannel has a larger reverse bias than the source end.⇒ the depletion region is wider at the drain.
M. B. Patil, IIT Bombay
![Page 27: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/27.jpg)
JFET with VG = constant, VD 6= 0 V
G
G
DS
depletedneutral
G
G
DS
G
G
DS
p+
L
0 V
a hW
VD =0 Vx
0 V 0 V
VD =1 VVD =0.05 VV (x)
W
ha
0 V
1 V
* Consider an n-JFET with VG constant (and not in pinch-off mode).If a positive VD is applied, the potential V (x) inside the channel from S to D(along the dashed line) increases from 0 V to VD .Note that W and h are now functions of x such that, W (x) + h(x) = a.
* Since the p-n junction bias at a given x is (VG − V (x)), the drain end of thechannel has a larger reverse bias than the source end.
⇒ the depletion region is wider at the drain.
M. B. Patil, IIT Bombay
![Page 28: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/28.jpg)
JFET with VG = constant, VD 6= 0 V
G
G
DS
depletedneutral
G
G
DS
G
G
DS
p+
L
0 V
a hW
VD =0 Vx
0 V 0 V
VD =1 VVD =0.05 VV (x)
W
ha
0 V
1 V
* Consider an n-JFET with VG constant (and not in pinch-off mode).If a positive VD is applied, the potential V (x) inside the channel from S to D(along the dashed line) increases from 0 V to VD .Note that W and h are now functions of x such that, W (x) + h(x) = a.
* Since the p-n junction bias at a given x is (VG − V (x)), the drain end of thechannel has a larger reverse bias than the source end.⇒ the depletion region is wider at the drain.
M. B. Patil, IIT Bombay
![Page 29: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/29.jpg)
JFET: derivation of ID equation
G
G
DS a
0 V
W
h
0 V
Area =2 h Z
2 h
Z
x
y
V
x
VD
L
Consider a slice of the device. The current density at any point in the neutral region is assumed tobe in the x direction, and given by,
Jn = qµnnE + qDndn
dx≈ qµnnE = qµnNd
dV
dx,
where we have neglected the diffusion current, since n ≈ Nd ⇒dn
dx= 0.
Note that only the neutral part of the n-Si conducts since there are no carriers in the depletionregions.
At a given x, the current ID is obtained by integrating Jn over the area of the neutral channelregion (see figure on the right). Since Jn is constant over this area,
ID (x) =
Z ZJndx dz = 2hZ ×
„qµnNd
dV
dx
«= 2qZµnNda
dV
dx
„1−
W
a
«,
where we have used h = a −W , i.e., h = a(1−W/a).
M. B. Patil, IIT Bombay
![Page 30: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/30.jpg)
JFET: derivation of ID equation
G
G
DS a
0 V
W
h
0 V
Area =2 h Z
2 h
Z
x
y
V
x
VD
L
Consider a slice of the device. The current density at any point in the neutral region is assumed tobe in the x direction, and given by,
Jn = qµnnE + qDndn
dx≈ qµnnE = qµnNd
dV
dx,
where we have neglected the diffusion current, since n ≈ Nd ⇒dn
dx= 0.
Note that only the neutral part of the n-Si conducts since there are no carriers in the depletionregions.
At a given x, the current ID is obtained by integrating Jn over the area of the neutral channelregion (see figure on the right). Since Jn is constant over this area,
ID (x) =
Z ZJndx dz = 2hZ ×
„qµnNd
dV
dx
«= 2qZµnNda
dV
dx
„1−
W
a
«,
where we have used h = a −W , i.e., h = a(1−W/a).
M. B. Patil, IIT Bombay
![Page 31: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/31.jpg)
JFET: derivation of ID equation
G
G
DS a
0 V
W
h
0 V
Area =2 h Z
2 h
Z
x
y
V
x
VD
L
Consider a slice of the device. The current density at any point in the neutral region is assumed tobe in the x direction, and given by,
Jn = qµnnE + qDndn
dx≈ qµnnE = qµnNd
dV
dx,
where we have neglected the diffusion current, since n ≈ Nd ⇒dn
dx= 0.
Note that only the neutral part of the n-Si conducts since there are no carriers in the depletionregions.
At a given x, the current ID is obtained by integrating Jn over the area of the neutral channelregion (see figure on the right). Since Jn is constant over this area,
ID (x) =
Z ZJndx dz = 2hZ ×
„qµnNd
dV
dx
«= 2qZµnNda
dV
dx
„1−
W
a
«,
where we have used h = a −W , i.e., h = a(1−W/a).
M. B. Patil, IIT Bombay
![Page 32: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/32.jpg)
JFET: derivation of ID equation
G
G
DS a
0 V
W
h
0 V
Area =2 h Z
2 h
Z
x
y
V
x
VD
L
Consider a slice of the device. The current density at any point in the neutral region is assumed tobe in the x direction, and given by,
Jn = qµnnE + qDndn
dx≈ qµnnE = qµnNd
dV
dx,
where we have neglected the diffusion current, since n ≈ Nd ⇒dn
dx= 0.
Note that only the neutral part of the n-Si conducts since there are no carriers in the depletionregions.
At a given x, the current ID is obtained by integrating Jn over the area of the neutral channelregion (see figure on the right). Since Jn is constant over this area,
ID (x) =
Z ZJndx dz = 2hZ ×
„qµnNd
dV
dx
«= 2qZµnNda
dV
dx
„1−
W
a
«,
where we have used h = a −W , i.e., h = a(1−W/a).
M. B. Patil, IIT Bombay
![Page 33: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/33.jpg)
JFET: derivation of ID equation
G
G
DS a
0 V
W
h
0 V
Area =2 h Z
2 h
Z
x
y
V
x
VD
L
Consider a slice of the device. The current density at any point in the neutral region is assumed tobe in the x direction, and given by,
Jn = qµnnE + qDndn
dx≈ qµnnE = qµnNd
dV
dx,
where we have neglected the diffusion current, since n ≈ Nd ⇒dn
dx= 0.
Note that only the neutral part of the n-Si conducts since there are no carriers in the depletionregions.
At a given x, the current ID is obtained by integrating Jn over the area of the neutral channelregion (see figure on the right). Since Jn is constant over this area,
ID (x) =
Z ZJndx dz = 2hZ ×
„qµnNd
dV
dx
«= 2qZµnNda
dV
dx
„1−
W
a
«,
where we have used h = a −W , i.e., h = a(1−W/a).
M. B. Patil, IIT Bombay
![Page 34: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/34.jpg)
JFET: derivation of ID equation
G
G
DS a
0 V
W
h
0 V
Area =2 h Z
2 h
Z
x
y
V
x
VD
L
Consider a slice of the device. The current density at any point in the neutral region is assumed tobe in the x direction, and given by,
Jn = qµnnE + qDndn
dx≈ qµnnE = qµnNd
dV
dx,
where we have neglected the diffusion current, since n ≈ Nd ⇒dn
dx= 0.
Note that only the neutral part of the n-Si conducts since there are no carriers in the depletionregions.
At a given x, the current ID is obtained by integrating Jn over the area of the neutral channelregion (see figure on the right). Since Jn is constant over this area,
ID (x) =
Z ZJndx dz = 2hZ ×
„qµnNd
dV
dx
«= 2qZµnNda
dV
dx
„1−
W
a
«,
where we have used h = a −W , i.e., h = a(1−W/a).
M. B. Patil, IIT Bombay
![Page 35: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/35.jpg)
JFET: derivation of ID equation
G
G
DS a
0 V
W
h
x
y
ID (x) = 2 q Z µn Nd adV
dx
„1−
W
a
«.
Since ID (x) is constant from x = 0 to x = L, we get,Z L
0
IDdx = IDL = 2qZµnNda
Z VD
0
1−
s2ε
qNda2
qVbi − (VG − V )
!dV ,
where we have used, for the depletion width W ,
W (x) =
s2ε
qNd
[Vbi − (VG − V )] .
Evaluating the integral and using Vbi − VP =qNda2
2ε, we get (do this!)
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
,
where G0 = 2qZµnNda/L.
Note that G0 is the channel conductance if there was no depletion, i.e., if h(x) = a throughout the
channel.
M. B. Patil, IIT Bombay
![Page 36: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/36.jpg)
JFET: derivation of ID equation
G
G
DS a
0 V
W
h
x
y
ID (x) = 2 q Z µn Nd adV
dx
„1−
W
a
«.
Since ID (x) is constant from x = 0 to x = L, we get,Z L
0
IDdx = IDL = 2qZµnNda
Z VD
0
1−
s2ε
qNda2
qVbi − (VG − V )
!dV ,
where we have used, for the depletion width W ,
W (x) =
s2ε
qNd
[Vbi − (VG − V )] .
Evaluating the integral and using Vbi − VP =qNda2
2ε, we get (do this!)
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
,
where G0 = 2qZµnNda/L.
Note that G0 is the channel conductance if there was no depletion, i.e., if h(x) = a throughout the
channel.
M. B. Patil, IIT Bombay
![Page 37: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/37.jpg)
JFET: derivation of ID equation
G
G
DS a
0 V
W
h
x
y
ID (x) = 2 q Z µn Nd adV
dx
„1−
W
a
«.
Since ID (x) is constant from x = 0 to x = L, we get,Z L
0
IDdx = IDL = 2qZµnNda
Z VD
0
1−
s2ε
qNda2
qVbi − (VG − V )
!dV ,
where we have used, for the depletion width W ,
W (x) =
s2ε
qNd
[Vbi − (VG − V )] .
Evaluating the integral and using Vbi − VP =qNda2
2ε, we get (do this!)
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
,
where G0 = 2qZµnNda/L.
Note that G0 is the channel conductance if there was no depletion, i.e., if h(x) = a throughout the
channel.
M. B. Patil, IIT Bombay
![Page 38: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/38.jpg)
JFET: derivation of ID equation
G
G
DS a
0 V
W
h
x
y
ID (x) = 2 q Z µn Nd adV
dx
„1−
W
a
«.
Since ID (x) is constant from x = 0 to x = L, we get,Z L
0
IDdx = IDL = 2qZµnNda
Z VD
0
1−
s2ε
qNda2
qVbi − (VG − V )
!dV ,
where we have used, for the depletion width W ,
W (x) =
s2ε
qNd
[Vbi − (VG − V )] .
Evaluating the integral and using Vbi − VP =qNda2
2ε, we get (do this!)
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
,
where G0 = 2qZµnNda/L.
Note that G0 is the channel conductance if there was no depletion, i.e., if h(x) = a throughout the
channel.
M. B. Patil, IIT Bombay
![Page 39: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/39.jpg)
Special case: VD ≈ 0 V
G
G
DS
G
G
DS
depletedneutral
a
0 V
W
h
x
y p+
L
0 V
a hW
VD≈ 0 V
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
≈ G0
VD −
2
3(Vbi − VP )−1/2
»3
2VD (Vbi − VG )1/2
–ff(using Taylor’s series)
= G0VD
(1−
„Vbi − VG
Vbi − VP
«1/2)
.
Since W =2ε
qNd
(Vbi − VG )1/2, and a =2ε
qNd
(Vbi − VP )1/2, we get
ID = G0VD
1−
W
a
ff.
This simply shows that the channel conductance reduces linearly with W (as seen before the
VS = VS = 0 V condition), and for VG = VP (i.e., W = a), the conductance becomes zero.
M. B. Patil, IIT Bombay
![Page 40: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/40.jpg)
Special case: VD ≈ 0 V
G
G
DS
G
G
DS
depletedneutral
a
0 V
W
h
x
y p+
L
0 V
a hW
VD≈ 0 V
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
≈ G0
VD −
2
3(Vbi − VP )−1/2
»3
2VD (Vbi − VG )1/2
–ff(using Taylor’s series)
= G0VD
(1−
„Vbi − VG
Vbi − VP
«1/2)
.
Since W =2ε
qNd
(Vbi − VG )1/2, and a =2ε
qNd
(Vbi − VP )1/2, we get
ID = G0VD
1−
W
a
ff.
This simply shows that the channel conductance reduces linearly with W (as seen before the
VS = VS = 0 V condition), and for VG = VP (i.e., W = a), the conductance becomes zero.
M. B. Patil, IIT Bombay
![Page 41: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/41.jpg)
Special case: VD ≈ 0 V
G
G
DS
G
G
DS
depletedneutral
a
0 V
W
h
x
y p+
L
0 V
a hW
VD≈ 0 V
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
≈ G0
VD −
2
3(Vbi − VP )−1/2
»3
2VD (Vbi − VG )1/2
–ff(using Taylor’s series)
= G0VD
(1−
„Vbi − VG
Vbi − VP
«1/2)
.
Since W =2ε
qNd
(Vbi − VG )1/2, and a =2ε
qNd
(Vbi − VP )1/2, we get
ID = G0VD
1−
W
a
ff.
This simply shows that the channel conductance reduces linearly with W (as seen before the
VS = VS = 0 V condition), and for VG = VP (i.e., W = a), the conductance becomes zero.
M. B. Patil, IIT Bombay
![Page 42: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/42.jpg)
Special case: VD ≈ 0 V
G
G
DS
G
G
DS
depletedneutral
a
0 V
W
h
x
y p+
L
0 V
a hW
VD≈ 0 V
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
≈ G0
VD −
2
3(Vbi − VP )−1/2
»3
2VD (Vbi − VG )1/2
–ff(using Taylor’s series)
= G0VD
(1−
„Vbi − VG
Vbi − VP
«1/2)
.
Since W =2ε
qNd
(Vbi − VG )1/2, and a =2ε
qNd
(Vbi − VP )1/2, we get
ID = G0VD
1−
W
a
ff.
This simply shows that the channel conductance reduces linearly with W (as seen before the
VS = VS = 0 V condition), and for VG = VP (i.e., W = a), the conductance becomes zero.
M. B. Patil, IIT Bombay
![Page 43: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/43.jpg)
Special case: VD ≈ 0 V
G
G
DS
G
G
DS
depletedneutral
a
0 V
W
h
x
y p+
L
0 V
a hW
VD≈ 0 V
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
≈ G0
VD −
2
3(Vbi − VP )−1/2
»3
2VD (Vbi − VG )1/2
–ff(using Taylor’s series)
= G0VD
(1−
„Vbi − VG
Vbi − VP
«1/2)
.
Since W =2ε
qNd
(Vbi − VG )1/2, and a =2ε
qNd
(Vbi − VP )1/2, we get
ID = G0VD
1−
W
a
ff.
This simply shows that the channel conductance reduces linearly with W (as seen before the
VS = VS = 0 V condition), and for VG = VP (i.e., W = a), the conductance becomes zero.
M. B. Patil, IIT Bombay
![Page 44: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/44.jpg)
Special case: VD ≈ 0 V
G
G
DS
G
G
DS
depletedneutral
a
0 V
W
h
x
y p+
L
0 V
a hW
VD≈ 0 V
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
≈ G0
VD −
2
3(Vbi − VP )−1/2
»3
2VD (Vbi − VG )1/2
–ff(using Taylor’s series)
= G0VD
(1−
„Vbi − VG
Vbi − VP
«1/2)
.
Since W =2ε
qNd
(Vbi − VG )1/2, and a =2ε
qNd
(Vbi − VP )1/2, we get
ID = G0VD
1−
W
a
ff.
This simply shows that the channel conductance reduces linearly with W (as seen before the
VS = VS = 0 V condition), and for VG = VP (i.e., W = a), the conductance becomes zero.
M. B. Patil, IIT Bombay
![Page 45: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/45.jpg)
JFET: pinch-off near drain
G
G
DS100
50
0
200
150
1 2 3 4 5 0
a
0 V
W
h
x
y
VD (Volts)
I D(µ
A)
VG =−2 V
VG =−1 V
VG =0 V
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
.
For a given VG , ID reaches a maximum at VD = VG − VP (show this by differentiating the aboveequation).
At this value of VD , the bias across the p-n junction at the drain end is VG − VD = VP .In other words, the drain end of the channel has just reached pinch-off.
G
G
DS
pinch−off0 V
What happens if VD is increased further?
M. B. Patil, IIT Bombay
![Page 46: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/46.jpg)
JFET: pinch-off near drain
G
G
DS100
50
0
200
150
1 2 3 4 5 0
a
0 V
W
h
x
y
VD (Volts)
I D(µ
A)
VG =−2 V
VG =−1 V
VG =0 V
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
.
For a given VG , ID reaches a maximum at VD = VG − VP (show this by differentiating the aboveequation).
At this value of VD , the bias across the p-n junction at the drain end is VG − VD = VP .In other words, the drain end of the channel has just reached pinch-off.
G
G
DS
pinch−off0 V
What happens if VD is increased further?
M. B. Patil, IIT Bombay
![Page 47: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/47.jpg)
JFET: pinch-off near drain
G
G
DS100
50
0
200
150
1 2 3 4 5 0
a
0 V
W
h
x
y
VD (Volts)
I D(µ
A)
VG =−2 V
VG =−1 V
VG =0 V
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
.
For a given VG , ID reaches a maximum at VD = VG − VP (show this by differentiating the aboveequation).
At this value of VD , the bias across the p-n junction at the drain end is VG − VD = VP .
In other words, the drain end of the channel has just reached pinch-off.
G
G
DS
pinch−off0 V
What happens if VD is increased further?
M. B. Patil, IIT Bombay
![Page 48: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/48.jpg)
JFET: pinch-off near drain
G
G
DS100
50
0
200
150
1 2 3 4 5 0
a
0 V
W
h
x
y
VD (Volts)
I D(µ
A)
VG =−2 V
VG =−1 V
VG =0 V
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
.
For a given VG , ID reaches a maximum at VD = VG − VP (show this by differentiating the aboveequation).
At this value of VD , the bias across the p-n junction at the drain end is VG − VD = VP .In other words, the drain end of the channel has just reached pinch-off.
G
G
DS
pinch−off0 V
What happens if VD is increased further?
M. B. Patil, IIT Bombay
![Page 49: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/49.jpg)
JFET: pinch-off near drain
G
G
DS100
50
0
200
150
1 2 3 4 5 0
a
0 V
W
h
x
y
VD (Volts)
I D(µ
A)
VG =−2 V
VG =−1 V
VG =0 V
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
.
For a given VG , ID reaches a maximum at VD = VG − VP (show this by differentiating the aboveequation).
At this value of VD , the bias across the p-n junction at the drain end is VG − VD = VP .In other words, the drain end of the channel has just reached pinch-off.
G
G
DS
pinch−off0 V
What happens if VD is increased further?
M. B. Patil, IIT Bombay
![Page 50: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/50.jpg)
JFET: pinch-off near drain
G
G
DS100
50
0
200
150
1 2 3 4 5 0
a
0 V
W
h
x
y
VD (Volts)
I D(µ
A)
VG =−2 V
VG =−1 V
VG =0 V
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
.
For a given VG , ID reaches a maximum at VD = VG − VP (show this by differentiating the aboveequation).
At this value of VD , the bias across the p-n junction at the drain end is VG − VD = VP .In other words, the drain end of the channel has just reached pinch-off.
G
G
DS
pinch−off0 V
What happens if VD is increased further?
M. B. Patil, IIT Bombay
![Page 51: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/51.jpg)
JFET: saturation
G
G
DS
G
G
DSDD
G
G
S
G
G
S
A B C D
A
B
C D
VD < V satD
0 V
VD = V satD
0 V
VD > V satDVD≈ 0 V
0 V 0 V
VDV sat
D =VG − VP
ID
Consider a fixed VG with VD varying from ∼ 0 V to a value beyond condition C.
In this situation, i.e., VD > V satD , a short high-field region develops near the drain end, and the
“excess” voltage, VD − V satD drops across this region.
Because the high-filed region is confined to a very small distance, the conditions in the device arealmost identical in C and D.
⇒ The current in case D is almost the same as that for case C.
The region VD > V satD is therefore called the “saturation region.”
M. B. Patil, IIT Bombay
![Page 52: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/52.jpg)
JFET: saturation
G
G
DS
G
G
DSDD
G
G
S
G
G
S
A B C D
A
B
C D
VD < V satD
0 V
VD = V satD
0 V
VD > V satDVD≈ 0 V
0 V 0 V
VDV sat
D =VG − VP
ID
Consider a fixed VG with VD varying from ∼ 0 V to a value beyond condition C.
In this situation, i.e., VD > V satD , a short high-field region develops near the drain end, and the
“excess” voltage, VD − V satD drops across this region.
Because the high-filed region is confined to a very small distance, the conditions in the device arealmost identical in C and D.
⇒ The current in case D is almost the same as that for case C.
The region VD > V satD is therefore called the “saturation region.”
M. B. Patil, IIT Bombay
![Page 53: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/53.jpg)
JFET: saturation
G
G
DS
G
G
DSDD
G
G
S
G
G
S
A B C D
A
B
C D
VD < V satD
0 V
VD = V satD
0 V
VD > V satDVD≈ 0 V
0 V 0 V
VDV sat
D =VG − VP
ID
Consider a fixed VG with VD varying from ∼ 0 V to a value beyond condition C.
In this situation, i.e., VD > V satD , a short high-field region develops near the drain end, and the
“excess” voltage, VD − V satD drops across this region.
Because the high-filed region is confined to a very small distance, the conditions in the device arealmost identical in C and D.
⇒ The current in case D is almost the same as that for case C.
The region VD > V satD is therefore called the “saturation region.”
M. B. Patil, IIT Bombay
![Page 54: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/54.jpg)
JFET: saturation
G
G
DS
G
G
DSDD
G
G
S
G
G
S
A B C D
A
B
C D
VD < V satD
0 V
VD = V satD
0 V
VD > V satDVD≈ 0 V
0 V 0 V
VDV sat
D =VG − VP
ID
Consider a fixed VG with VD varying from ∼ 0 V to a value beyond condition C.
In this situation, i.e., VD > V satD , a short high-field region develops near the drain end, and the
“excess” voltage, VD − V satD drops across this region.
Because the high-filed region is confined to a very small distance, the conditions in the device arealmost identical in C and D.
⇒ The current in case D is almost the same as that for case C.
The region VD > V satD is therefore called the “saturation region.”
M. B. Patil, IIT Bombay
![Page 55: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/55.jpg)
JFET: saturation
G
G
DS
G
G
DSDD
G
G
S
G
G
S
A B C D
A
B
C D
VD < V satD
0 V
VD = V satD
0 V
VD > V satDVD≈ 0 V
0 V 0 V
VDV sat
D =VG − VP
ID
Consider a fixed VG with VD varying from ∼ 0 V to a value beyond condition C.
In this situation, i.e., VD > V satD , a short high-field region develops near the drain end, and the
“excess” voltage, VD − V satD drops across this region.
Because the high-filed region is confined to a very small distance, the conditions in the device arealmost identical in C and D.
⇒ The current in case D is almost the same as that for case C.
The region VD > V satD is therefore called the “saturation region.”
M. B. Patil, IIT Bombay
![Page 56: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/56.jpg)
JFET: example
An n-channel silicon JFET has the following parameters (at T = 300 K): a = 1.5µm, L = 5µm,
Z = 50µm, Nd = 2× 1015 cm−3, Vbi = 0.8 V , µn = 300 cm2/V -sec.
(a) What is the pinch-off voltage?
(b) Write a program to generate ID -VD characteristics for VG = 0 V , −0.5 V , −1 V , −1.5 V ,−2 V .
(c) For each of the above VG values, compute V satD , and show it on the ID -VD plot. The part of
an ID -VD corresponding to VD < V satD is called the “linear” region, and that corresponding
to VD > V satD is called the “saturation” region.
Answer:
(a) VP =−2.68 V .
(b) linear saturation
100
50
0
200
150
0 1 2 3 4 5
VD (Volts)
I D(µ
A) −0.5 V
−1 V
−1.5 V
−2 V
VG =0 V
M. B. Patil, IIT Bombay
![Page 57: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/57.jpg)
JFET: example
An n-channel silicon JFET has the following parameters (at T = 300 K): a = 1.5µm, L = 5µm,
Z = 50µm, Nd = 2× 1015 cm−3, Vbi = 0.8 V , µn = 300 cm2/V -sec.
(a) What is the pinch-off voltage?
(b) Write a program to generate ID -VD characteristics for VG = 0 V , −0.5 V , −1 V , −1.5 V ,−2 V .
(c) For each of the above VG values, compute V satD , and show it on the ID -VD plot. The part of
an ID -VD corresponding to VD < V satD is called the “linear” region, and that corresponding
to VD > V satD is called the “saturation” region.
Answer:
(a) VP =−2.68 V .
(b) linear saturation
100
50
0
200
150
0 1 2 3 4 5
VD (Volts)
I D(µ
A) −0.5 V
−1 V
−1.5 V
−2 V
VG =0 V
M. B. Patil, IIT Bombay
![Page 58: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/58.jpg)
JFET: simplified model for saturation
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
.
At saturtation, V satD = VG − VP , giving
I satD = G0
(VD −
2
3(Vbi − VP )
"1−
„Vbi − VG
Vbi − VP
«3/2#)
.
The following approximate model is found to be adequate in circuit design:
I satD (VG ) = IDSS (1− VG/VP )2, where IDSS = I sat
D (VG = 0 V ).
In amplifier design, we are interested in gm =∂ID
∂VG
˛̨̨̨VD =constant
, which is obtained as:
gm = gm0 (1− VG/VP ),
where gm0 =−2IDSS/VP = gm(VG = 0 V ).
M. B. Patil, IIT Bombay
![Page 59: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/59.jpg)
JFET: simplified model for saturation
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
.
At saturtation, V satD = VG − VP , giving
I satD = G0
(VD −
2
3(Vbi − VP )
"1−
„Vbi − VG
Vbi − VP
«3/2#)
.
The following approximate model is found to be adequate in circuit design:
I satD (VG ) = IDSS (1− VG/VP )2, where IDSS = I sat
D (VG = 0 V ).
In amplifier design, we are interested in gm =∂ID
∂VG
˛̨̨̨VD =constant
, which is obtained as:
gm = gm0 (1− VG/VP ),
where gm0 =−2IDSS/VP = gm(VG = 0 V ).
M. B. Patil, IIT Bombay
![Page 60: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/60.jpg)
JFET: simplified model for saturation
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
.
At saturtation, V satD = VG − VP , giving
I satD = G0
(VD −
2
3(Vbi − VP )
"1−
„Vbi − VG
Vbi − VP
«3/2#)
.
The following approximate model is found to be adequate in circuit design:
I satD (VG ) = IDSS (1− VG/VP )2, where IDSS = I sat
D (VG = 0 V ).
In amplifier design, we are interested in gm =∂ID
∂VG
˛̨̨̨VD =constant
, which is obtained as:
gm = gm0 (1− VG/VP ),
where gm0 =−2IDSS/VP = gm(VG = 0 V ).
M. B. Patil, IIT Bombay
![Page 61: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/61.jpg)
JFET: simplified model for saturation
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
.
At saturtation, V satD = VG − VP , giving
I satD = G0
(VD −
2
3(Vbi − VP )
"1−
„Vbi − VG
Vbi − VP
«3/2#)
.
The following approximate model is found to be adequate in circuit design:
I satD (VG ) = IDSS (1− VG/VP )2, where IDSS = I sat
D (VG = 0 V ).
In amplifier design, we are interested in gm =∂ID
∂VG
˛̨̨̨VD =constant
, which is obtained as:
gm = gm0 (1− VG/VP ),
where gm0 =−2IDSS/VP = gm(VG = 0 V ).
M. B. Patil, IIT Bombay
![Page 62: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/62.jpg)
JFET: simplified model for saturation
ID = G0
(VD −
2
3(Vbi − VP )
"„VD + Vbi − VG
Vbi − VP
«3/2
−„
Vbi − VG
Vbi − VP
«3/2#)
.
At saturtation, V satD = VG − VP , giving
I satD = G0
(VD −
2
3(Vbi − VP )
"1−
„Vbi − VG
Vbi − VP
«3/2#)
.
The following approximate model is found to be adequate in circuit design:
I satD (VG ) = IDSS (1− VG/VP )2, where IDSS = I sat
D (VG = 0 V ).
In amplifier design, we are interested in gm =∂ID
∂VG
˛̨̨̨VD =constant
, which is obtained as:
gm = gm0 (1− VG/VP ),
where gm0 =−2IDSS/VP = gm(VG = 0 V ).
M. B. Patil, IIT Bombay
![Page 63: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/63.jpg)
JFET: source/drain resistances
S D
Cross−sectional view
G
G
G
(Not drawn to scale. Typically, L≫ 2a.)
L
2an− Si S ′ D′
S D
p+
RS RD
In real JFETs, there is a separation between the source/drain contacts and the active channel.
The n-type semiconductor regions between the active channel and the source/drain contacts can
be modelled by resistances RS and RD .
M. B. Patil, IIT Bombay
![Page 64: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/64.jpg)
JFET: source/drain resistances
S D
Cross−sectional view
G
G
G
(Not drawn to scale. Typically, L≫ 2a.)
L
2an− Si S ′ D′
S D
p+
RS RD
In real JFETs, there is a separation between the source/drain contacts and the active channel.
The n-type semiconductor regions between the active channel and the source/drain contacts can
be modelled by resistances RS and RD .
M. B. Patil, IIT Bombay
![Page 65: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/65.jpg)
JFET: small-signal model
G
D
S
G
S
D
Amplifier example
RG RG
VDD
VSS
V1 V2
Vo
R R
gd
gmvg
vg Cgs
Cgd
* A small-signal model of a JFET is required in analysis of an amplifier.
* The DC gate current, which is the reverse current of a p-n junction, is generally insignificantand is therefore ignored.
* gm =∂ID
∂VG
with VD = constant.
* gd =∂ID
∂VD
with VG = constant.
* gm and gd can be obtained by differentiating ID (VG ,VD ). Note that, in our simple model,short-channel effects have not been included; we would therefore obtain gd = 0 f insaturation. However, a real device would show a small increase in ID with an increase in VD
in saturation, giving rise to a non-zero gd .
* The capacitances Cgs and Cgd are depletion capacitances of the p-n junction.
M. B. Patil, IIT Bombay
![Page 66: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/66.jpg)
JFET: small-signal model
G
D
S
G
S
D
Amplifier example
RG RG
VDD
VSS
V1 V2
Vo
R R
gd
gmvg
vg Cgs
Cgd
* A small-signal model of a JFET is required in analysis of an amplifier.
* The DC gate current, which is the reverse current of a p-n junction, is generally insignificantand is therefore ignored.
* gm =∂ID
∂VG
with VD = constant.
* gd =∂ID
∂VD
with VG = constant.
* gm and gd can be obtained by differentiating ID (VG ,VD ). Note that, in our simple model,short-channel effects have not been included; we would therefore obtain gd = 0 f insaturation. However, a real device would show a small increase in ID with an increase in VD
in saturation, giving rise to a non-zero gd .
* The capacitances Cgs and Cgd are depletion capacitances of the p-n junction.
M. B. Patil, IIT Bombay
![Page 67: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/67.jpg)
JFET: small-signal model
G
D
S
G
S
D
Amplifier example
RG RG
VDD
VSS
V1 V2
Vo
R R
gd
gmvg
vg Cgs
Cgd
* A small-signal model of a JFET is required in analysis of an amplifier.
* The DC gate current, which is the reverse current of a p-n junction, is generally insignificantand is therefore ignored.
* gm =∂ID
∂VG
with VD = constant.
* gd =∂ID
∂VD
with VG = constant.
* gm and gd can be obtained by differentiating ID (VG ,VD ). Note that, in our simple model,short-channel effects have not been included; we would therefore obtain gd = 0 f insaturation. However, a real device would show a small increase in ID with an increase in VD
in saturation, giving rise to a non-zero gd .
* The capacitances Cgs and Cgd are depletion capacitances of the p-n junction.
M. B. Patil, IIT Bombay
![Page 68: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/68.jpg)
JFET: small-signal model
G
D
S
G
S
D
Amplifier example
RG RG
VDD
VSS
V1 V2
Vo
R R
gd
gmvg
vg Cgs
Cgd
* A small-signal model of a JFET is required in analysis of an amplifier.
* The DC gate current, which is the reverse current of a p-n junction, is generally insignificantand is therefore ignored.
* gm =∂ID
∂VG
with VD = constant.
* gd =∂ID
∂VD
with VG = constant.
* gm and gd can be obtained by differentiating ID (VG ,VD ). Note that, in our simple model,short-channel effects have not been included; we would therefore obtain gd = 0 f insaturation. However, a real device would show a small increase in ID with an increase in VD
in saturation, giving rise to a non-zero gd .
* The capacitances Cgs and Cgd are depletion capacitances of the p-n junction.
M. B. Patil, IIT Bombay
![Page 69: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/69.jpg)
JFET: small-signal model
G
D
S
G
S
D
Amplifier example
RG RG
VDD
VSS
V1 V2
Vo
R R
gd
gmvg
vg Cgs
Cgd
* A small-signal model of a JFET is required in analysis of an amplifier.
* The DC gate current, which is the reverse current of a p-n junction, is generally insignificantand is therefore ignored.
* gm =∂ID
∂VG
with VD = constant.
* gd =∂ID
∂VD
with VG = constant.
* gm and gd can be obtained by differentiating ID (VG ,VD ). Note that, in our simple model,short-channel effects have not been included; we would therefore obtain gd = 0 f insaturation. However, a real device would show a small increase in ID with an increase in VD
in saturation, giving rise to a non-zero gd .
* The capacitances Cgs and Cgd are depletion capacitances of the p-n junction.
M. B. Patil, IIT Bombay
![Page 70: EE101: JFET operation and characteristicssequel/ee101/ee101_jfet_1.pdf · * The mechanism of gate control varies in di erent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs](https://reader033.fdocuments.net/reader033/viewer/2022043012/5fa9c03da798e861eb5e25a8/html5/thumbnails/70.jpg)
JFET: small-signal model
G
D
S
G
S
D
Amplifier example
RG RG
VDD
VSS
V1 V2
Vo
R R
gd
gmvg
vg Cgs
Cgd
* A small-signal model of a JFET is required in analysis of an amplifier.
* The DC gate current, which is the reverse current of a p-n junction, is generally insignificantand is therefore ignored.
* gm =∂ID
∂VG
with VD = constant.
* gd =∂ID
∂VD
with VG = constant.
* gm and gd can be obtained by differentiating ID (VG ,VD ). Note that, in our simple model,short-channel effects have not been included; we would therefore obtain gd = 0 f insaturation. However, a real device would show a small increase in ID with an increase in VD
in saturation, giving rise to a non-zero gd .
* The capacitances Cgs and Cgd are depletion capacitances of the p-n junction.
M. B. Patil, IIT Bombay