EE 240B discussion 4

Eric Chang

Outline

• HW2 design solution.

Amplifier type?

• PMOS or NMOS?– Depends on noise characteristics.

• In our technology, PMOS input gives you better noise performance.– Generally the case.

Amplifier sizing• Given a “unit amplifier”:

• When BW-limited, size is set by ! = #$%#&'(,'&*+#$%,-..,'&*/-01'.

• When integrated-noise-limited, we have SNR = 56789: -01'.;<= , >&8

?8>&8@?0>&0,

which sets minimum load cap, and size is set by BW constraint.

• When noise-density-limited, we have SNR = 6789: >&8AB<=∆# ,

>&8?8>&8@?0>&0

, which sets minimum DEF and therefore the size.

• Observations:– To make sure all specs passed, we need to figure out whether BW spec or

noise spec is active.

– For noise spec the constant >&8?8>&8@?0>&0

determines the noise performance. Should try to maximize.

DiffAmp input sizing

• Set !"#$% to minimum voltage (maximize headroom).– Later on in class we’ll figure out better way to

determine this…• !&'"() given by spec, !$*() set by linearity

spec.

DiffAmp load sizing

• !"# set by !$%&'( and )*+,- set by input transistor (KCL). We can freely pick !.#, then the number of fingers is uniquely determined from !.#, !"#, and )*+,-.

• Which !.# should we pick? Maximize /$? Minimize noise? How to minimize noise?

• Also have to make sure we meet gain/maximum BW requirement.

DiffAmp Load Vgs tradeoff• Amplifier Gain and

max BW increase with Vgs.

• ! increases with Vgs, but "# (per current) decreases faster.

• So choosing maximumVgs makes everything better.

• Basically, triode load has better noise performance.

DiffAmp Noise-limited design flow

1. Design input from linearity spec.2. Find Vgs for load that meets gain/max BW

specs and minimize !"#.3. Determine if amplifier size is noise or BW

limited, and size accordingly.– For integrated noise case, we may need to add

additional capacitance.4. Design tail transistor to support the required

bias current.

Cascode amplifier design

• Same idea as diffamp, just more variables.– More opportunities for optimization…

• Noise-density constraint gives us:

SNR = %&'() *+',-./∆1 2

*+'3'*+'435*+5

• Assuming most noise come from the input instead of the load, the SNR is roughly proportional to 678/:8. So we want to maximize this quantity (normalized to bias current).

Cascode input tradeoff• “weak” dependence of !∗ on !#$ means we can tweak !%$.

• &' increases with !#$and ( is roughly constant when in saturation, so we should maximize bottom !#$ to improve noise.

• The larger the cascode transistor ()), the better the output resistance. So want to maximize that.– But not too much as

that’ll kill BW spec.

Cascode load/amplifier design

• Just sweep bottom Vgs, cascode transistor size, and cascode bias and find the configuration that meets gain/max BW specs and minimize !"#$".

• Also check that the intrinsic gain of the bottom transistor is above a certain threshold.– The assumption that only bottom transistor

contribute noise is only valid if the bottomtransistor is in saturation.

• The final amplifier size is determined just like in the differential amplifier case.

Cascode amplifier design flow

1. Design input from linearity spec, and try to find cascode settings that maximize !"#/%# and &'.

2. Find load configuration that meets gain/max BW specs and minimize %(!"(. Make sure bottom transistor is “saturated”.

3. Determine if amplifier size is noise or BW limited, and size accordingly.

4. Design tail transistor to support the required bias current.

Implementation details/Python tricks (see solution).

• In characterization script, if you set load_from_file=True, it will load pre-existingsimulation data and re-do the post-processingalgorithm.– This allows you to change noise integration period (i.e.

how gamma is computed) without re-running simulations.

• scipy.optimize.brentq() can find zero of an arbitrary 1-D function inside a given interval.– Can be used to solve for intermediate cascode voltage

with just transistor characterization data (no simulation needed).