Dynamic CMOS Circuits - ChulaDynamic CMOS Circuits Boonchuay Supmonchai Integrated Design...

B.Supmonchai July 4th, 2005

2102-545 Digital ICs 1

Chapter 6

Dynamic CMOS Circuits

Boonchuay SupmonchaiIntegrated Design Application Research (IDAR) Laboratory

August 15, 2004; Revised - July 4, 2005

2102-545 Digital ICs Dynamic CMOS Gates 2

B.Supmonchai

Goals of This Chapter

q In-depth discussion of CMOS logic families

ß Static and Dynamic

ß Pass-Transistor

ß Nonratioed and Ratioed Logic

q Optimizing gate metrics

ß Area, Speed, Energy or Robustness

q High Performance circuit-design techniques


B.Supmonchai

Dynamic CMOS

q In static circuits at every point in time (exceptwhen switching) the output is connected toeither GND or VDD via a low resistance path.ß fan-in of N requires 2N devices

q Dynamic circuits rely on the temporary storageof signal values on the capacitance of highimpedance nodes.ß requires only N + 2 transistors

ß takes a sequence of precharge and conditionalevaluation phases to realize logic functions


B.Supmonchai

on

Dynamic Gate

In1

In2 PDN

In3

Me

Mp

CLK

CLK

Out

CL

Out

CLK

CLK

A

BC

Mp

Me

Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)

on

off

1off

!((A&B)|C)




B.Supmonchai

Conditions on Output

q Once the output of a dynamic gate is discharged, itcannot be charged again until the next prechargeoperation.

q Inputs to the gate can make at most one transitionduring evaluation.

q Output can be in high impedance state during andafter evaluation (PDN off), state is stored on CL

ß This behavior is fundamentally different than the staticcounterpart that always has a low resistance pathbetween the output and one of the power rails


B.Supmonchai

Properties of Dynamic Gatesq Number of transistors is N + 2 (versus 2N for static

complementary CMOS)

ß Logic function is implemented by the PDN only

ß Should be smaller in area than static complementary CMOS

q Full swing outputs (VOL = GND and VOH = VDD)

q Nonratioed - sizing of the devices is not important forproper functioning (only for performance)

q Low noise margin (NML)

ß PDN starts to work as soon as the input signals exceed VTn, soset VM, VIH and VIL all equal to VTn


B.Supmonchai

Properties of Dynamic Gates IIq Faster switching speeds

ß Reduced load capacitance due to lower number of transistorsper gate (Cint) so a reduced logical effort

ß Reduced load capacitance due to smaller fan-out (Cext)

ß No Isc, so all the current provided by PDN goes intodischarging CL

ß Ignoring the influence of precharge time on the switchingspeed of the gate, tpLH = 0 but the presence of the evaluationtransistor slows down the tpHL

q Needs a precharge/evaluate clock


B.Supmonchai

Properties of Dynamic Gates IIIq Power dissipation should be better than CMOSß Consumes only dynamic power – no short circuit power

consumption since the pull-up path is not on when evaluating

ß Lower CL- both Cint (since there are fewer transistorsconnected to the drain output) and Cext (since there the outputload is one per connected gate, not two)

ß No glitches - By construction can have at most one transitionper cycle

q However overall power dissipation is usually higherthan static CMOS due toß higher transition probabilitiesß extra load on CLK




B.Supmonchai

Dynamic Behavior

CLK

CLK

In1

In2

In3

In4

Out

83ps0ns110psVTn2.5-VTnVTn0V2.5V6

tptpLHtpHLNMLNMHVMVOLVOH#Trs

In &CLK Out

-0.5

0.5

1.5

2.5

0 0.5 1

Time (ns)V

olt

age

(V)

Evaluate

Precharge

all data inputs set to 1


B.Supmonchai

Notes on Dynamic Behaviorq The precharge time is determined by the time it takes to

charge CL through the PMOS precharge transistor.

ß Often, the overall digital system can be designed in such a waythat the precharge time coincides with other system functions(e.g., precharge of a FU can coincide with instruction decode).

q The duration of the precharge cycle can be adjusted bychanging the size of the PMOS precharge transistor.

q But making it too large increases the gate’s Cint as wellas increasing the capacitive load on the clock.


B.Supmonchai

Gate Parameters are Time Independentq The amount by which the output voltage drops is a

strong function of the input voltage and the availableevaluation time.ß Noise needed to corrupt the signal has to be larger if the

evaluation time is short – i.e., the switching threshold is trulytime independent.

Time (ns)

-0.5

0.5

1.5

2.5

0 20 40 60 80 100

Vo

ltag

e (V

)

CLK

Vout (VG=0.45)

Vout (VG=0.5)

Vout (VG=0.55)


B.Supmonchai

Power Consumption of Dynamic Gate

Power only dissipated when previous Out = 0

In1

In2 PDN

In3

Me

Mp

CLK

CLK

Out

CL

But what about clock power impact?

EliminatesStatic powerConsumption




B.Supmonchai

011

001

010

100

OutBA

Dynamic 2-input NOR Gate

Assume signal probabilities PA=1 = 1/2 PB=1 = 1/2

Then transition probability P0Æ1 = Pout=0 x Pout=1

= 3/4 x 1 = 3/4

Switching activity can be higher in dynamic gates!P0Æ1 = Pout=0

Dynamic PC is Data Dependent

(static NOR gate P0Æ1 = 3/16)


B.Supmonchai

Issues in Dynamic Design 1: Charge Leakage

CLK

VOut

Precharge

EvaluateCLK

CLK

Out

A=0

Leakage sources

CL

Mp

Me

1

2

34

Minimum clock rate of a few kHz


B.Supmonchai

Source of Charge Leakageq Charge stored on CL will leak away with time (input in

low state during evaluation)

q Dominant leakage sources are reverse-biased diode (1)and the sub-threshold leakage (2) of the NMOSpulldown device.

q PMOS precharge device also contributes some leakagedue to reverse bias diode (3) and subthresholdconduction (4) that, to some extent, offsets the leakagedue to the pull down paths.

q Requires a minimum clock rateß Not good for low performance products such as watches (or

when there are conditional clocks)


B.Supmonchai

-0.5

0.5

1.5

2.5

0 20 40

Time (ms)

Vo

ltag

e (V

)

CLK

Out

Impact of Charge Leakageq Output settles to an intermediate voltage determined by a

resistive divider of the pull-up and pull-down networks

ß Once the output drops below the switching threshold of thefan-out logic gate, the output is interpreted as a low voltage.




B.Supmonchai

A Solution to Charge Leakage

Same approach aslevel restorer logic

Keeper

q Keeper compensates for the charge lost due to the pull-down leakage paths.

CL

CLK

CLK

Me

Mp

A

B

Mkp

Out

ONVDDOFFEvaluate

ON

Irr.

PDN

ON Æ OFFVDD Æ 0

ONVDDPrecharge

MkpOutState

If PDN is on, there is a fight between the PDN and the PUN - circuitmust be ratioed so that PDN wins, eventually


B.Supmonchai

Issues in Dynamic Design 2: Charge Sharing

Charge stored originally onCL is redistributed (shared)over CL and CA leading tostatic power consumption bydownstream gates andpossible circuit malfunction.

When DVout = - VDD (Ca / (Ca + CL )) the drop in Vout islarge enough to be below the switching threshold ofthe gate it drives causing a malfunction.

CL

CLK

CLK

Ca

Cb

B=0

A

OutMp

Me


B.Supmonchai

What is the worst case voltage drop on y? (Assume all inputs arelow during precharge and that all internal nodes are initially at 0V.)

Charge Sharing Example

CLK

CLK

A !A

B !B B !B

C!C

y = A ⊕ B ⊕ C

Cy=50fF

Ca=15fF

Cc=15fF

Cb=15fF

Cd=10fF

Loadinverter

a

b

dc

DVout = - VDD [(Ca + Cc)/((Ca + Cc) + Cy)]

= - 2.5V*(30/(30+50)) = -0.94V


B.Supmonchai

Notes on Charge Sharing Example

q Output stays high for 4 out of 8 cases (!A B C,!A !B !C, A !B C, and A B !C)

q Worst case is obtained by exposing themaximum amount of internal capacitance tothe output node during evaluation.

ß This happens when !A B C or A !B C

q ∆V = -0.94 V so the output drops to 2.5 - 0.94 =1.56 V which is below the switching threshold ofthe Load inverter.




B.Supmonchai

Precharge internal nodes using a clock-driven transistor(at the cost of increased area and power)

Solution to Charge Redistribution

Me

Mp

CLK

CLK

A

B

Out

Mkp CLK


B.Supmonchai

=1=0

q Susceptible to crosstalk due to 1) high impedance of theoutput node and 2) capacitive coupling

Issues in Dynamic Design 3: Backgate Coupling

CLK

CLK

B=0

A=0

Out1Mp

Me

Out2

In

Dynamic NAND

Static NAND

M1

M2M3

M4

M5M6

CL1 CL2

Out2 capacitively couples with Out1through the gate-source and gate-drain capacitances of M4


B.Supmonchai

Backgate Coupling Effect

Vo

lta

ge

Time (ns)

-1

0

1

2

3

0 2 4 6

CLK

In

Out1

Out2

q Capacitive coupling means Out1 drops significantly soOut2 does not go all the way to ground


B.Supmonchai

Notes on Backgate Coupling Effectq The high impedance of the output node makes

the circuit very sensitive to crosstalk effects.ß A wire routed over or next to a dynamic node may

couple capacitively and destroy the state of thefloating node.

q Due to capacitive backgate coupling between theinternal and output node of the static gate andthe output of the dynamic gate, Out1 voltage isreduced.

q Out1 overshoots VDD (2.5V) due to clockfeedthrough




B.Supmonchai

CL

CLK

CLK

B

A

OutMp

Me

Coupling between Out andCLK input of the prechargedevice due to the gate- draincapacitance. So voltage ofOut can rise above VDD. Thefast rising (and falling edges)of the clock couple to Out.

q A special case of capacitive coupling between the clockinput of the precharge transistor and the dynamic outputnode

Issues in Dynamic Design 4: Clock Feedthrough


B.Supmonchai

CLK

CLK

In1

In2

In3

In4

Out

In &CLK

Out

Time (ns)

-0.5

0.5

1.5

2.5

0 0.5 1

Vo

ltag

e (V

)

Clockfeedthrough

Clock Feedthrough Example

Clock feedthrough

Signal levels can rise enough above VDD that the normally reverse-biased junction diodes become forward-biased causing electronsto be injected into the substrate.


B.Supmonchai

Cascading Dynamic GatesV

t

CLK

In

Out1

Out2DV

VTn

Only a single 0 Æ 1 transition allowed at theinputs during the evaluation period!

CLK

Out1

CLK

CLK

In

Mp

Me

Out2

CLK Mp

Me


B.Supmonchai

Domino Logic

1 Æ 11 Æ 0

0 Æ 00 Æ 1

Out1 Out2

Mkp

In1

In2 PDN

In3

Me

Mp

CLK

CLK

In2 PDN

In3

Me

Mp

CLK

CLK

Assume all inputs to the Domino gate are initially zero




B.Supmonchai

Why Domino?

In1

CLK

CLK

Ini PDNInj

Ini

Inj

PDN Ini PDNInj

Ini PDNInj

Like falling dominos!


B.Supmonchai

Notes on Dominic Logicq Ensures all inputs to the Domino gate are set to 0 at the

end of the precharge period. Hence, the only possibletransition during evaluation is 0 to 1

q Additional advantage is that the fan-out of the gate isdriven by a static inverter with a low-impedance outputthat increases the noise immunity.

q The buffer also reduces the capacitance of the dynamicoutput node by separating internal and loadcapacitances.

q Finally, the inverter can be used to drive a bleeder tocombat leakage and charge redistribution.


B.Supmonchai

Ci,0

CLK

CLK

G0

P0 P1 P2 P3

G1 G2 G3

Ci,41234

5

6

3 3 3 3 3

1

2

2

3

3

4

4

5

!(G0 + P0 Ci,0) !(G1 + P1G0 + P1P0 Ci,0)

Domino Manchester Carry Chain

Automatically forms all the intermediate carries


B.Supmonchai

CLKA3

B3

A2

B2

A1

B1

A0

B0

Out

Domino Comparator

Don’t need isolation NMOS in the pull-down,since the PDN is forced off during precharge.




B.Supmonchai

Properties of Domino Logicq Only non-inverting logic can be implemented, fixes

include

ß can reorganize the logic using Boolean transformations

ß use differential logic (dual rail)

ß use np-CMOS (zipper)

q Very high speed

ß tpHL = 0, only Low-High transitions allow

ß static inverter can be optimized to match fan-out (separation offan-in and fan-out capacitances)

ß Input capacitances reduced - smaller logical effort


B.Supmonchai

Due to its high-performance, differential domino is very popularand is used in several commercial microprocessors!

1 0 1 0

onoff

Differential (Dual Rail) Domino

Me

Mp Mkp Mkp Mp

A

B

CLK

CLK

!Out = !(AB)

!A !B

CLK

Out = AB

AND/NAND

q Solve problem of non-inverting logic


B.Supmonchai

Notes on Differential Dominoq The inputs and their complements come from other

differential DR gates and thus all inputs are low duringprecharge and make a conditional transition from 0 to 1.

q Expensive - but can implement any arbitrary function.

q Use significant power since they have a guaranteedtransition every single clock cycle (regardless of signalstatistics, since either Out or !Out will transit from 0 to 1).

q Nonratioed (even though it has a cross-coupled PMOSpair)


B.Supmonchai

np-CMOS (Zipper)

1 Æ 11 Æ 0

0 Æ 00 Æ 1

Only 0 Æ 1 transitions allowed at inputs of PDNOnly 1 Æ 0 transitions allowed at inputs of PUN

In1

In2

In3

Me

Mp

CLK

CLKOut1

In4

In5

Me

Mp!CLK

!CLK

Out2(to PDN)

PUN

PDN

In4 and In5 must be from PDN




B.Supmonchai

NORA (No Race)

1 Æ 11 Æ 0

0 Æ 00 Æ 1

Very sensitive to Noise!

In1

In2

In3

Me

Mp

CLK

CLKOut1

In4

In5

Me

Mp!CLK

!CLK

Out2(to PDN)

to otherPDN’s

to otherPUN’s

PUN

PDN


B.Supmonchai

Note on np-CMOS and NORAq DEC alpha uses np-CMOS logic (Dobberpuhl)

q Have to size the PUN’s to equalize the delay to that ofthe PDN’s

q Really dense layouts and very high speed (20% fasterthan domino with the correct sizing)

q Reduced noise margin (as with any dynamic gate)

ß More sensitive to noise

q Increase complexity

ß Have two clock signals to generate and route - CLK and !CLK


B.Supmonchai

np-CMOS Adder Circuit

1 Æ x

0 Æ xB0

C0

C0

C0

!C1

!Sum0B0A0

A0

B0B0 A0

A0

CLK

CLK !CLK

!CLK

C2

Sum1!A1

!A1

!B1!B1

!A1!A1!B1

!B1

!C1

!C1

!CLK

!CLK CLK

CLK

0 Æ x

1 Æ x

0 Æ x

0 Æ x

1 Æ x

1 Æ x


B.Supmonchai

3

4

2

1

Ease

4

2 + clk

3

1

Power

1yes10DCVSL*

2no6 + 2domino

4no12 + 2CPL*

3no8Comp Static

DelayRatioed?# TransStyle

4-input NAND

* Dual Rail

q Current trend is towards an increased use ofcomplementary static CMOS: design support throughDA tools, robust, more amenable to voltage scaling.

How to Choose a Logic Styleq Must consider ease of design, robustness (noise

immunity), area, speed, power, system clockingrequirements, fan-out, functionality, ease of testing

Dynamic CMOS Circuits - ChulaDynamic CMOS Circuits Boonchuay Supmonchai Integrated Design...

Documents

Transcript of Dynamic CMOS Circuits - ChulaDynamic CMOS Circuits Boonchuay Supmonchai Integrated Design...