Dynamic CMOS 2004

8/6/2019 Dynamic CMOS 2004

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Krish Chakrabarty 1

Dynamic CombinationalCircuits

Dynamic circuits Charge sharing, charge redistribution

Domino logic np-CMOS (zipper CMOS)

Krish Chakrabarty 2

Dynamic Logic

Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate

1

2A Y

4/3

2/3

AY

1

1

AY

Static Pseudo-nMOS Dynamic

Precharge Evaluate

Y

Precharge


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Krish Chakrabarty 3

The Foot What if pulldown network is ON during

precharge? Use series evaluation transistor to prevent fight.

AY

foot

precharge transistor Y

inputs

Y

inputs

footed unfooted

f f

Krish Chakrabarty 4

Dynamic Logic

M p

M e

V DD

PDN In 1 In 2 In 3

Out M e

M p

V DD

PUN In 1 In 2 In 3

Out

C L

C L

2 phase operation: Evaluation

Precharge

n network p network


3/15

Krish Chakrabarty 5

Logical EffortInverter NAND2 NOR2

1

1

AY

2

2

1

B

AY

A B 11

1

g d = 1/3p d = 2/3

gd = 2/3pd = 3/3

gd = 1/3pd = 3/3

Y

2

1

AY

3

3

1

B

AY

A B 22

1

g d = 2/3p d = 3/3

gd = 3/3pd = 4/3

gd = 2/3pd = 5/3

Y

footed

unfooted

32 2

Krish Chakrabarty 6

Dynamic Logic

N+2 transistors for N-input function Better than 2N transistors for complementary static CMOS Comparable to N+1 for ratio-ed logic

No static power dissipation Better than ratio-ed logic

Careful design, clock signal needed


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Krish Chakrabarty 7

Dynamic Logic: Principles

M p

M e

V DD

PDN In 1 In 2 In 3

Out

C L

Precharge = 0, Out is precharged to V DD by M p.

M e is turned off, no dc current flows(regardless of input values)

Evaluation = 1, M e is turned on, M p is turned off.Output is pulled down to zero dependingon the values on the inputs. If not,

precharged value remains on C L.

Important : Once Out is discharged, it cannot be charged again!Gate input can make only one transition during evaluation

Minimum clock frequency must be maintained Can M e be eliminated?

Krish Chakrabarty 8

Example

M p

M e

V DD

Out

A

B

C

Ratioles s

No Static Power Consumption

Noise Margins small (NM L)

Requires Clock


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Krish Chakrabarty 9

Dynamic 4 Input NAND Gate

In 1

In 2

In 3

In 4

Out

V DD

GND

Krish Chakrabarty 10

Cascading Dynamic Gates

M p

M e

V DD

M p

M e

V DD

In

Out 1 Out 2

Internal nodes can only make 0-1 transitions during evaluation period

Out 2

Out 1

In

V

t

V Tn


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Monotonicity Dynamic gates require monotonically rising inputs

during evaluation 0 -> 0 0 -> 1 1 -> 1 But not 1 -> 0

Precharge Evaluate

Y

Precharge

A

Output should rise but does not

violates monotonicityduring evaluation

A


Monotonicity Woes But dynamic gates produce monotonically falling

outputs during evaluation Illegal for one dynamic gate to drive another!

A X

Y Precharge Evaluate

X

Precharge

A = 1

Y should rise but cannot

Y

X monotonically falls during evaluation


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Reliability Problems Charge Leakage

M p

M e

V DD

Out

AC L(1)

(2)

t

t

V out

(b) Effect on waveforms(a) Leakage sources

precharge evaluate

Minimum Clock Frequency: > 1 MHz

A = 0

(1) Leakage through reverse-biased diode of the diffusion area(2) Subthreshold current from drain to source


Leakage Dynamic node floats high during evaluation

Transistors are leaky (I OFF 0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds!

Use keeper to hold dynamic node Must be weak enough not to fight evaluation

A

H

2

2

1 kX Y

weak keeper


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Charge Sharing (redistribution)

M p

M e

V DD

Out

A

B = 0

C L

C a

C b

M a

M b

X

Assume: during precharge, A and B are 0, C a is discharged During evaluation, B remains 0 and A rises to 1 Charge stored on C L is now redistributed over C L and C a

CLVDD = C L Vout(t) + C aVX

VX = V DD - V t, thereforeVout(t) = V out(t) - V DD = (V DD-V t)CL

Ca

Desirable to keep the voltage drop below threshold

of pMOS transistor (why?) Ca/CL < 0.2


Charge Sharing Dynamic gates suffer from charge sharing

B = 0

AY

x

Cx

CYA

x

Y

Charge sharing noise

Y x Y DD

x Y

C V V V

C C = =

+


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Charge Redistribution - Solutions

M p

M e

V DD

Out

A

B

M a

M b

M bl M p

M e

V DD

Out

A

B

M a

M b

M bl

(b) Precharge of internal nodes(a) Static bleeder


Secondary Precharge Solution: add secondary precharge transistors

Typically need to precharge every other node

Big load capacitance C Y helps as well

B

AY

x

secondaryprechargetransistor


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Domino Logic

M p

M e

V DD

PDN In 1 In 2 In 3

Out1M p

M e

V DD

PDN In 4

Out2

M r

V DD

Static Inverterwith Level Restorer

Static inverters between dynamic stages


Domino Gates Follow dynamic stage with inverting static gate

Dynamic / static pair is called domino gate Produces monotonic outputs

Precharge Evaluate

W

Precharge

X

Y

Z

A

B C

C

AB

W X Y Z =X

ZH H

A

W

B C

X Y Z

domino AND

dynamicNAND

staticinverter


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Domino Logic - Characteristics

Only non-inverting logic

Very fast - Only 1->0 transitions at input of inverter

Adding level restorer reduces leakage andcharge redistribution problems

Optimize inverter for fan-out

Precharging makes pull-up very fast


Domino Optimizations Each domino gate triggers next one, like a string of

dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic

S0

D0

S1

D1

S2

D2

S3

D3

S4

D4

S5

D5

S6

D6

S7

D7

YH


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Dual-Rail Domino Domino only performs noninverting functions:

AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem

Takes true and complementary inputs Produces true and complementary outputs

invalid11

101

010

Precharged00

Meaningsig_lsig_hY_h

f

inputs

Y_l

f


Example: AND/NAND Given A_h, A_l, B_h, B_l Compute Y_h = A * B, Y_l = ~(A * B) Pulldown networks are conduction complements

Y_h

Y_lA_h

B_hB_lA_l

= A*B= A*B


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Example: XOR/XNOR

Sometimes possible to share transistors

Y_h

Y_lA_l

B_h

= A xor B

B_l

A_hA_lA_h= A xnor B


Domino Summary

Domino logic is attractive for high-speed circuits 1.5 2x faster than static CMOS But many challenges:

Monotonicity Leakage Charge sharing Noise

Widely used in high-performance microprocessors


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np-CMOS (Zipper CMOS)

M p

M e

V DD

PDNIn1In2In3

M e

M p

V DD

PUNIn4

Out1

Out2

Only 1-0 transitions allowed at inputs of PUN Used a lot in the Alpha design


np CMOS Adder

V DD

C i0

A0 B0 B0

A0

V DD

B1

A1

V DD

A1 B1

C i1

C i2

C i0C i0

B0 A0 B0

S 0

A0

V DD

V DD

V DD

B1 C i1 B1

A1 A1

V D D S 1C i1

Carry Path


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CMOS Circuit Styles - Summary

Dynamic CMOS 2004

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