DSD Lecture 6

7/23/2019 DSD Lecture 6

http://slidepdf.com/reader/full/dsd-lecture-6 1/12Dr Oday A.L.A Ridha 76

ALGORITHMIC STATE MACHINE (ASM)

The binary information stored in a digital system can be classified as either data orcontrol information. Data are discrete elements of information that are manipulated to

perform arithmetic, logic, shift, and other similar data processing tasks. These operations are

implemented with digital components such as adders, decoders, multiplexers, counter, andshift registers. Control information provides command signals that supervise the variousoperations in the data section in order to accomplish the desired data-processing tasks. The

logic design of a digital system can be divided into two distinct parts. One part is concerned

with the design of the digital circuits that perform the data-processing operations. The other part is concerned with the design of the control circuit that supervises the operations and their

sequence.The relationship between the control logic and the data processor in a digital system is

shown in the figure below.

The control sequence and data-processing tasks of a digital system are specified by amean of a hardware algorithm, a finite number of procedural steps that specify how to obtain

a solution to a problem. The most challenging and creative part of a digital design is theformulation of hardware algorithms for achieving required objectives.

A flowchart is a convenient way to specify the sequence of procedural steps anddecision paths for an algorithm. A special flowchart that has been developed specially to

define digital hardware algorithms is called Algorithmic state machine (ASM) chart.The chart is composed of three basic elements: the state box, the decision box, and the

conditional box. A state in the control sequence is indicated by state box. The shape of thestate box is rectangle within which are written register operations or output signal names thatthe control generates while being in this state. The state is given a symbolic name, which

placed at the upper left corner of the box. The binary code assigned to the state is placed atthe upper right corner. Inside box is written register operations or output signals.

Control Logic Data processor

Commands

Status conditions

External

InputsInput

Data

Output

Data

Register operations or

output signals

Name Binary code

General descri tion

R 0START

T1 001

Exam le



The decision box describes the effect of an input on the control subsystem. It has a

diamond-shape box with two or more exit paths, as shown below.

The input condition to be tested is written inside the box. One exit path is taken if the

condition is true and another when the condition is false.

The third element of ASM chart is the conditional box. It has an oval shape. The

rounded corner is to differentiate it from state box. The input path of conditional box mustcome from one of the exit paths of the decision box. The register operations or outputs listed

inside the conditional box are generated during a given state provided that the input conditionis satisfied.

ASM block is a structure consisting of one state box and all the decision and

conditional boxes connecting to its exit path. An ASM block has one entrance and anynumber of exit paths represented by the structure of the decision boxes. An ASM chartconsists of one or more of interconnected blocks. Each ASM block describes the state of

logic circuit during one clock pulse interval.

Condition0 1

Exit path Exit path

Register operations or

output signals

ASM block

E

F10

0 1

A A+1

R 1

T1

T2 T3 T4

001

010 011 100

One clock

cycle

Present state

T1

Next state

T2, T3, or

T4



Some ASM figures

Some of register operations

Symbolic notation Description

A←B Transfer the content of reg. B to A

R ←0 Clear reg. R

A←A+1 Increment the content of reg. A by one

A←A-1 Decrement the content of reg. A by one

A←A+B Add reg. A and B then store the result in A

E

0

1

A A+1

T1

T2

001

010

E

0

1

A A+1

T1

T2

001

010

Invalid feedback Valid feedback

1

A A+1

I 1 0

R 1

T1 001

I 2 0

K 1

1

1

A A+1

T1 001

I 2 0

K 1

1

I 1 0

R 1Parallel interconnection

Serial interconnection



The ASM chart is very similar to a state diagram. Each state block is equivalent to a

state in sequential circuit. The decision box is equivalent to the binary informationwritten along the directed lines that connect two states in a state diagram. As

consequence, it is sometimes convenient to convert the chart to a state diagram and

then use sequential circuit procedures to design the control logic.

The ASM chart gives all the information necessary to design digital system. Therequirements for the design of data-processor subsystem are specified inside the state

and conditional boxes. The control logic (circuit) is determined from decision boxes

and required state transitions.

The control section of a digital system is essentially a sequential circuit that can bedesigned by the procedure used for previous lectures. However, in most cases this

method is impractical because of the large number of state and inputs that a typicalcontrol circuit may have, except for small controllers. There are special methods for

control logic design. These methods may be considered as an extension of the

sequential method. One of these methods is design with multiplexers.

E

F10

0 1

A A+1

R 1

T1

T2 T3 T4

001

010 011 100

001

010

011

100

E=1

EF=01

EF=00



Example: design a digital system with two flip-flops (E and F) and one 4-bit binary counter

(A). A start signal (S) initiates the system by clearing the counter (A) and the flip-flop (F).

The counter is then incremented by one starting from the next clock pulse, and continues

counting until the operations stop. Counter bits A3 and A4 determine the sequence ofoperations as follows:

• If A3=0, E is cleared to 0 and the counting continues.

•

If A3=1, E is set to 1; then if A4=0, the counting continues. But if A4=1, F is set to 1 on

the next clock pulse and the system stops counting.

J

K

Q

Q

E

J

K

Q

Q

F

4-bit

Counter

A4 A3 A2 A1

S

CLK

Control

Circuit

T0 T1

Tn

Clear

Count

Combinational

circuit



Solution:

By using G1 & G2 (JK-type F.F) for representingstates and using k-map for simplification, we

obtain the following logic equations for the control

circuit:

J1=QG2A3A4 , K1=1,

J2=S, K2=QG1,T0=QG2’, T1=QG1’.QG2, T2=QG1.

Combinational circuit equations

Clear=S.T0, Count=T1,JE=T1.A3, K E=T1.A3’,

JF=T2, K F=S.T0.

For more examples see Morris Mano page 305.

P.S

symbol

P.S.

Code

G1G2

I/Ps N.S.

Code

G1G2

O/Ps

S A3 A4 T0 T1 T2

T0 00 0 X X 00 1 0 0T0 00 1 X X 01 1 0 0

T1 01 X 0 X 01 0 1 0

T1 01 X 1 0 01 0 1 0

T1 01 X 1 1 11 0 1 0

T2 11 X X X 00 0 0 1

A←A+1

T1 01

F←1

1

T2

1

0

T0 00

A←0, F←0

0 1

E←0

0

E←1

11

S

A3

A4

CLKA3 A4

S J

K

Q

Q

G2

J

K

Q

Q

G1

1

T0

T1

T2

Control circuit

State table for control



MUX

D Q

F.F.

0

12

3S0 S1

MUX

D Q

F.F.

0

12

3

S0 S1

CLK

Decoder

T0

T2

T1

G1

G2

0

1S

0

0

A3

A4

Control circuit

Design with multiplexers

One major goal of control-logic design is the development of a circuit that implementsthe desired control sequence in a logical and straightforward manner. The attempt to

minimize the number of gates tends to produce an irregular network making it difficult foranyone but designer to identify the sequence of events the control undergoes. As

consequence, it is difficult to alter, service, or maintain the equipment after initial design. Thesequence of states in the control should be clearly evident from the circuit configuration even

if this requires additional components and results in a nonminimal circuit. The multiplexermethod is such an implementation.

The control circuit consists of three levels: the first level consists of multiplexers that

determine the next state. Second level contains a register that holds the present binary state.The third level has a decoder that provides separate output for each control state.

For example we redraw the control logic circuit using multiplexer method.

P.S. N.S. Input

conditions

Multiplexer inputs

G1 G2 G1 G2 MUX1 MUX2

0 0 0 0 S’0 S

0 0 0 1 S

0 1 0 1 A3’

A3.A4 10 1 0 1 A3.A4’

0 1 1 1 A3.A4 1 1 0 0 0 0



Shift register R1 Counter R2E

Input data Inputs= All 1’s

CountLoad R2

Output count

Load E

SI=0Shift right

Load R1

Z=1 if R1=0

Z Data processor subsystem of 1’s counter

Exercises1. A digital system consists of two registers ( R1 and R2) and a flip-flop E (as shown in the

figure below). Draw the ASM chart of the control circuit that makes the digital system countthe number of 1’s in the number loaded into register R1 and store the result in R2.

Solution

Count=R2←R2+1=T1, Load R2=S.T0

Shift R1=load E=T2, Load R1=S.T0

P.S. N.S. Input

conditions

Multiplexer inputs


0 0 0 0 S’0 S

0 0 0 1 S

0 1 0 0 ZZ’ 0

0 1 1 0 Z’

1 0 1 1 none 1 1

1 1 1 0 E’ E’ E1 1 0 1 E

R2←R2+1

T1 01

Shift R1 to E

1

0

T0 00

R1←input,R2←All 1’s

1

S

Z

0T2 10

T3 11

0 E

1

MUXD Q

F.F.

0

1

2

3 S0 S1

MUXD Q

F.F.

0

1

2

3

S0 S1

CLK

Decoder

T0

T3

T1

T2

G1

G2

E

0S

0

E’

Z’

Control circuit

1

1



Register B

Register A Register Q

Parallel Adder

E

Counter P

Z=1 if P=0

Z

Q1

Cout

Data processor subsystem of multiplier

Count

Load P

Load B

Clear ALoad A

Shift right

Load Q

Shift right

Load E

Clear E

B - MultiplicandQ - Multiplier P - down counter,

initially hold thelength of Q (n)

2. Design a logic circuit that multiplies two numbers

Solution

Clear E=Clear A=Load P=T1, Count=P ←P -1=T2, Load A=Load E=T2.Q1

Shift A=Shift Q=T3

P.S. N.S. Input

conditions

Multiplexer inputs


0 0 0 0 S’0 S

0 0 0 1 S

0 1 1 0 none 1 0

1 0 1 1 none 1 1

1 1 1 0 Z’Z’ 0

1 1 0 0 Z

A←0E←0

P←n

T1 01

P←P-1

1

0

T0 00

A←A+B, E←Cout

S

Q1

0

Shift ri ht AT3 11

0

Z1

T2 10

1MUX

D Q

F.F.

0

1

2

3 S0 S1

MUXD Q

F.F.

0

1

2

3

S0 S1

CLK

Decoder

T

T

T

T

G1

G2

0

0S

0

Z’

1

Control circuit

1

1



A

B

Full A

Full B

Empty B

M1 M2

M3 M4

M6Empty C

Heater

M5

100 C

Control and Driving circuitStart

Stop

Size= 1 volume

Size= 2 volume

Pump

Motor

Sensor

EmptyA

3.

Design a circuit that controls the process of mixing and heating two liquids (A and B).

The ratio between A and B in produced liquid must be ½ and at temperature of 100 C.Design the control circuit in such away that the production is maximum.


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Some states

ZB

ZA

Other states

Calling Machine A

Some states

ZA

Idle state

ZB

Calling Machine B

DSD Lecture 6

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