DSD Module1

8/13/2019 DSD Module1

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Module 1


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SummaryWhat is a digital system?

Why digital systems are favorite?

Introduction to HDL. Types of HDL Languages.

Basic Design Concept using VHDL.


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VHDL- Design Flow Design process divided into two

Front-end process Back end process


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Front end process Block Diagram

Coding

Compilation Simulation/Verification.


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CompilationVHDL compiler analyzes code for syntax errors and

also checks compatibility with other modules onwhich it relies.

It also creates internal information that is needed for asimulator to process the design later.


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Verification Simulation is just one piece of a larger step is called

verification.

It is verify that the circuit works as desired. Two types

Functional

Timing


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Verification Contd.

Functional

Study the circuits logical operations independent oftiming considerations.

Timing

We study the circuits operations including estimatedtime delays .


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Back-end process Synthesis

Fitting/Place+Route

Timing Verification.


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Synthesis Converting VHDL description into a set of primitives

or components that can be assembled in targettechnology.

FPGA

Synthesis tool generate two-level sum-of-productsequations.

ASIC Synthesis tool generate a list of gates and a netlist that

specifies how they should be interconnected.


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Fitting/Place + Route Laying down individual gates in a pattern and findings

way to connect them within the physical constraints ofthe ASIC or FPGA die.


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Timing VerificationAt this stage that the actual delay, due to wire length,

electrical loading etc. can be calculated withreasonable precision.


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Basic Structure of VHDL


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Entity Declaration

Identifier Mode

Type


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Basic Language Elements

( Lexical Elements of VHDL) Identifier

Identifiersare user-defined words used to name objectsin VHDL models.

We have seen examples of identifiers for input andoutput signals as well as the name of a design entity andarchitecture body.

When choosing an identifier one needs to follow thesebasic rules:


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Basic Rules May contain only alpha-numeric characters (A to Z, a

to z, 0-9) and the underscore (_) character

The first character must be a letter and the last onecannot be an underscore.

An identifier cannot include two consecutiveunderscores.

An identifier is case insensitive (ex. And2 and AND2 orand2 refer to the same object)

An identifier can be of any length.


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Keywords (Reserved words)

Certain identifiers are used by the system as keywordsfor special use such as specific constructs.

These keywords cannot be used as identifiers forsignals or objects we define.

We have seen several of these reserved words alreadysuch as in, out, or, and, port, map, end, etc.


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Modeis one of the reserved words to indicate the signal

direction:

inindicates that the signal is a n input

out indicates that the signal is an output of the

entity whose value can only be read by other entitiesthat use it.

buffer indicates that the signal is an output of theentity whose value can be read inside the entitysarchitecture

inout the signal can be an input or an output.


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Type- Pre-defined bitcan have the value 0 and 1 bit_vectoris a vector of bit values (e.g. bit_vector (0 to 7)

std_logic, std_ulogic, std_logic_vector, std_ulogic_vector:can have 9 values to indicate the value and strength of a

signal. Std_ulogic and std_logic are preferred over the bitor bit_vector types.

booleancan have the value TRUE and FALSE

integercan have a range of integer values

realcan have a range of real values

character any printing character

timeto indicate time


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Std_logic, std_ulogictypeSTD_ULOGIC is(

U, -- uninitialized

X, -- forcing unknown

0, -- forcing 01, -- forcing 1

Z, -- high impedance

W, -- weak unknownL, -- weak 0

H. -- weak 1

-); -- dont care


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User Defined Type typeidentifier istype_definition;

Integer types

type small_intis range 0to 1024; Floating type

Physical types

Enumerated Types

typestate_type is(S0, S1, S2, S3);


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Numbers

The default number representation is the decimalsystem.

VHDL allows integer literals and real literals. Integerliterals consist of whole numbers without a decimal

point, while real literals always include a decimalpoint.

Exponential notation is allowed using the letter E ore. For integer literals the exponent must always be

positive. Examples are: Integer literals: 12 10 256E3 12e+6

Real literals: 1.2 256.24 3.14E-2


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Characters, Strings and Bit Strings

use a character literal in a VHDL code, one puts it in asingle quotation mark, as shown in the examplesbelow:

a, B

On the other hand, a string of characters are placed indouble quotation marks as shown in the followingexamples:

This is a string,


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Bit StringA bit-string represents a sequence of bit values.

In order to indicate that this is a bit string, one placesthe B in front of the string: B1001.

Binary: B11001001, b1001011

Hexagonal: XC9, X4b

Octal: O311, o113

D Obj Si l V i bl d


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Data Objects: Signals, Variables andConstants.

A data object is created by an object declarationandhas a valueand typeassociated with it. An object canbe a Constant, Variable, Signal or a File.


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Constant

A constant can have a single value of a given type andcannot be changed during the simulation. A constantis declared as follows,

constant list_of_name_of_constant: type [ := initialvalue] ;

where the initial value is optional. Constants can be

declared at the start of an architecture and can then beused anywhere within the architecture.


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Examples constant RISE_FALL_TME: time := 2 ns;

constant DELAY1: time := 4 ns;

constant RISE_TIME, FALL_TIME: time:= 1 ns; constant DATA_BUS: integer:= 16;


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Variable

A variable can have a single value, as with a constant,but a variable can be updated using a variableassignment statement.

The variable is updated without any delay as soon asthe statement is executed.

Variables must be declared inside a process (and are

local to the process). The variable declaration is as follows:


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variablelist_of_variable_names: type [ := initial value] ;

A few examples follow:

variableCNTR_BIT: bit :=0;

variableVAR1: boolean :=FALSE;

variableSUM: integerrange 0to 256 :=16;

variableSTS_BIT: bit_vector (7 downto0);


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Signal

Signals are declared outsidethe process using the followingstatement:

signallist_of_signal_names: type [ := initial value] ;

signalSUM, CARRY: std_logic;signalCLOCK: bit;

signal TRIGGER: integer :=0;

signal DATA_BUS: bit_vector (0 to 7);

signalVALUE: integer range0 to100; Signals are updated when their signal assignment

statement is executed, after a certain delay, as illustratedbelow,


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SUM


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Operators

Logical Relational

Shift

Addition

Unary

Multiplying

Miscellaneous

DSD Module1

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