DPU Systems

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DPU Systems 2006

Programmable Single Step Processors

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$epartment, %lumina Press, P& 'o( ))22*6, +oral Springs, % --0))22*6

/S'N 1326*131

Printed in the 4nited States of America by %lumina Press

%ibrary of +ongress +ontrol Number 200630*0

Table of Contents/N5!&$4+5/&N in1 Purpose and &vervie 1

1.1 /ncreasing +omple(ity and +oncentration 1

1.1.1 +entralied Processing and +ontrol 2

1.1.2 5he 'ottlenec# 2

1.1.- 7ulnerability -

1.1.* %imits *

1.2 $ecentraliation and /ntegration

1.2.1 8andling the +ode )

1.2.2 Apportioning 9

1.2.- Simultaneous Processes 3

1.2.* 5he &perating System 101.2. 'ooting, %oading, and 5ermination 11

2 PSSPs : unction, and $esign 1

2.1 Separation of +ode and $ata 16

2.1.1 Processing Section of PSSPs 1)

2.1.2 +ontrol Section of PSSPs 20

2.1.- $ata lo and Activation 2

2.2 PSSPs ith $edicated unctions -0

2.2.1 Se"uencing PSSPs -1

2.2.2 5he /;&


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-.-.2 Se"uencing &perations 2

-.-.- %ocal +ontrol &perations )

-.* Program lo &perations 66

-.*.1 >umps ithout a !eturn 66

-.*.2 >umps ith a !eturn 6)

-.*.- !?5, N&P, and 8%5 69

-. +oding ?(ample 63

* 'uilding a System )1*.1 'us Structures )1

*.1.1 Nonapportioned 'us Structures )2

*.1.2 Apportioned 'us Structures ))

*.1.- 'ilateral +ontrol 'us 90

*.2 Apportioning 9-*.2.1 Sitches 9-

*.2.2 Sitch +ontrol 9

*.- &perating System 96

*.-.1 +ontrol of the 'us Structures 9)

*.-.2 'ooting, ?(ecution, and 5ermination 93

*.-.- /;& System 93

*.-.* Security and Stability 3)


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correspondence to csy#esCPSSPsystems.com.

/ tried to avoid unnecessary Bargon ithin the te(t and #ept the e(planations simple. 5here is a lot

of repetition in the presentation of the concepts, especially hen the concepts occur ithin a different

conte(t. 5his is done purposely, in an effort to tie all the concepts into a coherent hole. 5here is a

glossary and an inde( at the rear to assist the reader.

T1

1

Purpose and Overviewecentralied processing units are the name given to the devices designed to replace the central

processing units used in computers today. A multitude of decentralied processing units areused to collectively handle the functions ithin a computer no handled by one or more central

processing units ith associated memory. 8ereafter, these devices ill be referred to as PSSPs. 'efore

e(plaining hat PSSPs are, and ho they or#, it is orthhile e(ploring some of the problems the

computer industry is encountering in its attempts to design better computing machines. Attempts to

find solutions for these problems led to the development of PSSPs.

1.1 Increasing Complexity and Concentration

?ver since the building of the earliest computers, the search has been on to find ays of increasing

the throughputDthe amount of or# that can be done in a given amount of time. =ost efforts have

succeeded to some degree, but the struggle continues as tas#s increase in sie and comple(ity and

demand ever greater computing poer. 5he future of computing machines re"uires an increasing vista

of capability as humanity e(pands and see#s to use them as tools to understand and master the

physical realm. 5his struggle to increase throughput is leading to systems of such comple(ity thatunderstanding them is beyond the capacity of most people.

@hy are computing systems becoming so comple(E =achines evolve to fill an evere(panding set

of e(pectations. =any machines have evolved this ay. 5he first cars ere very simple devicescompared to cars of today. So much more is e(pected no. +omfort, ease of use, safety, and lo

environmental impact are features of todays cars, and the comple(ity has increased accordingly.

5here are many other e(amplesDtelephones, radios, refrigeration unitsDeven simple things, such as

car #eys and cloc#s. /n the beginning, computers ere intended as calculating machines, but they have

become capable of such a variety of functions that they are no ubi"uitous ithin our culture.


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D

2turned into or#able solutions, e came to accept these solutions as sacrosanct. @e may oe

reverence to the original concepts and theories, but solutions need to bend to the technologies of the

time and ma#e use of the capabilities ithin the industry.

1.1.1 Centralized Processing and Control

%oo#ing bac# at the beginning, the original pioneers of computing machines correctly led us

believe that these devices needed certain elements to function as computing machines. =any no refer

to these elements as F7on Nuemann architecture,G even though others came forard ith the same

ideas. !egardless of ho deserves credit for it, the concept that all computing machines must have

these essential elements has become so ingrained that e no longer even thin# about it. 5he original

concepts are solidH nobody can find flas in them. /t is ho e apply the concepts that e need to

e(amine more closely.

5hat processing, control, and memory are essential elements of computing machines is idely

accepted and understood. Some people believe that /;& elements belong ith the other three, but for

this discussion, they ill be momentarily set aside and added later. +ost and manufacturingconstraints, at the time the first machines ere built, led to compromises as to ho these elements

ould be incorporated into the design. +ontrol and processing ere implemented ithin a control and

processing unit, hich today is referred to as the central processing unit. =emory as #ept separate

from control and processing e(cept for a small set of registers located close to processing. &ver the

years, the +P4 became increasingly poerful and memory as e(panded to evergreater "uantities to

accommodate the processes the +P4s had to handle.

5oday, the machines are basically built the same. 5echnology and throughput have vastly

improved, even as overall costs of the systems have decreased. Processing and control is stillcentralied, and memory is treated as a resource to serve the needs of the +P4. ?fforts have been

made to begin the decentraliation of processing and control, but this effort has not progressed far.

5remendous efforts are being made to build systems ith multiple +P4s. Some are designed so that

each +P4 has its on set of resources, hile others use cooperative methods to share resourcesamongst the multiple +P4s. All of these efforts are increasing comple(ity and yet failing to come up

ith real solutions to the problems standing in the ay of all but modest increases in throughput.

1.1.2 The Bottleneck

5he difficulties preventing substantial increases in throughput have come to be #non as the F7on

Nuemann bottlenec#.G =emory has been #ept separate from processing and control, and conse"uently,

the need remains for the data and code to transit bac# and forth over the bus structures. ?ven hen the

+P4 #eeps fre"uently used code and data nearby for rapid access, a tremendous amount of system

resources is needed to #eep it organied and easily available.

$irect memory access, caches, pipelining, virtual memory, !/S+ architecture, and other methods

have all sought to overcome the problem of separating memory from processing and control. 5hey have

succeeded in increasing throughput to some degree, but none has solved the problem presented by

#eeping the memory separate from processing and control. Some attempts to overcome the bottlenec#have done so by moving portions of memory closer to the processing element. 5he solution definitely

seems to lie in that direction, but for some reason e cant overcome our bias against memory.

PSSP Systems-@hy do e thin# memory is different from processing and controlE /ts function is different, Bust as

the function of processing is different from the function of control, but is the value of memory less

than processing and controlE =emory is treated as if it is merely a resource of processing and control,

and yet the pioneers of computing clearly indicated that all three elements ere needed. Never did

they indicate that memory as the lesser element of the three, or that it as there to serve the needs of


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processing and control. @hat if processing and control as treated as a resource for memoryE @hat if,

instead of trying to get memory closer to processing and control, an attempt as made to get

processing and control closer to memoryE 5hese are serious "uestions, not hypothetical entertainment.

@hat if control, processing, memory, and even /;& ere combined to achieve full integration of all the

essential elements of computingE

1.1.3 Vulneraility

@ith the increasing comple(ity of the systems comes increasing vulnerability. System

vulnerability comes in many forms, including susceptibility to malicious or inade"uately designedcode, difficulty understanding the interactions beteen comple( components or code, possible system

failures because of so many comple( interactions, and the difficulty of training personnel to handle the

comple(ities of such systems. /t seems that as comple(ity increases, so does vulnerability.

At odds ith this vulnerability is the need for reliability ithin systems as they handle

increasingly important functions ithin our culture. 5he systems e design and implement shouldreach the highest plateau of reliability and robustness. ?(traordinary efforts are made to increase the

reliability of systems, but it alays comes at great e(pense. 5he trend is going in the rong direction.

/f our efforts fail to increase system reliability ithout raising the cost, e need to rethin# hat e are

doing. 5he need for reliability ill increase as computers are integrated into systems that are

themselves increasingly comple(. System failure is becoming less tolerable, contrasting a reality that

gives us the increasing possibility of failure hich e are e(pected to accept as normal.

5he cost of a system includes, among other things, the original cost associated ith the purchase,and the cost associated ith maintenance and recovery from system failure. @hile the original cost of

systems is actually decreasing hen measured against throughput, this is not so for costs associated

ith maintenance and failure recovery. 5hose costs are increasing rapidly as the comple(ity of

systems increases. +omple(ity is a natural component of groth. As products are refined to ma#e

them more responsive to needs and more efficient, increased comple(ity is usually one of the results.

8oever, at some point, comple(ity fails to meet our needs or provide greater efficiency. 5hat point is

reached hen failure occurs too often, at too great a cost, or ith too great an impact.

@hen systems fail, e usually revert to simpler methods, at least temporarily. Perhaps a balance is

attainable beteen comple(ity and simplicity. Perhaps a desirable goal in our engineering efforts is

simplicity of design, function, and use. 5he notion that any Bob can be reduced to a series of simple,

repeatable steps that can be done by simple devices can be applied to computing machines. Perhaps

computing machines can be reduced to simple redundant components, each doing a small part ingetting the Bob done.

1.1.! "imits

or many years, scientists and engineers have been pushing the limits of ho fast electronic

circuits can change from one state to another state. Astonishing increases in throughput have been

*achieved, and still more are attainable, but ho much is it costing, and isnIt there a limitE +osts in

material, research, and manufacturing techni"ues, as ell as the cost of system failure and even one

persons disgust hen their +P4 malfunctions, are all related, even though they are not comparably

measurable in economic terms. 5hey are the results of the search for greater speed through comple(ity

and centraliation.

+urrent research, collectively costing our culture billions of dollars, see#s to have computationsoccurring at the speed of light. @hile interesting, even fascinating, is it practical as a goalE @hat isactually being sought is increased throughput, the ability to get more or# done in a given amount of

time. $istributed computing, parallel designs, and other methods that spread the or#load seem to

offer more promise in increasing throughput at a reasonable cost. Problems e(ist in synchroniing the

efforts of multiple systems or +P4s or#ing on the same problem and many resources are e(pended

in such efforts. Successful solutions usually come hen the problems are disassembled into a set of

smaller, simpler problems that can be or#ed on independently.

5he concentration of processing and control into one or a fe places seems to have created a host

of problems ithin our system designs. +P4s are so poerful and fast no that there is a problem


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ith e(cess heat. 5his causes the need for special designs or cooling devices and the result is even

more comple(ity and increased possibility of component failure. =emory is still separated from and is

much sloer than processing, hich necessitates special system additionsDanother added comple(ity.

/ncreased speed is sought at great e(pense and effort, and is usually achieved through greater

comple(ity. 5he increasing comple(ity increases the rate of system failure and costs are rising as a

result. Perhaps there is a better ay to thin# about the problems. Perhaps there is a need to rethin# the

original design constraints to fit the manufacturing capabilities of modern times.

5he concentration of processing and control ithin hardare designs is mirrored in theapproach used in the design of operating systems. /ncreasingly comple( operating systems are

being designed to deal ith the hardare and the applications designed to run on it. 5rying to

design softare that ill control the systems and is capable of handling all situations that could

arise has only led to even more comple(ity and a tremendous e(penditure of system resources.

@hile the attempt has not completely failed, it has not been successful either, as system failureand vulnerability have not been eliminated.

+oncentrating computing resources, hether through hardare or softare, is the rong

direction in hich to e(pend our efforts hile trying to design better systems to increase

throughput. !eal orld systems, natural or manmade, that fail the least and achieve the most,

seem to have plurality, or redundancy, in their design. ?(amples of this abound. &ne ant is easily

ignored, but a nest of ants is not. &ne tree does little to affect the environment, but the effect of a

forest is distinct. &ne seep ith a broom barely leaves a trail, but repeated seepings clean thefloor. &ne man couldnt build a pyramid in his lifetime, but a thousand men could. A Bourney on

foot begins ith the first step and can only be completed by stepping repeatedly until the tas# is

done. A nation ruled collectively prospers more than a nation ruled by one. +anIt these analogies

also be applied to our system designsE

/t is true that concentration of resources or poer has benefits hen applied to the right situation.

8oever, there is an inherent vulnerability and ea#ness in such situations and there is usually

multiplicity of some resource at the disposal of the concentration. A general is bac#ed up by his

troops, but if he is disabled, the troops have no leader. A tree has a multiplicity of roots and branches,

PSSP Systemsbut it is easily overcome hen an a( is ta#en to the trun#, the one point here they all converge. A

netor# of client computers becomes useless if the server goes don.5hese analogies may seem silly, but the point is all too often overloo#ed hen systems are

designed. =ust ne designs alays see# to concentrate more speed, poer, and control into a central

location instead of diffusing or distributing it throughout a systemE 5o design systems ithout the

concentration of resources and poer is to ma#e them stronger and more robust. /f systems have

multiplicity and redundancy ithin their design, then the failure of one part leaves the others still

operating. !edundancy and multiplicity are more easily achieved ith simplicity, and all three

attributes are steps in the right direction, leading aay from the concentration of processing poer,

and the vulnerabilities inherent in such an approach.

1.2 #ecentralization and Integration

5here are several system designs that are referred to as decentralied. 5he term has been loosely

applied to almost any system ith more than one +P4. &ne system that is tal#ed about, but not yet on the

scene claims to have over one million +P4s spread out in the design. /t certainly sounds decentraliedDbut hat about integrationE Segregation is an accurate term to use hen referring to current systems. 'ythis / mean that some of the computing elements are #ept separate from others. or e(ample, a system ith

a +P4 contains the elements of processing and control in the +P4, and there ill be at least a fe registers

close at hand. 8oever, if the hole design is loo#ed at, it ill be seen that the main memory is separated

from processing and control. %oo#ing at it from the point of vie of memory, the "uestion might be as#ed,

F@hy isnt there a potential for processing close at hand, here it is neededEG

5his point of vie has provided the impetus for the development of the design presented in the

rest of this boo#. =emory consists of a multitude of addressable units, all connected to a common

system of buses. /t is already decentralied, as much as possible, e(cept for the fact that each memory


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unit is concentrated into a series of bits, the basic data sie ithin the system. %et us alter the design of

a system by ma(imiing the decentraliation of the processing and control elements. At the same time,

let us fully integrate these three elements so that they are spread throughout the design as small units,

each capable of handling one basic datasied chun# of bits, and each capable of handling one tas#

related to processing or control. urthermore, let us ma#e these individual units programmable, so e

can periodically change hich tas# they do. %et us also integrate the /;& into the design so that

herever e have control, processing, and memory, e also have /;& capability. @hat e end up ith

is hat / refer to hen / spea# of decentralied processing units.A more e(act description of ho they might be constructed and used to build a system ill be

given in the pages that follo. 'efore getting into those details, let us e(plore hat a system

ould be li#e if it ere built of such devices and ho e might set things up so multiple

processes could be run simultaneously ithin the system. 5ry to see the big picture before

attempting to understand the small, but important, details. @e ill begin the e(ploration by givinga more precise definition of a PSSP.

A PSSP is a combination of circuits that are separated into to sections. &ne section is loaded, or

programmed, ith an opcode that comes from a set of opcodes. 5he other section holds one related

operand. 5he section holding the operand can also do some processing of that operand, alone, or in

conBunction ith another operand. ?ach PSSP is connected to every bus in the system, but each bus has

a different purpose, and the connection to each bus may be different. ?ach PSSP can be activated,

6hich means to be turned on for some purpose. 5he PSSP can be activated as a hole, or the section

holding the operand can be activated separately. /f a PSSP is activated as a hole, its behavior ill be

determined by the opcode it holds. /f Bust the section holding the operand is activated, its behavior ill

be determined by the opcode held in some other PSSP.

No let us imagine a process that has been implemented ith a series of instructions that follo an

algorithm. 8ere e use a simple process to envision its implementation ith the PSSPs. At this point, dontbe concerned ith ho the opcodes accomplish their functions. /magine that there are PSSPs that can

implement the functions as instructions to carry out the algorithm. No let us ta#e the data and instructions

as listed belo and put them into a series of PSSPs, one after another. ?ach PSSP can hold one opcode and

one operand. 5he opcode goes into one section of the PSSP, and the corresponding operand goes into the

other section. 5he operand can be data or an address. /f more space is needed to hold e(tra data, oroperands, use some of the PSSPs that precede the group of PSSPs holding the opcodes.The Task

'egin ith to numbers

Add the to numbers

?nd ith the to numbers and a result

The $lgorithm

Storage for the first number

Storage for the second number


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116 8%5

The ao%e code is ho& it &ill look e'ore processing. $'ter processing addresses (12) 111) and 11! &ill

contain the numer 12

@hen e are all set up, let us proceed to activate the PSSPs holding the instructions, or opcodes,

one at a time, starting ith the first in the series, beginning at address 110. As each is activated, it ill

perform one little part of the process, its part being the particular opcode that it holds.


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1.2.2 $pportioning

5he to preceding sections shoed, ithout many details, ho a process ould be implemented

ith a group of PSSPs. +omputers run processes in a sort of timesharing arrangement. ?ach process

ta#es a turn using the resources of the system hile all other processes ait their turn. 5he +P4

handles this timesharing very "uic#ly, and to a user, it seems as if many things are happening at once,

but this not so. Advanced systems, systems ith multiple processors, do run processes simultaneously.

8oever, such arrangements are e(ceptions and do not represent normal computing.

A system built of PSSPs ill run numerous processes simultaneously as an ordinary part of itsoperation. 5his is hy the system is designed as it isDto achieve a tremendous increase in throughput

by spreading the or# among numerous processes, running simultaneously. &ne aspect of this

increase in throughput is to decentralie the processing and control to the ma(imum e(tent, to spread it

evenly throughout the entire system. Another aspect is the full integration of memory and /;& ith

processing and control. 5hese to aspects account for the development and use of PSSPs ithin thesystem. 5he third and final aspect is called apportioning. Apportioning is the act of dividing the

resources of the system into small sections of the sies needed for the various processes running ithin

the system. or instance, suppose a system has a total resource base of 16 =egs of PSSPs, and has four

different processes that need PSSP space. Process 1 needs - =egs of PSSP space, process 2 needs 00

#ilos of PSSP space, process - needs 1 =eg of PSSP space, and process * needs 100 #ilos of PSSP

space. After apportioning, there ill be four sections of those sies and a fifth space consisting of all

the remaining PSSPsD11.* =egs. 5his seems straightforard and similar to ho memory is handledin systems that e already understand, but it is more concrete and a lot less comple( hen dealing

ith a system built of PSSPs.

Apportioning is accomplished by actually separating a section of PSSPs, both physically and

logically, from all other sections of PSSPs. 5he separation is physical because there are apportioning

sitches that actually sever the various buses, causing a section of PSSPs to become physically

isolated. 5he section of PSSPs is logically separated from other sections because it cannot address any

PSSP outside of the section that it is isolated in, nor can it send data along the data bus to anyhere

outside its on section. 5he isolation is physical, logical, and it is continued for as long as the process

is running in that section.

PSSPs in one apportioned section cannot affect the PSSPs in another section that is apportioned

separately. A process in an apportioned section can only address PSSPs ithin the section that it is a

part of and can only send data along the data bus to another PSSP ithin the same apportioned section.5he &S is the only process that can set the apportioning sitches used to sever the buses, but the

isolated processes cannot affect the &S either, because they are in different apportioned sections,

isolated from each other. /f a programming error occurs, or a malicious attempt is made to influence

the system, this isolation ill protect the system. ailure or corruption of a process can still occur, but

the effects are isolated to that section of PSSPs. 5here is no possibility that the problem ill spread to

the rest of the system.

/n the preceding paragraph, / stated that a PSSP couldnt affect a PSSP outside of its apportioned

section. 5his is true, e(cept for PSSPs being used by the &S. 5he &S must be able to reach into any

PSSP Systems

3part of the system, be able to ta#e control, if the need arises. 5herefore, several opcodes are privileged

and only to be used by the &S. Part of the process of loading code into an apportioned section ofPSSPs is to perform a validity chec# on the code being loaded. +hec#s verify that the code is a validopcode and not a privileged instruction.

5he /;& system provides a means of communication beteen processes. 5he /;& system is much

more e(tensive in a system built of PSSPs. ?very standard PSSP has the potential to access the /;& bus.

urthermore, the /;& bus remains hole and undivided at all times, regardless of ho the &S sets the

sitches used for apportioning. 5he /;& system is responsible for facilitating data flo beteen

processes. A global control bus reaches every PSSP in the system, but it handles the global control

signalsDnot data or addresses. or a process to reach another process it must use the /;& bus, there are

no e(ceptions, e(cept for the &S and its control over the system. All data coming into or leaving a


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process, an apportioned section, must do so via the /;& bus. @hen the &S is loading the process it

ma#es use of the secondary address bus, the data bus, and the au(iliary data;control bus, but once the

process begins se"uencing, communication beteen it and any other process, including the &S, is

done via the /;& bus.

1.2.3 +imultaneous Processes

@e have seen ho a process is run in a series of PSSPs, and ho a process can be isolated ithin

the system. %et us complete this picture ith a fe more details, to sho ho a completed system can

have multiple processes running simultaneously. @e ill begin ith a fe instructions that are uni"ueto this design. 5hen e ill tal# about the /;& system and the &S. inally, e ill go through bootup

to the loading of processes, and conclude this part of the boo# ith all these processes running

simultaneously. @e are loo#ing for the big picture, the overall vie, so that e can better grasp the

details as they come to us later.

?very process in an apportioned section ill have a series of PSSPs that handle the se"uencing ofthe program code in the PSSPs. 5hey are calledsequencers orsequencing PSSPs. +ollectively, they are

called thesequencing stack. 5hree opcodes are used by the PSSPs in the se"uencing stac#, but only

one ill be presented at this time. 5he S?J instruction, an opcode, ill reside in the section of a

se"uencing PSSP that holds the opcode. /n the other section of the same PSSP is the address of the ne(t

PSSP to be activated. ?arlier in this chapter, during the e(ecution of the simple process, the PSSPs ere

activated one at a time to accomplish the tas#. 5he se"uencer does the activating by se"uentially

putting the address of each PSSP onto the primary address bus.5he se"uencer, along ith the rest of the se"uencing stac#, behaves li#e the program counter in a

conventional computer. ?very process has a se"uencer ithin its apportioned section to handle the

activationDthe se"uencingDof its PSSPs. 'eginning the process, halting the process, Bumps, and

returns are all handled by the se"uencing stac#. 5here is even a set of control lines dedicated to the

function of se"uencing ithin each process. 5hey are called thesequence control lines, and they are

local to the process. 5he &S uses a global control line to enable or disable the se"uencing in one or

more processes. 4se of this control line, the sequence master control line, gives ultimate control over

all se"uencing to the &S, but the &S does not do the se"uencing for any process e(cept itself.

An opcode reserved for use by the &S is the =&7+ instruction. 5he mnemonic stands for Fmove

code.G 5he &S uses this instruction to load a process into an apportioned section of PSSPs. 5he use of

this opcode causes the contents of the processing section of a PSSP, that section that holds the program

10data, to be put onto a set of data lines that ill deposit the data in the control section of a different PSSP.

5he control section of a PSSP is the section that holds the opcode, and the only ay to get the opcode

into it is ith the =&7+ instruction. 5he code and data are not mi(ed. 5hey are #ept in different

sections of a PSSP, but hen code and data are removed from a secondary storage device, it is all mi(ed

together. As in a conventional system, it is stored as a series of bit values, and code is indistinguishable

from data. 5he &S sorts out hich is data and hich is code, and then uses the =&7+ instruction to put

the code into the control sections of the PSSPs that have been apportioned for that process.

5he only other opcodes that need to be e(amined at this time are the >&!? and >/!? instructions.

>&!? is used to output data onto the /;& bus, and >/!? is used to input data from the /;& bus. %i#e the

S?J instruction, these instructions are selfactivating, meaning they automatically e(ecute their

instruction ith each pulse of the cloc# signal. 5he >/!? instruction is slightly different from the S?Jand >&!? instructionsDit is the only one of the three that cannot be disabled. 5he SJ= control line isthe control line that can disable the S?J instruction. A different control line can enable or disable the

>&!? instruction, but there is no similar control line for the >/!? instruction.

5hese to instructions, >&!? and >/!?, are the gate#eepers beteen the /;& bus and a process. /n

the processing section of the PSSP holding one of these instructions is a number that identifies the /;&

process the gate#eeper is atching for. 5he PSSP serving as a gate#eeper atches the /;& bus for this

number. @hen it shos up and the gate#eeper also gets a signal that it is an /;& routine identification

number, a Bump ill occur to an /;& routine that handles the input or output. 5he PSSP serving as the

gate#eeper sends the address of the routine to the se"uencer and the se"uencer begins se"uencing at


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the ne address. A return from the routine is e(ecuted at the end of the /;& routine.

5his e(planation leaves out many details of ho and hy it happens this ay. All of the details ill

come later in the te(t. At this point, it is only necessary to realie that every process has PSSPs

programmed ith these to /;& instructions, Bust as every process has its on se"uencing stac#. 'ecause

each process is isolated in its on apportioned section of PSSPs, it needs some ay to communicate ith

the other processes. ?very process must send or receive data if it is a meaningful process, and it ill use

the /;& bus for this purpose. Any data that enters or leaves the process must do so via the /;& bus, and

these to /;& instructions serve as the gateay beteen the process and the /;& bus.

5here are many details to present to the readers ho are unfamiliar ith this system. 5he details

sho a system very different from conventional systems. /t is not necessary to completely understand

and memorie all of these details at this time. All ill be repeated as they are needed, and your

understanding of the system ill gro as you progress through the te(t. Ne(t, the &S ill be brieflydiscussed, and it ill become obvious that it is very different from most conventional operating systems.

1.2.! The ,perating +ystem

5he most noticeable thing about the &S in a PSSPbased system is hat it is not doing in

comparison to a conventional &S. ull integration and decentraliation of the computing functions

ithin the PSSPs of the system, along ith the ability to isolate processes ithin apportioned sections,

frees the &S of the to most burdensome tas#s of a conventional system. irst, the operating system is

no longer in control of a +P4, so it no longer needs to ration every moment of the +P4s time. /t stillrations the systems resources but this is done on a much higher level, and there is no +P4 involved.

Secondly, the &S is not involved in e(ecuting the code of each process. ?ach process e(ecutes its on

PSSP Systems

11code ith its on se"uencer and PSSPs. 5hese to tas#s account for the bul# of the time used by a

conventional operating system, and they are eliminated in a system built of PSSPs.

At its highest level, the &S controls the bus system. Part of that tas# is configuring all of theapportioning sitches used to sever or unite the bus structures. 5his enables the &S to ration the apportioned

sections among the processes. Another part of that tas#, the most important part, is ta#ing care of the

/;& bus. 5he &S loads a process into an apportioned section and then releases the process to start

se"uencing on its on. 5here is no need for the &S to concern itself ith e(ecution of the process.

?ach process has the resources it needs, e(cept for the ability to communicate ith other processes.5he only reason for the &S to interfere ith the se"uencing ithin the process is if it should need to

halt the process temporarily so it can ma#e use of that portion of the bus system.

All the isolated processes run simultaneously ithin the system and their greatest need ill be

interprocess communication. 5his is the primary function of the &SDto facilitate and control all

communications beteen processes via the /;& bus. 5o ma#e use of the /;& bus, a process needs to use

the /;& gate#eeper instructions and the /;& routines that ere constructed by the &S. ?ach process, as

it is loaded, informs the &S of its /;& needs. /nsofar as it is possible, the &S accommodates the process

by constructing the necessary /;& routines and inserting them in the process, along ith the

information necessary for the process to use them.

/n this type of system, here the three basic elements of computing have been fully integrated anddecentralied by using PSSPs, the /;& system has also been fully integrated and decentralied. /n aPSSP system, the /;& system is much more than an interface beteen the system and the outside

orldDit is the interface beteen all processes ithin the system, including those that deal ith the

outside orld.

5he /;& system is composed of the /;& bus, the softare that controls it, and the capability of each

PSSP to serve as an interface beteen a process and the /;& system. 5he /;& bus is connected to almost

every PSSP in the system, and every PSSP connected to it has the potential for handling input and

output. urthermore, the &S, relieved of the burden of controlling a +P4, ill spend most of its time


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handling the /;& system, providing each output process time to use the /;& bus.

/ have spo#en of the &S and the /;& system as if they are to different and separate processes, but

this is not an accurate depiction of the situation. 5he need for speed ithin the /;& system is sufficient

reason to have it run in an autonomous manner, but it ill still need to be closely integrated ith the

&S. /t might even be more accurate to say that the /;& system is the &S, and that all other &S

functions become secondary to the needs of handling the /;& bus. rom the moment the system begins

operation, the /;& is given priority and is accounted for in the loading and operation of every process.

@hile each process can run autonomously ithin their apportioned section, ithout /;& support theybecome meaningless. 5he /;& system literally binds everything together.

1.2.- Booting) "oading) and Termination

5he boot process for a PSSP system is similar to that of a traditional system, but there are some

crucial differences. /n many respects, a PSSP is li#e a simplified +P4 in that it performs elements of

processing and control. 4pon activation, a PSSP ill attempt to e(ecute the opcode contained ithinits control section, but this activation usually re"uires the address of the PSSP to occur on the primary

address bus. 'ecause of this, one of the first things that must occur in the boot process is that the SJ=

control line must go high to disable all possible se"uencing ithin the system, e(cept ithin the boot

12process. 5he /&% control line must also go high to disable any possible activation of the /;&

gate#eeper instructions. Along ith control over the control lines, control must be e(erted over the /;&bus and the apportioning sitches. 5his occurs hen poer is first applied, to prevent random

occurrences of conflicting conditions that might interfere ith the boot process.

PSSPs used for the boot process are li#e standard PSSPs, e(cept the opcodes ithin them are preprogrammed

before system installation and unchangeable once installed. %i#e the !&= chips used for

booting in a conventional system, these PSSPs contain the code that get the system started initially.

%i#e a conventional system, a PSSP system needs to establish the /;& system and then begin loading its

code from a secondary storage device. /n addition, many system components need chec#ing, and datastructures need to be established for a fully functioning &S. &nce the components of the &S have been

established other processes can be installed ithin the system.

@hen the &S receives a call to assign resources to a process, it must establish the sie of the

process so it can apportion a section of PSSP resources for that process. or loading the process, the

&S needs to configure the apportioning sitches so that the buses are temporarily available to senddata to the nely apportioned section, and then reconfigure them to isolate the process ithin its

section. 5his means the &S may need to stop se"uencing in one or more processes temporarily so that

the bus sections apportioned for those processes can be used to move data to the section used for the

ne process. After loading the process, the buses ill be surrendered bac# to the processes that needed

them, and the ne process ill be isolated ithin its apportioned section.

Part of the loading process is ascertaining hat is code and hat is data, and then chec#ing the

code for instructions that are restricted for use by the &S. An analysis of the /;& needs of the process

is also done, along ith construction of the /;& routines. /nformation about output routines is passed to

the /;& system, and time allotments are made for these routines ithin the /;& systems timesharing

scheme.

After the process is fully loaded and isolated ithin its apportioned section, the &S ill set the

SJ= control line in that section lo. @hen this line goes lo, it permits se"uencing to commenceithin the process. 5he process is completely isolated and se"uences on its on once this happens,and the only ay it can communicate ith anything outside itself is by sending messages via the /;&

system.

Similar to the loading of one process is the loading of all other processes, the only limitation being

the resources of the system. Assuming there are enough apportionable sections of the sie needed for

FKG number of nonsystem processes, at the end of loading FKG number of processes, there ill be

FKG number of processes, plus the &S processes, running simultaneously ithin the system. All

processes ill be running independently of each other e(cept for the flo of messages and data

beteen them, hich can only occur via the /;& system.


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Process termination is normally accomplished ith the process running its termination routine.

5his routine sends a signal to the &S that the process is finished and can be terminated. After sending

this message to the &S, the process ill go into a N&P loop hile it aits for the &S to set its section

of the SJ= control line to the correct state to disable se"uencing ithin the process. &nce this is done,

the &S ill then ta#e the necessary steps to recover the PSSPs used by the process and remove any

references to it from the &S system. 5his is not the only ay a process can be terminated, but it is the

normal, or preferred, method.

5his completes the overall vie of a system built around the use of PSSPs. 8opefully, the readerno has a good idea of hat the system is capable of, and ho it is accomplished. $etails ill follo

PSSP Systems1-in the rest of the boo#, beginning ith a more indepth loo# at the PSSP, since its capabilities and

design are at the core of the systems design. A thorough understanding of the PSSPs ill facilitate anunderstanding of the rest of the components ithin the system. 'ut before going on, a recapitulation of

this chapter is provided.

PSSPs enable a system to overcome the limitations and problems associated ith the increasing

comple(ity and centraliation of current system designs. PSSPs are designed to integrate processing,

control, memory, and /;& into individual units. A multitude of the individual units is used to

collectively accomplish all computing functions ithin the system. @ithin these devices, the code

and program data are #ept separate and only the &S can move the code. A bus system that can bedivided into sections enables an apportioning process that allos programs to run simultaneously

and independently ithin the system. +ommunication beteen these simultaneously running

programs is facilitated by an /;& system that reaches into every portion of the system. +ontrol of the

/;& system is the primary function of the operating system, hich also handles the apportioning of

system resources.

1

2

PSSPS Funtion and Desi!necentralied processing units handle all of the processing, control, memory, and /;& functionsneeded ithin a computer. No single PSSP is more functional than any other PSSP, but theymay have different functions. 5he PSSPs or# together to handle all the functions a central processing

unit handles in a conventional system. @hile some PSSPs ithin the system are dedicated to one

function, this is not so for the maBority. =ost are general purpose in design and are able to handle

almost any of the functions needed ithin the system. 5hey are designed to have the same capabilities

and the same connections to the buses.

@ithin this te(t, e(cepting the modified PSSPs that are readonly and used for booting the system,

there are three basic types of PSSPs. =ost abundant are the general purpose PSSPs referred to as

standard PSSPs. 5his type can handle any operation e(cept se"uencing and /;& gate#eeper functions.

5he other to types are specialied PSSPs dedicated to particular functions that standard PSSPs cannot

handle. &ne is used for the three se"uencing instructions, and the other is used for the to /;&gate#eeper instructions. 5he PSSPs that are modified to be readonly and used for booting are Bust li#e

the three basic types, e(cept that their code, data, or both may be in readonly form.

?ach PSSP is designed to hold one instruction from the set of instructions. 5he instruction is

programmed into the PSSP ith softare, hich means the operating system loads the code into the

control section of the PSSP. A PSSP can handle only one instruction at a time. 5o handle a different

instruction, it must be reprogrammed ith the ne instruction. ?ach instruction may have one

operand, to operands, or no operand at all. ?ach instruction ill also have a result. 5he result can bea piece of data that is held until it is needed, or it can be a control action, such as setting a control line

high or lo. ?ach PSSP can hold one operand before the operation. After the operation, it may hold the


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original operand or the result of the operation, if the result is a data obBect.

?ach PSSP is programmed to do its part ithin a process. Some are used to fully activate other

PSSPs, hile others are used to perform an operation on one or to operands. 5hey may move data

around, cause a Bump in the se"uencing of the process, atch the /;& bus, or provide an element of

control for the process or system. ?ach PSSP ill do its part, hen it is activated, to fulfill the tas#

assigned to the group.

&nly one standard PSSP is fully active at any particular moment ithin a process. 8oever,

the selfactivating PSSPs, hich are used for dedicated tas#s, ill be fully active at the same timeas the standard PSSP. /n addition to PSSPs that are fully active, other PSSPs may only be partially

active. 5he differences beteen a fully and partially activated PSSP ill be e(plained in detail

after PSSP design has been presented. /t is important to realie that in any particular group of

PSSPs being used for a process, a tremendous amount of activity is going on. @ithin a system,

here many processes are running simultaneously in different apportioned sections, many doensof PSSPs are active to some degree and participating in the or#load. 5his is a normal level of

activity for a PSSP system.

D162.1 +eparation o' Code and #ata

?ach PSSP is composed of to sections, the processing section, and the control section. 5hese to

sections are different in structure and function, but they do share some common characteristics. ?ach

section is dependent upon the other, but they can also act independently of each other at times.

5ogether, the to sections ma#e up a PSSP that is capable of handling a predetermined "uantity of data

during one e(ecution cycle.

5he processing section re"uires direction from its control section as to hat operation it shouldperform, but it can also be directed to read or rite data hen receiving control signals from the

control section of a different PSSP. Similarly, the control section directs the processing section to ta#e

an action, and then that processing section can directly influence the control section of a different

PSSP. /n all cases, the control section of a PSSP initiates the action or series of actions. 5his is alaystrue, regardless of the type of PSSP involved.

PSSPs must have certain capabilities in order to function as they are e(pected ithin a system of

PSSPs. 5hey must be capable of performing as memory and holding their data until it is needed. 5he

processing section of every PSSP has a latch for each data bit it must hold, and its control section has a

latch for each bit of opcode it must hold. ?ach PSSP must possess a minimal set of processing and

control capabilities so it can manipulate the program data or perform control functions. &nly the

processing section has processing capabilities, and only the control section has the capability to handle

the various aspects of control needed ithin the system, process, or PSSP.

All PSSPs are referenced ith a uni"ue address. All are logically organied so that their addresses

are linearly arranged. 5he first address is folloed by the second, folloed by third, all the ay

up to the highest address. ?ach address refers to the entire PSSP, but it can be used to activate

either of the to sections of the PSSPDthe control section or the processing section. /f the addressof a PSSP appears on the primary address bus, the control section of that PSSP is activated, hich

in turn activates the entire PSSP. /f the address appears on the secondary address bus, only theprocessing section ill be activated for the reading or riting of data. /n addition, it is possible to

activate the processing section of a PSSP ith any one of the four bilateral control lines of the

bilateral control bus.

?ach PSSP can hold program data and program code. Program data and program code are #ept

separate. Program data can be operands, addresses, or any other data obBect used by the program code.

Program codes are the instructions that tell PSSPs hat actions to ta#e. &ne of the instructions enables

a PSSP to handle program code as program data, but the instruction is restricted for use by the &S.


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&nly the &S can use this instruction to move code into the control section of a PSSP. 4ntil code is put

into a control section it is considered to be data and ill reside in the processing section of a PSSP, or

in secondary storage.

5he program data is #ept in the processing section of a PSSP. 5he program code is #ept in the

control section. No process, e(cept the &S, has access to the opcode bits of a control section, or is able

to change an opcode once it is in a control section. 5his is one of the many advantages of this system

in regards to system security and stability. 5here is a method that is used for output and se"uencing

instructions, hich ill be discussed later, in hich an opcode can be enabled, or disabled, as needed,but the opcode is not really changed.

PSSP Systems1)2.1.1 Processing +ection o' P++Ps

5he processing section of a PSSP handles all processing and storage of data. 5his includes the inputand output of data via the /;& bus. 5he processing section of a PSSP is under the direction of the control

section of the same, or another, PSSP. /n a conventional system, all processing is done in the central

19processing unit, each instruction decoded and e(ecuted as it is brought to the +P4. /n a PSSP system, the

processing is spread out in the system, ith each process e(ecuting instructions as they occur ithin the

PSSPs at its disposal. ?ach PSSP ith an instruction ill e(ecute the instruction each time that it is fullyactivated. /t ill not e(ecute any other instruction until it has been reprogrammed to do so.

System memory is handled by the processing sections of the PSSPs ithin the system. 5here is no

separate memory area, or memory devices, e(cept secondary mass storage devices, such as a hard

dis#. 8oever, it is possible to set aside portions of the PSSPs ithin a process, to be used solely as

storage. $ata, in all its forms, is stored in the processing section of PSSPs. ?ach processing section can

hold one set of bits that represent the basic data sie of the system, hether it is bytes, ords, or some

larger entity. @hile the code in the control section is static until the &S changes it, the data in theprocessing section can be changed by the instruction in the control section of any PSSP ithin the

apportioned section of PSSPs.

5he processing section of a PSSP can be activated by the control section of the PSSP that it is a

part of, or it can be activated by the control section of another PSSP. A processing section

activated by its on control section processes its data as directed by the opcode in the controlsection. 5his activation is referred to asfull activation. A processing section activated by the

control section of some other PSSP is only activated to read or rite data. 5his type of activation

is referred to aspartial activation. ull activation of a PSSP causes the activation of the control

section, and the control section then causes activation of the processing section of the same PSSP.

ull activation of a PSSP can only result from the se"uencer putting the PSSPs address onto the

primary address bus, or from the PSSP being selfactivating. Secondary activation of a processing

section occurs hen the opcode of a fully activated PSSP re"uires the processing section of

another PSSP to read or rite data. /n this case, the data is read or ritten, but it is not processed

in the partially activated PSSP. 8oever, the data in the partially activated PSSP may be needed

for processing ithin the fully activated PSSP that caused the partial activation. Partial activation

is caused by the PSSPs address appearing on the secondary address bus or by a control signal from

one of the to adBacent PSSPs via a bilateral control line.ull activation of a processing section occurs henever aPSSP is activated by its address appearing on theprimary address bus, hich only occurs hen the se"uencer selects that address as the ne(t to receive

full activation. 8oever, in the case of the three selfactivating instructions, full activation is constant

and automatic for PSSPs containing them, if the instruction is enabled. Secondary activation occurs

hen a PSSP receiving full activation by the primary address bus needs to retrieve or store an operand

re"uired by the operation being performed in the processing section. /n other ords, if the fully

activated PSSP needs to retrieve or store an operand, it ill cause partial activation of to other PSSPs.

&ne PSSP contains the address of here the operand is, or here it ill be put. 5he other contains the

operand.


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17/78

deposited into the opcode latches of the control section of the PSSP addressed by the secondary

address bus. &utput from the latches to a bus does not cause any change in the contents of the

20latches. lag signals, generated by A%4s, are sent to the data flo controller, hich ill use

individual bit signals to generate a composite signal that is sent bac# to the control section of the

PSSP via the internal signal flo beteen its to sections.

A PSSP designed for the se"uencing stac# has a processing section that is much less complicatedthan a standard PSSP. or se"uencing, the processing section only needs to hold an address that isincremented or replaced. 5he only operations needed ithin the A%4s of a se"uencing PSSP is to

increment by one or to. lag signals are not needed, and the ' input is only needed for the to

loest bit values. 5he output from the latches can only be put onto the primary address bus, hile

input can only come from the data bus. 5his greatly simplifies the design of the processing section of ase"uencing PSSP.

5here is a group of control lines that can influence the processing section of all PSSPs. 5hey

are called the bilateral control lines, collectively #non as the bilateral control bus. 5hese

control lines ill be discussed thoroughly in the section detailing system bus structures, but a fe

details about them ill be given at this time. 'eteen every PSSP and the to PSSPs logically

adBacent to it, there are to control lines. or each PSSP, there are to control lines going to the

address that precedes it and to other control lines going to the address that follos it. 5hesecontrol lines are used by the fully activated PSSP to partially activate an adBacent PSSP. 5he

partially activated PSSP ill read or rite data used by the fully activated PSSP that sent the signal

on the bilateral control line. 5hese signals go from the control section of the fully activated PSSPs

to the control section of the adBacent PSSPs, and pass to the processing section of that PSSP. 5his

ill become clearer as more #noledge is gained on ho PSSPs handle instructions that have an

indirectly addressed operand.

2.1.2 Control +ection o' P++Ps

5he control section of a PSSP is used for all functions e(cept storage and processing of data. 5he

control sections of the PSSPs must generate all the local and global control signals for the system, for

every process, and each PSSP as it is activated. 5he only e(ceptions to this are the cloc# and poer

signals, hich are autonomous. /n many instances, the processing section ill hold the control

variable, such as the state a control line should ta#e, but it is the control section ta#es the action andsets the control line to the correct state. 5he processing section holds data and does data processing,

but the control section initiates all actions.

5here are three types of control signalsDglobal, local, and internal. ?ach has their on control

bus, or control lines.


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controls the actions of the entire PSSP in hich it resides. As a secondary matter, it may also influence

an adBacent PSSP, or a PSSP elsehere in the apportioned section. /n the case of PSSPs used by the &S,

the opcode may affect global control signals that can affect any part of the system. 5his influence can

only be e(erted during full activation by the primary address bus. %ac#ing full activation, the control

section of a PSSP can do nothing e(cept maintain the condition of a control line, or transmit the signal

from a bilateral control line. /f the PSSP is fully activated, it can directly affect the processing section

of an adBacent PSSP ith a bilateral control line. /t can also directly affect the processing section of

another PSSP by causing an address to be put onto the secondary address bus in conBunction ith asignal on the !;@ control line.

5he opcode latches get their input from the au(iliary data;control bus, hich can only occur during the

programming, or loading, of the PSSPs by the &S. $ata is not usually put onto the au(iliary data;control

bus. 5he =&7+ instruction, a privileged instruction only used by the &S, provides the means to put the

data onto this bus so it can be routed to the control section of a PSSP. 5his is the only ay the opcodelatches can receive data. No other instruction has the capability of affecting these latches.

5he au(iliary data;control bus is used to put the code into the control section of a PSSP only hen

the process is being loaded. @hen a process is running by itself, the au(iliary data;control bus is used

for control signals local to that process. =ore details about this dualpurpose bus, and the other buses,

ill be given later. or no, understand that this bus, the global control bus, and the bilateral control

bus are the only three e(ternal buses ith connections to the control sections of the PSSPs. 5he

au(iliary bus is the local control bus hen a process is se"uencing. 5he &S uses the global control busfor system control. 5he bilateral control bus carries signals beteen adBacent PSSPs for partial

activation. 5he internal bus is the one that carries the control signals beteen the control section and

the processing section of a PSSP.

Normally, an opcode cannot change hile a process is running. 8oever, in the se"uencing stac#,

the PSSPs can sitch beteen an active and inactive state, but this is an e(ception. Also, the >&!?

instruction can be enabled or disabled ith a local control line, but the opcode doesnt really change.

?(cept for these to instances, opcodes are unchanging once the &S has loaded them. or an opcode

to be changed se"uencing of the process ould need to be stopped so that the &S can ma#e use of the

au(iliary bus.

5he number of bit positions in the control section of a PSSP is e"ual to, or less than, the number of

bit positions ithin the processing section of a PSSP. 5he number of bit positions ill also e"ual the

number of bit lines of the au(iliary data;control bus. urthermore, since the bit positions represent thelatches that hold the opcodes, there is a direct relationship beteen the number of bit positions in the

control section and the number of instructions possible ithin the set of opcodes.

5he decoder circuits are the most comple( part of a PSSP. 5hey generate all the necessary control

signals for the entire system, but this is not all done by one PSSP. =any different PSSPs, ithin

different processes and different apportioned sections, or# to generate the correct control signals.

$ecoder circuits must decode the incoming signals and generate the necessary combination of output

signals. /nputs to the decoder come from the opcode latches, the au(iliary data;control bus, the global

22control bus, the bilateral control lines, and the internal signal flo coming from the processing section.

8oever, the number of inputs that need to be handled by any particular PSSP ill depend upon the

opcode it is assigned to e(ecute.PSSP Systems

2-5he input to the decoder from the opcode latchesDthe opcodeDill control the basic functioning of

the entire PSSP hen it is fully activated by the primary address bus. @ithin the opcode itself is the

necessary information to provide control for the A%4s, the data latches, and the data flo controller of

the processing section. 5he information in the opcode specifies hich function the A%4 should

perform, from hich bus the data is received, to hich bus the data should output, hich flag control

lines should be set, or a combination of these. /nformation from the opcode is used in conBunction ith

other data entering the decoding circuits of the control section. or instance, a conditional Bump


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instruction needs information pertaining to the condition of a particular flag control line. or the

instruction to be e(ecuted, the state of the flag control line needs to be ascertained before the correct

signals can be sent to the processing section.

Also providing inputs to the decoding circuits are the local control signals that come in via the

au(iliary data;control bus. 5his bus acts as a control bus once se"uencing has begun ithin the

process, therefore, if the PSSP has been fully activated, the signals on this bus are control signals.

5hese signals are used as input to the decoder circuits and they ill change state hen the PSSP

e(ecutes its opcode. 5hey include flag signals generated in the processing section of a PSSP, the !;@signal used for data transfers, the /;& enable signal used to control the >&!? instruction, and the three

local se"uence control lines. As each PSSP is fully activated, it ill influence, and may be influenced,

by one or more of these signals.

5he global control bus also provides inputs to the decoder circuits, but these inputs only concern

control signals that are global in scope. 5he local process only uses these signals hen it involvessome aspect of shared system resources. or instance, a high signal on the /&! control line, hich is a

global control signal, is a signal to all PSSPs actively using the >&!? instruction that the data on the

/;& bus is the identification number of an /;& process. 5he signal is a global signal, dealing ith a

shared resourceDthe /;& bus. 5hese global control signals are autonomous or generated by the &S and

cannot be influenced by a local process. Some of these signals are set ith instructions that are

privileged to the &S. /n addition to the /&! control line, the global control bus includes signals used

by the operating system for apportioning the buses, the to cloc# signals, the +@? control signal, andthe SJ= control signal.

5he decoder circuits also get signals from the processing section of the same PSSP via the internal

signal flo that e(ists beteen the to sections of the PSSP.


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bus. As its name implies, it has to functionsDone is as a data bus, and the other is as a control bus. 5hese

to functions occur at different times, so there is no conflict ith the bus being used for both functions.

&riginally there ere to separate buses ithin this design, each ith its on function. 5he realiation that

these to functions could coe(ist ithin one bus structure led to the dualpurpose bus.

5he bus is only used for data transfer hile a process is being loaded into an apportioned section

of PSSPs. 5he input for this bus, hile it is being used as a data bus, can only come from the

processing section of a PSSP being used by the &S to transfer data. 5his data is actually program code

being moved from a secondary storage device to the control section of PSSPs being loaded ith code.5he &S ill use the =&7+ instruction to load the code, and the section of PSSPs being loaded ill

not have begun se"uencing yet.

After the code has been loaded, the &S ill permit the process to begin se"uencing. At this point,

the au(iliary data;control bus ill no longer be a data bus. &nce se"uencing begins it ill become the

local control bus. 5he bus as only used for data transfer hile the process as inactive. &nce theprocess is active it ill be used for control signals confined to the process. 5he bus is used for control

signals for as long as the process is actively se"uencing ithin the apportioned section. @hen the

process terminates, the bus ill become inactive until the &S again loads a process into that section of

PSSPs.

&ther than that special use of the au(iliary bus for data transfer by the &S, all data transfers

ithin the system occur on the data bus or the /;& bus. 5he /;& bus is used for data transfers

beteen processes isolated from each other, hile data flo ithin a process alays occurs on thedata bus. 5echnically, it is not possible for a process to recover the same data from the /;& bus

26that it is putting on the /;& bus, so it is not possible to use the /;& bus for data flo ithin a

process. Similarly, the data bus is an apportioned bus, and it is not possible for it to be used for

data flo beteen isolated processes. @ithin a process, the data bus is the only bus used for data

flo beteen PSSPs.5he data bus is one of the apportioned buses. 5his means it is divided into sections, ith each

section being assigned to a process. @hen the data bus is mentioned in relation to a process, it

should alays be understood that only the section of the data bus assigned to that process is being

referred to, not the entire data bus. 5his is important because many processes are running

simultaneously, and each process ma#es its on independent use of its assigned section of thedata bus.

5his is not so for the /;& bus. 5he /;& bus is not apportioned or subdivided in any ay. /t is

hole and complete throughout the system. /t has connections to every standard PSSP ithin the

system, regardless of here the PSSP is or to hat process it is assigned. Putting data onto the /;&

bus is done in a strictly controlled manner. /t is not possible for a process to use it for data transfer

beteen processes, e(cept for hat has been planned. @hen a process is loaded, all of its input

and output needs are ascertained by the &S and must be accounted for ith sections of code that

the &S inserts into the code of the process. 5his is a very important point to #eep in mind. All /;&,

in particular the output, is planned and controlled. 5his does not mean a process cannot decide

hen it might ant to output data, but it does mean that it must as# permission to output data onto

the /;& bus, and then ait for permission to be given. ?ven the &S has to follo the protocols set

up for the use of the /;& bus.5hat covers hat the reader needs to #no right no about the au(iliary bus, the data bus, and the/;& bus. Ne(t come details about the to different address buses and the bilateral control bus. 5hese

buses are used to activate the PSSPs, either fully or partially. &f the three buses, only the primary

address bus can cause full activation. /t is referred to as the primary address bus because it is used to

begin e(ecution of an instruction. 5he secondary address bus is not used ith every instruction, only

ith instructions that have an indirect operand. 5he secondary address bus and the bilateral control

lines can only cause partial activation.

ull activation causes the control section of the PSSP being activated to e(ecute the opcode in its

opcode latches. All opcodes need to be in the control section of a PSSP before they can be activated.


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5here is no ay they can be e(ecuted elsehere. &nly hen data has been put into a control section

does the data becomes code. &nce the code is in a control section, the PSSP of hich that control

section is a part must be fully activated by the primary address bus for the code to be e(ecuted. 5his is

the only ay an opcode can be e(ecuted, e(cept for the three selfactivating, or selfenabling,

opcodesDS?J, >&!?, and >/!?. 5hese three opcodes do not need activation by the primary address

bus or any other bus, but there is a method to enable or disable the >&!? and S?J instructions.

Partial activation refers to the processing section of a PSSP being activated for the reading or

riting of data. 5he processing section cannot do any processing hen it is partially activated. /t canaccept data from the data bus, or it can put data onto the data bus or the secondary address bus. /n the

case of the =&7+ instruction, restricted for use by the &S, data can be put onto the au(iliary

data;control bus.

Partial activation can be achieved by the secondary address bus or by one of the control lines of

the bilateral control bus. Partial activation by the secondary address bus is alays accompanied by asignal on the !;@ control line, e(cept for the =&7+ instruction, in hich case it ill be accompanied

PSSP Systems2)by a signal on the +@? control line. Partial activation caused by a bilateral control line is alays

directed toards one of the to adBacent PSSPs. /t is not accompanied by any other control signal.

5here are four of these bilateral control lines to affect four possible actions by an adBacent PSSP.

/n a conventional system, the address bus is used to select a memory address for reading orriting. 5he selection is alays done by the system +P4 as part of an instruction e(ecution cycle, and

the

29+P4 is alays in control of the address bus. /n a PSSP system, each PSSP is given temporary

control of the secondary address bus. An e(ception to this is the se"uencing instruction that is given

total control of the primary address bus. Not every instruction needs to use the secondary address bus,and in those cases, it ill remain idle until an instruction needs to use it. 'oth address buses are

apportioned, so their use is local to the process involved.

?(cept for the three selfactivating instructions, every instruction e(ecuted in a PSSP has been

fully activated by the primary address bus. /f an e(ecuted instruction has an indirect reference to an

operand, partial activation ill occur to to other PSSPs. Partial activation ill occur to the processingsection of one of the to adBacent PSSPs via a bilateral control line, and partial activation of the

processing section of the referenced PSSP ill occur ith the secondary address bus, in conBunction

ith the !;@ control line. /f an e(ecuted instruction re"uires to operands, the first ill be in the

processing section of the PSSP ith the instruction, and the second ill be referred to indirectly ith

an address in the processing section of the PSSP, folloing the instruction. 5hat PSSP ill be partially

activated ith a bilateral control line, and the processing section of the addressed PSSP ill be

partially activated ith the secondary address bus and the !;@ control line.

$cti%ation +e/uence 'or Instructions

Includes all except the three sel'0acti%ating instructions

hen the se/uencer puts an address on the primary address us) the P++P at that address is

'ully acti%ated 'or execution. hat 'ollo&s 'ull acti%ation depends on the numer and type

o' operands that the instruction needs.ero ,perand Partial acti%ation is not re/uired4 there is no operand.

,ne ,perand #irect Partial acti%ation is not re/uired. The operand is in the processing

section o' the 'ully acti%ated P++P.

,ne ,perand Indirect The source or destination address is in the processing section o' the

'ully acti%ated P++P. Three di''erent situations can occur.

1. +ource o' the operand is the address in the processing section o' the P++P that is 'ully

acti%ated.

+ource is partially acti%ated y the secondary address us and the 56 control line.

#estination o' the operand is the processing section o' the P++P that 'ollo&s the 'ully


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acti%ated P++P.

#estination is partially acti%ated y the $# ilateral control line.

2. +ource o' the operand is the processing section o' the P++P that precedes the 'ully

acti%ated P++P.

+ource is partially acti%ated y the $P#5 ilateral control line.

#estination o' the operand is the address in the processing section o' the 'ully acti%ated

P++P.

#estination is partially acti%ated y the secondary address us and the 56 controlline.

PSSP Systems233. +ource o' the operand is the processing section o' the P++P preceding the 'ully acti%ated

P++P.

+ource is partially acti%ated y the $P$5 ilateral control line.

#estination o' the operand is the address in the processing section o' the 'ully acti%ated

P++P.

#estination is partially acti%ated &ith the secondary address us and the C7 control

line.

T&o ,perands The 'irst operand is in the processing section o' the 'ully acti%ated P++P.

The source o' the second operand is the address in the processing section o' the P++P'ollo&ing the 'ully acti%ated P++P.

The processing section holding the source address o' the second operand is partially

acti%ated y the $$5 ilateral control line.

The source o' the second operand is partially acti%ated y the secondary address us

and the 56 control line.

The destination o' the second operand is the B input to the $"8. The 'irst operand is reinput

into the $ input o' the $"8.

ull activation is achieved by the primary address bus, hich is alays controlled by the

se"uencer once se"uencing has begun. 5he se"uencer has an address in its processing section.

/nitially, the &S put this address there as it loaded the process. @hich address should be put there as

decided by the &S, using information obtained from the process and then adBusted by the &S so that it

fit the particular section of addresses apportioned for the process. As the process begins se"uencing,e(ecuting instructions, the address ill be adBusted as each PSSP is activated and its instruction is

e(ecuted.

=ost instructions ill cause the address to be incremented by one or to. 5he three separate

se"uence control lines that every instruction temporarily sets control this. ?ach instruction e(ecuted

via the se"uencer ill set each of the three se"uence control lines either high or lo. 5he section on

se"uencing PSSPs ill give all the details about se"uencing and the use of these control lines. As each

instruction e(ecutes, it ill cause the address ithin the processing section of the se"uencing PSSP to

increment by one or to, so that the ne(t instruction to e(ecute is pointed to by the se"uencer. >umps,

and returns from Bumps, can also cause adBustments of hich PSSP is the active se"uencer.

/n Bumps that succeed the address may or may not be incremented, depending on the type of Bump

instruction, but the se"uencer ill alays end up ith the Bump address. /f an instruction re"uires that

a Bump be made, the se"uencer ill need the ne address. 5he ne address ill alays be in theprocessing section of the PSSP ith the Bump instruction, or in the processing section of the adBacentPSSP immediately folloing the one ith the Bump instruction. /n either case, the address ill be put

onto the data bus, and the se"uencing PSSP ill accept it from that bus. 5he signals on the three

se"uence control lines ill signal the se"uencer that it needs to accept a ne address from the data

bus. /n Bumps here the ne address resides in the processing section of the PSSP adBacent to the PSSP

ith the Bump instruction, the PSSP ith the address ill be partially activated by a bilateral control

line.

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$ata can ta#e many forms ithin the system. /n a conventional system code and data are mi(ed

and only distinguished from each other at the time of e(ecution by virtue of their position in the

program code being e(ecuted. As the +P4 decodes each instruction, it automatically adBusts the

program counter to point to the ne(t instruction. 5he compiler is relied upon to put code and data in

the correct position so the +P4 doesnt ma#e an error. A PSSP system ill also have the code and data

mi(ed ithin secondary storage, and in the PSSPs, until it is loaded into a set of PSSPs for e(ecution.

5he &S ill ascertain hich is code and hich is data as each piece is chec#ed before loading.

urthermore, since the code and data are #ept separate ithin the PSSPs, there is no chance for these"uencer to ma#e an error in its se"uencing. /t relies on the code being e(ecuted to automatically set

the three se"uence control lines, providing the necessary information to the se"uencer as to here the

ne(t instruction for e(ecution is located.

@hile addresses can be moved as data beteen the processing sections of various PSSPs, hether they

ill be treated as an address or data depends on the actions of the control section of the active PSSP as ite(ecutes its opcode. >ust as in a conventional system, if the programmer fails to #eep trac# of hat each

piece of data represents, the result can be fatal to the process. /t should be remembered that ithin a PSSP

system, an address that attempts to point outside the isolated section of a local process ill cause a logical

error that may cause the process to fail, but it ill not affect the rest of the system.

2.2 P++Ps &ith #edicated unctions

5he original concept leading to the development of this system envisioned only one type of PSSP

throughout the entire system. Numerous small, redundant units ere thought to be the ideal methodith hich to implement full decentraliation and integration of processing, control, memory, and /;&

functions. Practical considerations led to an alternative design more in line ith real orld constraints.

/t as much less costly to create PSSPs ith specialied functions ithin the system. or each function

limited to a specialied PSSP, it as no longer necessary to put that function into the standard PSSP

design. 5he most li#ely possibilities for specialiation ere functions that didnt directly relate to

program code for applicationsDcontrol functions.

Se"uencing is a specialied tas# relating to control ithin an apportioned section. 5he se"uencer

activates each PSSP as it is needed, but the algorithm dictates hen each instruction should be

e(ecuted. 5he programmer implemented the algorithm ith code, the compiler generated the binary

code, and the se"uencer is the tool used to se"uence the code as dictated by the program. ?ach process

needs a se"uencer, and the need for Bumps ith subse"uent return instructions means some sort of

stac# is needed for se"uencing. 5his led to a se"uencing stac#. After much thought, it still seems thestac# can best be implemented ith hardare.

A se"uencing stac# involves a limited number of PSSPs ithin every apportioned section handling

the se"uencing for the process assigned to that section. 5he stac# has to be large enough to handle a

reasonable number of Bumps and returns. A Bump ith a return re"uires the return address to be saved

ithin the stac#. Saving the return address ill cause the stac# to adBust forard by one PSSP. @hen

the return instruction is e(ecuted, it ill cause se"uencing to return to the prior se"uencing PSSP

here the address as #ept. !ead more about this in the section dealing ith the se"uencing stac#. A

ellmade program seldom causes a problem, but e(actly ho large to ma#e the se"uencing stac#

needs to be carefully considered. Some programming, such as the use of recursive functions, could

re"uire very large stac#s, perhaps of an unreasonable sie.

PSSP Systems

-15o other instructions, or functions, that are specialied and limited ithin each process are >&!?and >/!?, the /;& gate#eeper instructions. ?ach uses to PSSPs to atch for an /;& routine

identification number to sho up on the /;& bus and initiate a Bump hen the right conditions are met.

?ach process needs a limited number of these instructions. 5herefore, it ma#es sense to put this

function in a specialied PSSP that can handle both instructions. 5hese three functions are the obvious

ones, but there may be more, especially those instructions privileged for use by the operating system.

5he to additional specialied PSSPs mentioned above led to a design ith three different PSSPs,

one for se"uencing, another for monitoring the /;& bus, and one for generalpurpose algorithm

e(ecution. 5he realiation that code in a permanent readonly form as needed for the boot process


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lead to another type of PSSP. 5his one is Bust li#e the generalpurpose type, but the code in the control

section, and possibly the data in the processing section, must be in a readonly form.

/t is li#ely that other specialied PSSPs ill be developed as opportunities to realie cost or

performance benefits arise. 5he concepts embodied in the design of PSSP systems are ne. As

engineers and designers in the industry see# to adapt the concepts to their needs, ne possibilities ill

emerge. /t is also very li#ely that PSSP designs ill ta#e advantage of evolving production capabilities.

2.2.1 +e/uencing P++Ps

/n this section, differences beteen se"uencing PSSPs and standard PSSPs are discussed. $etailson the operation of se"uencing PSSPs and their use ithin the se"uencing stac# ill be given later, but

a very brief description is given here. PSSPs designed for se"uencing only need be able to handle the

three se"uencing instructions used for se"uencing stac# operations. &ne of these instructions, S?J,

as briefly presented to the reader earlier. 5he other to are SS?J and S?JS%.

5he SS?J is the standby mode of the S?J instruction. 5here can only be one active se"uencerith the S?J instruction at any particular moment ithin a process. 5he active se"uencer is the one in

the process of e(ecuting an instruction, or has the address of the ne(t instruction to e(ecute and is

about to e(ecute it. =ost other se"uencing PSSPs in the stac# stand ready to se"uence hen certain

conditions occur. @hile they ait, they are in standby mode ith the instruction SS?J. 5he S?JS%

instructions are at the beginning and end of the se"uencing stac#. 5hey handle error situations

presented by breaching the se"uencing stac#s upper and loer bounds.

'ecause these PSSPs only handle the three se"uencing instructions, their design is greatlysimplified compared to standard PSSPs. 5hey do not need all the builtin functionality of a standard

PSSP, but they also have additional capabilities that are uni"ue to them. 5he processing section of a

se"uencing PSSP needs to be able to increment its address by one or to, accept data from the data

bus, and put an address onto the primary address bus. 5he processing section needs to have a latch in

each bit position to hold the address of the PSSP that is to be fully activated by the primary address

bus. 8oever, it does not need much in the ay of an A%4, nor does it need all the bus connections

common to standard PSSPs.

A standard PSSP can only increment the contents of its processing section by one, but se"uencing

PSSPs need to be able to increment by to. 5he increment function is handled internally by adding a

one or to to the contents of the processing section. 5his is handled ith a high signal entering the '

input of one of the to loest order bits of an A%4 unit modified to perform the A$$+ instruction.

5he A input to the A%4 only needs an e(ternal connection to the data bus for ne addresses that cometo the se"uencer over that bus, and an internal connection that allos the latch contents to be reinput.

-25he data flo controller only needs to be able to cause the data from the latches to be reinput or the

output to go to the primary address bus.

+hanges ithin the control section also simplify the design of se"uencing PSSPs. rom the global

control lines, only the SJ=, +%L1, and +%L2 control lines need to be monitored. 5he local control

DPU Systems

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