Digital Testing: Fault Simulation

04/20/23Based on text by S. Mourad

"Priciples of Electronic Systems"

Digital Testing: Fault Simulation

Fault Simulation

Classical Fault SimulationModern Fault Simulation for Combinational CircuitsModern Fault Simulation for Synchronous Sequential CircuitsParallel and Distributed Fault Simulation Fault Grading --- Approximate Fault SimulationHardware Approaches to Fault Simulation

1. To evaluate the quality of a test set -- usually in terms of fault coverage2. To incorporate into ATPG for test generation -- due to its lower complexity3. To construct fault dictionary -- for post-test diagnosis4. To analyze the operation of a circuit in the presence of faults -- for reliability analysis

Why Fault Simulation?

Conceptual Fault Simulation

• Logic simulation on both good (fault-free) and faulty circuits

Fault-free Circuit

Faulty Circuit #1 (A/0)

Faulty Circuit #2 (B/1)

Faulty Circuit #F (D/0)

PrimaryInputs(PIs) Primary Outputs (POs)

Patterns(Sequences)(Vectors)

Response Comparison

Detected?

A BC

D

Verified designnetlist

Verificationinput stimuli

Fault simulator Test vectors

Modeledfault list

Testgenerator

Testcompactor

Faultcoverage

?

Remove tested faults

Deletevectors

Add vectors

Low

Adequate

Stop

Fault Simulation

Fault simulation

Selection of target faults

Select target fault

doneGenerate test for target

Fault simulate

Discard detected faults

No more faults

Generate initial T

done

Evaluate T

Sufficient fault coverage?

Modify T

N Y

To evaluate (grade) a test T use fault simulation

Classical Fault Simulation

Common Characteristics:In general, no restriction on the circuit types.Developed before VLSI era.

Serial Fault Simulationtrivial single-fault single-pattern

Parallel Fault SimulationDeductive Fault SimulationConcurrent Fault Simulation

Complexity of Fault Simulation

• Complexity = P * F *G~ O(G3) with single s-a faults• The complexity is higher than logic simulation, O(G2), but is much lower than test pattern generation.• In reality, the complexity is much lower due to fault colapsing and advanced techniques.

#Gate (G)

#Pattern (P)

#Fault (F)

Serial fault simulation

fault specification (includes fault collapsing)fault insertionfault effect generation & propagationfault detection & discarding

In parallel fault simulation, a number of faulty circuits are simulated and signal values are represented by vectors

Classical Parallel Fault Simulation

Taking advantage of inherent parallel operation of computer words to simulate faulty circuits in parallel with fault-free circuit

the number of faults, that can be processed in parallel is limited by the word length.

Straightforward and memory efficientSome weaknesses:

A value change, of a single fault or fault-free circuit leads to the computation of the entire word. The fault-free logic simulation is repeated for the number of passes.

Example of Parallel Fault Simulation

— Bit-space: J/0 B/1 F/0 FF where FF = Fault-free

x

x

x

A

B

C

D E

F

G

H J

1

0

1

1

• Consider three faults: B/1, F/0, and J/0

0 0 0 0

0 1 0 0

1 1 1 1

1 0 0 1

0 1 0 0 0 1 0 1

1 1 0 11 1 1 1

1 1 0 1

1 0 1 1

Parallel Fault Simulation

u

G1 G2

G3 G4

G5

ab

cde

h i

g

f

Applied test pattern:abcde=10010

Parallel Fault Simulation

ff a/0 b/1 c/1 d/0 e/1 f/0 f/1 g/0 g/1 h/0 h/1 i/0 i/1 u/0 u/1

a=1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

b=0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

c=0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

d=1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

f=ab 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0

g=(f+c)’ 1 1 0 0 1 1 1 0 0 1 1 1 1 1 1 1

h=cd 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0

e=0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

i=e+h 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0

u=g+i 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1

Deductive fault simulation

Instead of keeping all signal values for all faulty circuits in parallel as in parallel simulation, only a list of faults which causes different responses on a given line is kept

0 1 2 3 4 5 6 7 8 9 F1 1 1 1 0 1 1 0 1 1 ... 1

faultssignal line i

Li = {4, 7}

parallel

deductive

Deductive Fault Simulation

(b)

x=1y=0z=0

x=1y=1

x=1y=0

x=1y=0

Lx Ly Ly

LxLx Ly Lx

(LyLz)

(a)

g=1

i=0 u=1

h=0

e=0

i=0

f=0

c=0

g=1

f=0a = 1

b=0

d=1

c=0 h=0

G1

G3G4

G2

G5

Lb La

f/1

Lg=LfLc

g/0 Lu=(Lg L i

(u/0)

Li=LhLe

i/1

Lf =(

(Lc L dh/1Lh =

Rules for deductive simulation

j IIf C = then L = { L } {Z sa(c i)}z j

else L = ({ L } - { L }) {Z sa(c i)}j C

jj I-C

j

I - inputc - controlling valuesi – inversion valueand for the primary inputs set )( icsaZLi

Therefore for AND,OR,NAND,NOR there is no 0,1,0 or 1 respectively on any input and append the output list list with Z/0, Z/1, Z/1, Z/0 respectively

So for AND,OR,NAND,NOR when there is 0,1,0 or 1 on their inputsappend output list with Z/1, Z/0, Z/0, Z/1 respectively


Besides faults which can propagate through the gate, we add the following output faults

c i |c| = 0 |c| > 0 fault fault equivalence dominance

AND 0 0 Z0 Z1 I0 Z0 I1 < O1OR 1 0 Z1 Z0 I1 Z1 I0 < O0NAND 0 1 Z1 Z0 I0 Z1 I1 < O0NOR 1 1 Z0 Z1 I1 Z0 I0 < O1

xy 00 01 10 11

AND Lx Ly Z/1

(Lx - Ly)Z/1 (LyLx)Z/1 Lx Ly Z/0

OR Lx Ly Z/1

(Ly - Lx) Z/0

(Lx - Ly) Z/0 Lx Ly Z/0

NAND Lx Ly Z/0

(Lx - Ly) Z/0

(Ly - Lx) Z/0 Lx Ly Z/1

NOR Lx Ly Z/0

(Ly - Lx) Z/1

(Lx - Ly) Z/1 Lx Ly Z/1


For two-input gates

Deductive Simulation

LEVEL 0 LEVEL 1 LEVEL 2 LEVEL3 LEVEL4Node FF PRIMARY INPUTS PRIMARY

OUTa 1 a/0b 0 b/1c 0 c/1d 1 d/0e 0 e/1f 0 --------------------- (LbLa)f/1 = b/1, f/1

g 1 --------------------- --------------------- LfLcg/0 = b/1, f1, c/1, g/0

h 0 --------------------- (LcLd)h/1 = c/1,h/1

i 0 --------------------- --------------------- LhLei/1 = c/1,e/1, i/1, h/1u 1 --------------------- --------------------- --------------------- LgLiu/0 = b/1, f1, g/0, u/0

So Lu = (Lg – Li) u/0 = ((b/1, f/1, c/1, g/0) -(c/1)) + u/0= b/1, f/1, g/0, u/0, as indicated in the last column

g=1

i=0 u=1

h=0

e=0

i=0

f=0

c=0

g=1

f=0a = 1

b=0

d=1

c=0 h=0

G1

G3 G4

G2

G5

Lb Laf/1

Lg=LfLcg/0 Lu=(Lg L i(u/0)

Li=LhLei/1

Lf =(

(Lc L dh/1

Lh =

Example of Deductive Simulation

x

x

x

A

B

CD E

F

G

H J

1

0

1

1

• Consider 3 faults: B/1, F/0, and J/0 and test t1={1,0,1}

LB = {B/1}, LF = {F/0}, LA = Ø LC=LD = {B/1}

x

x

x

A

B

CD E

F

G

H J

1

0

1

1

• Consider 3 faults: B/1, F/0, and J/0

LB = {B/1}, LF = {F/0}, LC=LD = {B/1}, LG = {B/1}, LE = {B/1}


x

x

x

A

B

CD E 1

F

G

H J

1

0

1

1


LB = {B/1}, LF = {F/0}, LC=LD = {B/1}, LG = {B/1}, LE = {B/1}, LH = {B/1, F/0}


x

x

x

A

B

CD E 1

F

G 0

H 1 J

1

0

1

1


LB = {B/1}, LF = {F/0}, LC=LD = {B/1}, LG = {B/1}, LE = {B/1}, LH = {B/1,F/0}, LJ = {F/0,J/0}


x

x

x

A

B

CD E 1

F

G 0

H 1 J

0

0

1

1

LB = {B/1}, LF = {F/0}, LC=LD = {B/1}, LG = Ø, different set for t2={0,0,1} LE = {B/1}, LH = {B/1,F/0}, LJ = {B/1,F/0,J/0}

• When A changes from 1 to 0



Example :After fault collapsing, the set of faults we simulate is { a0, a1, b1, c0, c1, d1, e0, g0 , h0, h1} Perform deductive fault simulation using test vector t1={00110}

1 k

ab

c

de

00

1

10

f 0

g

h

j 0

i 1

1m


Assume the first applied test vector is t1={00110}

La = {a1}, Lb = {b1}, Lc = {c0}, Ld = , Le = , Lf = La Lb = ,

Lg = Lc {g0}={c0,g0}, Lh = Lc {h0} = {c0, h0}, Lj = Lg - Lf = {c0, g0},

Li = Ld Lh = {c0, h0}, Lk = Li - Le = {c0, h0}, Lm = Lk - Lj = {h0}

1 k

ab

c

de

00

1

10

0f g

h

j 0

i 1

1m

Fault list { a0, a1, b1, c0, c1, d1, e0, g0 , h0, h1}

x=1x=1 x=1 x=1y=0

Ly Lx

x=0y=0 y=0

z=0y=1

Lx LyLx

(LyLz)Lx

Ly

y=0

Ly Lx

ExampleUsing test vector t2={1,1,0,1,0}Fault list after fault collapsing{ a0, a1, b1, c0, c1, d1, e0, g0 , h0, h1}

0 k

ab

c

de

11

0

10

1f g

h

0j

0i

0m

Start with La = {a0}, Lb = , Lc = {c1}, Ld = , Le =

Deductive Fault list

La = {a0}, Lb = , Lc = {c1}Ld = , Le = Lf = La Lb = {a0}Lg = Lc = {c1}Lh = Lc {h1} = {c1,, h1}Li = Lh - Ld = {c1,, h1}Lj = Lf - Lg = {a0} Lk = Li Lg = {c1,, h1}Lm = Lj Lk = {a0 ,c1, h1}

Faults detected in this step of deductive simulation

Concurrent Fault Simulation

Each gate retains a list of fault copies and each of them stores the status of a fault different from fault-free values. Simulation is similar to the regular fault simulation except that only the difference w.r.t. fault-free circuit is retained.Very versatile in circuit types and gate delaysAlthough theoretically all faults in a circuit can be processed in one pass, memory explosion restricts the fault number in each pass.

Fault List of AND Gate

A

BD

0

00

1

00

1

00

0

01

A/1

B/1

D/1

faults

a

b c

d

e

f

g

1

11

0

1

1

11

1

01

1 0

0

10

1

00

1

00

1

10

1

00

1

11 1

11

0

00

0

11

0

00

0

00

0 1 0 1 1 1

a0 b0c0 e0

a0 b0

b0

c0 e0

d0d0 g0 f1

f1

Concurrent Fault Simulation

Fault List Propagation

A

B

D0

00

C

E0

00

A

B

D1

00

C

E0

00

A/1: 10_0 C/1: 01_1

B/1: 01_0 D/1: 10_1

D/1: 00_1 E/1: 00_1

*A/0: 00_0 *B/1: 10_1 E/1: 00_1

*B/1: 11_1 C/1: 01_1

*D/1: 10_1 D/1: 10_1

*

faults Inputs andoutput

Example of Concurrent Simulation

x

x

x

A

B

CD E

F

G

H J

1

0

1

1


LG = {10_0, B/1:11_1} LE = {0_1, B/1:1_0}

Inputs_output Fault: Faulty inputs_output

signal

x

x

x

A

B

CD E 1

F

G

H J

1

0

1

1


LG = {10_0, B/1:11_1} LE = {0_1, B/1:1_0} LH = {11_1, B/1:01_0, F/0:10_0}


x

x

x

A

B

CD E 1

F

G 0

H 1 J

1

0

1

1


LG = {10_0, B/1:11_1} LE = {0_1, B/1:1_0} LH = {11_1, B/1:01_0, F/0:10_0}LJ = {01_1, B/1:10_1, F/0:00_0, J/0:01_0}


x

x

x

A

B

CD E 1

F

G 0

H 1 J

0

0

1

1

• When A changes from 1 to 0

LG = {00_0, B/1:01_0} LE = {0_1, B/1:1_0} LH = {11_1, B/1:01_0, F/0:10_0}LJ = {01_1, B/1:00_0, F/0:00_0, J/0:01_0}


Concurrent Simulation

u

G1 G2

G3 G4

G5

ab

cde

h i

g

f

G1 a b f G2 c f g G3 c d h G4 e h i G5 g I u1 0 0 0 0 1 0 1 0 0 0 0 1 0 1

a/0 0 0 0 b/1 0 1 0 c/1 1 1 1 c/1 0 1 1 b/1 0 0 0b/1 1 1 1 c1/1 1 0 0 d/0 0 0 0 e/1 1 0 1 c/1 0 1 1f/1 1 0 1 f /1 0 1 0 h/1 0 1 1 h/1 0 1 1 e/1 1 1 1

g/0 0 0 0 i/1 0 0 1 f /1 0 0 0

g/0 0 0 0h/1 1 1 1i/1 1 1 1u/0 1 0 0

Gates and their inputs

Detectable faults in boldPossiblefaults

Faulty responses

Fault Simulation

1

Y

Z

3

2

7 4

8 95

6

10

11

12

13

14

A

B

C

D

FG

H

I

E

Unused output B faults not detected

Tied to ground

Exercise

Digital Testing: Fault Simulation

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