Digital Controller for PE

8/8/2019 Digital Controller for PE

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Digital Controller For PowerDigital Controller For Power

Electronic SystemsElectronic Systems

Renji Chacko, Scientist DRenji Chacko, Scientist D

Power Electronics GroupPower Electronics Group

CDAC (formerly ERDCI), Thiruvanathapuram.

Web Site: www.erdcitvm.org


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Emergence of Power Electronics SystemsEmergence of Power Electronics Systems

Applications

DC drives, AC drives, UPS systems

Automotive applications - EV, HEVNon conventional energy converters

- Solar, wind etc.

Power quality systems

- STATCOM, Harmonic compensatorsVector control techniques for AC systems

Implemented with digital controller


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Control HardwareControl Hardware

Analog Controller

Discrete Digital Logics

PLCSFPGAS, ASICS

Micro-Controller

Digital Signal Processor

Hardware Selection depends onApplication, Circuit complexity, Speed,

Accuracy


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High band-widthHigh resolution

Easy to design

Simple circuit for

small systems

Susceptible to EMI

Sensitive to Componentaging

Sensitive toTemperature

Hardwired Design

Limited to ClassicalControl SystemDesign

Ad

va

nta

ges

Lim

ita

tio

ns

To Summarize on AnalogTo Summarize on Analog

ControllerController


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Digital Systems

Data Processing

Large memory

Data storage

High level user interface

Keyboard/ display

interface

Standard networking

Data processing delay

acceptable

Non real time

Control Application

Minimum memory

No external data storage

Minimum user interface

Keypad and LCD display

Industrial fieldbus

networking

Computational delay

critical

Real time


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DACDAC

80188CPU

80188CPU

WDTWDT MEMORYMEMORY UARTUART RS232CRS232C

ADCADCDIGITAL

I/ODIGITAL

I/O

SIGNALCONDITION

SIGNALCONDITION

OPTICAL

ISOLATOROPTICAL

ISOLATOR

OPTICAL

ISOLATOR

TRANSRELAY

OPTICAL

ISOLATOR

TRANSRELAY

DATABUS

ADDRESS BUS

CONTROL BUS

ANALOGINPUTS

DIGITALINPUTS

ANALOGOUTPUTS

DIGITALOUTPUTS

KEYBOARD

8888

Digital System for ControlApplications

Digital System for ControlApplications


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The CPUThe CPU

80C18880C188

DataBus

addressBus

controlBus

Int.

clock

controlin

I/ocs

Timout

16 bit CPU with

2 TimersInterruptController

Data Bus 8-bit

20 bit AddressControl lines forRead, write, etc

Clock 24MHzControl for DMA,

Timer etcInternal DecodersBuilt-in I/Os


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To summarize on Micro-ControllerTo summarize on Micro-Controller

Large Dynamic RangeInsensitive to Time

and TemperatureCommon Hardware

for many ApplicationsAlgorithmic

Implementation

RepeatableRemote ComputerInterface

Self Diagnostics

Creates Numerical

Patterns in an AnalogWorldMinimum Hardware

even for SimpleApplications

Design is TimeConsuming

Computational Delay isCritical

ADV

ANTA

GES

DISA

DVA

NTAG

ES


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DIGITAL SIGNAL PROCESSOR (DSP)DIGITAL SIGNAL PROCESSOR (DSP)

FORFOR

REAL TIME CONTROLREAL TIME CONTROL


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Real Time ControlReal Time Control

Reacts in deterministic way

Several tasks executed concurrently


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Comparison betweenComparison between

DSP and Micro-ProcessorDSP and Micro-Processor

High PerformanceSignal Processing

ArchitectureAdvanced Control

TechniquesAdditional functions

On-chip Peripherals

Supervisory functionsFamiliar Architecture

Limited Peripherals

Low PerformanceComputation Delay

Numerical Problems

DSP

Mic

ro

-controlle

r


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Architecture of TMS320F206 DSPArchitecture of TMS320F206 DSP

CPU

16-Bit TREG

16-Bit x 16-Bit Multiply

32-Bit PREG

ShiftL

32-Bit ALU32-Bit ACC

8 Auxiliary Registers

8 Level Hardware Stack

Repeat Instruction Counter

2 Status REG

D/P RAM256x16

D RAM288x16

D/P RAM4Kx16

P FLASH32Kx16

I/O64Kx16

SoftwareWSG

Timer

Serial Port(sync)

Serial Port(async)

A(0.15)

D(0.15)


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DSPDSP

FeaturesFeatures

Features Benefits

Single Cycle Instruction Advanced Algorithm

Pipelined Architecture High Band Width

Harvard Architecture Parallel Data & ProgramHardware Multiplier Min. Computation Delay

Hardware Shifters Large Dynamic Range

16-Bit Word Min. Quantization Errors

32-Bit Registers Min. Truncation ErrorHardware Stack Fast Int. Processing

Saturation Mode Prevents Wrap-Around

Built-in Timer, Wait State,

Serial I/O

Minimize Hardware


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Comparison between Floating PointComparison between Floating Point

and Fixed Point Digital Controllersand Fixed Point Digital Controllers

ProgrammableSoftware Development

Cost LowDevelopment in High

Level Language

Expensive and CostlyComponents

SoftwareDevelopment Cost High

Truncation and

Overflow ErrorsEffective codesthrough AssemblyLanguage

Floa

tingPoin

t

FixedPoin t

Less Expensive

Less Hardware


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Real time DSP Controller forReal time DSP Controller for

PEPE

NetworkDevelopment

System

FPGA

SensorsSensors

User

Interface

User

InterfaceDigital

Logic

Digital

Logic

AnalogInterfaceAnalog

Interface

ClockClock ResetReset

DSP

( AC Drive

Algorithm )

DSP

( AC Drive

Algorithm )

JTAG

Interface

JTAG

Interface

Serial

Interface

Serial

Interface

Analog output

(Debug)

Analog output

(Debug)

Gate Signal

Generation

Gate SignalGeneration

Gate DriverGate Driver

Fault

Interlock

Fault

Interlock


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DSP based PE ControllersDSP based PE Controllers

Stand Alone Small Systems

for UPS, small AC Drives etc.Stand Alone Medium PowerSystems

for Industrial Drives, UPS

etc.PC Based Controller

for large systems.


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Stand Alone SmallStand Alone Small

SystemsSystems

Ref.

TxDRxD

Isolation FPGA CktCPUTimerInt.

P FlashRAM

USART

RS232CFb.

Ckt

ADC

Fb.

To Gate

DSP Circuits for

PE


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STANDALONE CONTROLLER WITH SMPS


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Stand Alone Medium PowerStand Alone Medium Power

SystemsSystems

888888888888

ToGat

e

DSP

Ckts

DP

RAMCPU

ADC

DAC

DigitalI/O

RS232C

RS485


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STANDALONE CONTROLLER WITHSTANDALONE CONTROLLER WITH

NETWORKNETWORK


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PC Based ControllerPC Based Controller

PCBsOn PC MB

Industrial PCIndustrial PC

Features Standard Hardware One PCB PE Specific

Upto to date Hardware Cost High All software resource

easily adaptable Fast development

All PC Elements such as PC SMPS, FDD, HDD,VDU, Keyboard, Mouse Used during designFDD, VDU, Keyboard, Mouse RemovedSMPS by small one and HDD by Flash Replaced


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PE Specific Hardware onPE Specific Hardware on

PCPC

DSPCkts

DSPCkts

DPRAM

DPRAM

888888888888

I/O

interface

ToGate

ToGate

PCBus


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PC Add-on SystemPC Add-on System


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Control Hardware Flow Diagram


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Digital Controller HardwareFeatures

Multi layer PCB with Dedicated digital and ground planes

On board digital power supply regulator

Proper isolation from power circuit

Proper placement/ shielding to reduce EMI/EMC effect

Placement of components :

No mixing of high frequency

low frequency/ analog signals

Local decoupling for digital circuits

Isolation for I/O signals


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DesignDesignTechniquesTechniquesforforEMCEMC

Most preferred techniques Circuit design and choice of components

Cables and Connectors Filters and Transient suppressors Shielding PCB layout

ESD, Electromechanical devices and PFC


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Circuit design and choice ofCircuit design and choice of

componentscomponents

Digital components and circuit design

Choosing components,Bad IC sockets,

Spread spectrum clocking

Analog components and circuit designChoosing components, Preventing demodulation problem Switch-mode design

Topology,Snubbing,Heat sinks, Rectifiers, Magnetics

Signal communication components and circuit designNon-metallic communication,Optoisolation,

Communication,Protocols Choice of passive components


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Asyn link

Drive1Drive1

Drive 2Drive 2

Drive nDrive n

ActuatorsActuators

Sensor

Elements 1

Sensor

Elements 1

SensorElements n

SensorElements n

Syn link

. ..

Distributed Control ArchitectureDistributed Control Architecture


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Controller NetworkingController Networking

AddressAddress FunctionFunction DataData ChecksumChecksum

Address Is the Address of the ControllerFunction M-to-S, S-to-M, 16-bit, 8-bit, Variable or logicData Address, no of data, dataChecksum If no error acknowledge or skip

Master Slave configurationMessage oriented protocolCan be implemented on standard hardware like RS-232, RS-485

Mod BusMod Bus

EOFEOF


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Mod Bus Protocol

MasterMaster

Slave 1Slave 1 Slave 2Slave 2 Slave nSlave n

Master SlaveRead a variable value

Value of the variable

Master SlaveUpdate a variable value

Acknowledge

Data exchange in write mode

Data exchange in read mode

(Value updated)

Query

Response

Query

Response


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Controller Area Network(CAN)Controller Area Network(CAN)I

D

E

IdentifierR

T

R

S

O

F

r0 DLC Data EOF

I

FS

CRC

A

C

K

IdleIdle

Message Frame Format

CAN efficiently supports distributed real-time control applications Producer/Consumer broadcast model

Prioritization of messages, message identifiers instead of node address

Configuration flexibility

High reliability , Error detection and signaling

Automatic retransmission of corrupted messages.

Autonomous switching off of defect nodes

Carrier-sense, multiple-access-with-collision-resolution (CSMA/CR) protocol

Non-destructive bit-wise arbitration

Message oriented broadcast communication


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CAN Protocol


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Digital Controller for

Automotive Application

Processor basedController

3.3 V

12V

SMPS

RS232

15V, 5V

42V

SMPS

Peripheral Interface GATEdrive

JTAG

CANinterface

Analog

I/O

Digital

I/O

GATE

Signals

CAN

Bus

PC

42V DCBus

14V DC

Bus

(Optional)


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System DesignSystem Design

Formulate the Specification Develop the Overall Block Diagram

Develop the Control Block Develop the Flow Chart Develop the Flow Diagram Select an Appropriate Hardware Develop the Functional Software Modules Appropriately Cascade the Functional Modules Scale and Debug


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Common Software FunctionalCommon Software Functional

ModulesModules

Digital/ Analog input interface Space vector PWM PID controller

d-q Transformation and Re-transformation 3phase to 2phase transformation and vice versa Machine model implementation

Calculation of machine torque

Calculation of speed

Calculation of stator flux

Delay elements Integrator Sin and cos function generatorsDigital/ Analog output interface


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Functional Module Identification

f(n)input output

input output +==

=

=

ktsktst

t

s dttedttedttektu0

0

)()()()(

][*])1[()( ssss kteTtkuktu +=

input output

)()()(

tetudt

tduTd =+

]})1()({*)[(])1[()( ssdsss tkukteTTtkuktu +=

Look up table based function

generator

Delay element

Integrator


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Functional Module Identification

input output+= dttektektu ip )()()(

+= )()()( sisp ktekktekktsu

PI controller

input output3

2

)(*5.1)( ssrss ktikti =

)]()([*)2

3()( ssbssyss ktiktikti =

input output2

d-q

)]sin(*)([)]cos(*)([)( sssqsssdss ktktiktktikti =

)]cos(*)([)]sin(*)([)( sssqsssdss ktktiktktikti +=

d-q transformation

3-Phase to 2-Phase conversion


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PI ControllerPI Controller EquationEquation

)(12

TEK)(1EK)(1U

1)(2TEK1)(EK1)(U

2

TEKEKU

EK

EKU

eKeKu

IP

IP

IP

I

P

IP

111

z.(z)..z(z)..z(z).

z.(z)..z(z)..z(z).

1z

1z.(z)..(z).(z)

(s).

S

(s).(s)

dt(t).(t).(t)

++=

++=

++=

+=

+=

)( 11

2

T

+=

z

zS


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PIPI

ControllerController Equation cont..Equation cont..

2

T

2

T

2

T

2

T

2T

2T

2

T

2

T

.KKK

.KKK

eKeKuu

e.KKe.KKuu

E.KKE.KKUU

E.KKE.KKUU

IP2

IP1

21

IPIP

1IPIP

1

IPIP

)()(

)()(

)()(

+=

+=

++=

++++=

++++=

++++=

1)(k(k).1)(k(k)

1)(k.(k).1)(k(k)

..

(z).z.(z).(z).z(z)

.

11


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PI ControllerPI Controller Software moduleSoftware modulepiSpeed:

SETC OVM

LACC softSpeed

SUB wFb ;rotorSpeed

SACL sp0Error

* ----------------------------------------------------------

BCND negSpError,LTSUB #kpSpeedLimit

BCND skipSpError,LT

SPLK #kpSpeedLimit,sp0Error

B skipSpError

negSpError:

ADD #kpSpeedLimit

BCND skipSpError,GTSPLK #-kpSpeedLimit,sp0Error

skipSpError:----------------------------------------------------------

LT sp0Error

MPY kpSp ;e[k]*Kp

PAC

SACL tempA


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PI ControllerPI ControllerLACC torq0Error ;acc=e[k]

ADD torq1Error ;acc=e[k]+e[k+1]

SACL tempB ;tempB=e[k]+e[k+1]

LT tempB ;T=e[k]+e[k+1]

MPY kiTorq ;P={e[k]+e[k+1]}*Ki*T/2

LACL piTorqILo

ADD piTorqIHi,16 ;acc=Icon[k]LTD torq0Error ;acc=Icon[k]+{e[k]+e[k+1]}*Ki*T/2,

T=sp0Err0r, volt1Error=volt0Error

SACL piTorqILo

SACH piTorqIHi ;Icon[k+1]

ADD tempA,16

SACH tempA

LT tempA

MPY Tmax

PAC

SACH piTorqRef,1

CLRC OVM

RET

Software moduleSoftware module


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Structuring DSP ForStructuring DSP For

Power Electronics ControlPower Electronics Control

Int. RoutineMain Routine

Initialization

Timer Int.

Sampling time Sampling time

Timer outputTo the interrupt


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Software Development phasesPC based software development

C, C++, Assembly

Cross compiler/ assembler

Target Memory allocation for software

modules

Downloading and running in RAM

Debugging

Firmware into Flash/ EPROM


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Software development SupportSoftware development SupportSimulator

Software programs that simulate the

operation of the processorNo target hardware required

Monitor debugger-

Serial port, RS 232CIntel iaPX 86/88


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Software developmentSoftware development

SupportSupportIn Circuit Emulator- Emulation processor replaces

Actual processor

In circuitEmulatorIn circuitEmulator

JTAG (IEEE 1149.1)Emulator

PC Add on Card, Parallel port

Emulator header in target board

Target

Board

Target

Board


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Trends in digital controlTrends in digital control

HardwareHardware

Low voltage design: 3.3V instead of conventional 5VHigher level of integration, low power, Higher speed

High End Integration

ADC, DAC, PWM - Minimize the external interface for speed compatibility

No External data/ address bus and associated control lines

Flash / EEPROM memory

Power Down features in idle and fault condition

External Lower frequency crystal

10Mhz for 40-125 Mhz

Serial interface through SPI and SCI

Minimum I/O s for interface, if any

Complete system working on Single supply

Reduced power supply requirement

Built in industrial field bus network interface

CAN, I2C


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Power Electronics Group

C-DAC( Centre for Development of Advanced

Computing )

Thiruvananthapuram

Digital Controller for PE

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