Designing a Single Cycle Datapath & Datapath Control

Datorteknik DatapathControl bild 1

Designing a Single Cycle Datapath

&

Datapath Control


The Performance Perspective

Performance of a machine is determined by:

– Instruction count

– Clock cycle time

– Clock cycles per instruction

Processor design (datapath and control) will determine:– Clock cycle time

– Clock cycles per instruction

Single cycle processor: Advantage: One clock cycle per instruction Disadvantage: long cycle time

CPI

Inst. Count Cycle Time


How to Design a Processor: step-by-step

1. Analyze instruction set => datapath requirements– the meaning of each instruction is given by the register transfers

– datapath must include storage element for ISA registers

possibly more

– datapath must support each register transfer

2. Select set of datapath components and establish clocking methodology

3. Assemble datapath meeting the requirements

4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.

5. Assemble the control logic


The MIPS Instruction Formats All MIPS instructions are 32 bits long. The three instruction formats:

– R-type

– I-type

– J-type

The different fields are:– op: operation of the instruction

– rs, rt, rd: the source and destination register specifiers

– shamt: shift amount

– funct: selects the variant of the operation in the “op” field

– address / immediate: address offset or immediate value

– target address: target address of the jump instruction

op target address02631

6 bits 26 bits

op rs rt rd shamt funct061116212631

6 bits 6 bits5 bits5 bits5 bits5 bits

op rs rt immediate016212631

6 bits 16 bits5 bits5 bits


The MIPS-lite Subset for today

ADD and SUB– addU rd, rs, rt

– subU rd, rs, rt

OR Immediate:– ori rt, rs, imm16

LOAD and STORE Word– lw rt, rs, imm16

– sw rt, rs, imm16

BRANCH:– beq rs, rt, imm16










Logical Register Transfers

RTL gives the meaning of the instructions All start by fetching the instruction

op | rs | rt | rd | shamt | funct = MEM[ PC ]

op | rs | rt | Imm16 = MEM[ PC ]

inst Register Transfers

ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4

SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4

ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4

LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4

STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4

BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4


Requirements of the Instruction Set

Memory– instruction & data

Registers (32 x 32)– read RS

– read RT

– Write RT or RD

PC Extender Add and Sub register or extended immediate Add 4 or extended immediate to PC


Components of the Datapath

Combinational Elements Storage Elements

– Clocking methodology


Combinational Building Blocks

32A

B32

Y32

SelectM

UX

32

32

A

B32

Result

OP

AL

U

32

32

A

B32

Sum

Carry

Ad

der

CarryIn

Adder MUX

ALU


Storage Element (Register)

Register– Similar to the D Flip Flop except

N-bit input and output Write Enable input

– Write Enable: negated (0): Data Out will not change asserted (1): Data Out will become Data In

Clk

Data In

Write Enable

N N

Data Out


Storage Element: Register File

Register File consists of 32 registers:– Two 32-bit output busses:

busA and busB

– One 32-bit input bus: busW

Register is selected by:– RA (number) selects the register to put on busA (data)

– RB (number) selects the register to put on busB (data)

– RW (number) selects the register to be writtenvia busW (data) when Write Enable is 1

Clock input (CLK) – The CLK input is a factor ONLY during write operation

– During read operation, behaves as a combinational logic block: RA or RB valid => busA or busB valid after “access time.”

Clk

busW

Write Enable

3232

busA

32busB

5 5 5RW RA RB

32 32-bitRegisters


Storage Element: Idealized Memory

Memory (idealized)– One input bus: Data In

– One output bus: Data Out

Memory word is selected by:– Address selects the word to put on Data Out

– Write Enable = 1: address selects the memoryword to be written via the Data In bus

Clock input (CLK) – The CLK input is a factor ONLY during write operation

– During read operation, behaves as a combinational logic block: Address valid => Data Out valid after “access time.”

Clk

Data In

Write Enable

32 32DataOut

Address


Clocking Methodology

All storage elements are clocked by the same clock edge Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time

.

.

.

.

.

.

.

.

.

.

.

.

Clk

Don’t Care

Setup HoldSetup Hold


Step 3

Register Transfer Requirements –> Datapath Assembly

Instruction Fetch Read Operands and Execute Operation


Overview of the Instruction Fetch Unit

The common RTL operations– Fetch the Instruction: mem[PC]

– Update the program counter: Sequential Code: PC <- PC + 4 Branch and Jump: PC <- “something else”

32

Instruction WordAddress

InstructionMemory

PCClk

Next AddressLogic


Add & Subtract

R[rd] <- R[rs] op R[rt] Example: addU rd, rs, rt– Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields

– ALUctr and RegWr: control logic after decoding the instruction

32

Result

ALUctr

Clk

busW

RegWr

32

32

busA

32

busB

5 5 5

Rw Ra Rb

32 32-bitRegisters

Rs RtRd

AL

Uop rs rt rd shamt funct

061116212631



Register-Register Timing

32Result

ALUctr

Clk

busW

RegWr

3232

busA

32busB

5 5 5

Rw Ra Rb32 32-bitRegisters

Rs RtRd

AL

U

Clk

PC

Rs, Rt, Rd,Op, Func

Clk-to-Q

ALUctr

Instruction Memory Access Time

Old Value New Value

RegWr Old Value New Value

Delay through Control Logic

busA, BRegister File Access Time

Old Value New Value

busWALU Delay

Old Value New Value

Old Value New Value

New ValueOld Value

Register WriteOccurs Here


Logical Operations with Immediate

R[rt] <- R[rs] op ZeroExt[imm16] ]

32

Result

ALUctr

Clk

busW

RegWr

3232

busA

32

busB

5 5 5


Rs

RtRdRegDst

ZeroE

xt

Mu

x

Mux

3216imm16ALUSrc

AL

U

11

op rs rt immediate

016212631

6 bits 16 bits5 bits5 bits rd?

immediate

016 1531

16 bits16 bits

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Load Operations R[rt] <- Mem[R[rs] + SignExt[imm16

Example: lw rt, rs, imm16

11

op rs rt immediate

016212631

6 bits 16 bits5 bits5 bits rd

32

ALUctr

Clk

busW

RegWr

3232

busA

32busB

5 5 5


Rs

RtRdRegDst

Exten

der

Mu

x

Mux

3216

imm16

ALUSrc

ExtOp

Clk

Data InWrEn

32

AdrData

Memory

32

AL

UMemWr Mu

x

W_Src


Store Operations Mem[ R[rs] + SignExt[imm16] <- R[rt] ]

– Example: sw rt, rs, imm16

op rs rt immediate

016212631


32

ALUctr

Clk

busW

RegWr

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst

Exten

der

Mu

x

Mux

3216imm16

ALUSrcExtOp

Clk

Data InWrEn

32Adr

DataMemory

MemWr

AL

U

32

Mux

W_Src


The Branch Instruction

beq rs, rt, imm16

– mem[PC] Fetch the instruction from memory

– Equal <- R[rs] == R[rt] Calculate the branch condition

– if (COND eq 0) Calculate the next instruction’s addressPC <- PC + 4 + ( SignExt(imm16) x 4 )

elsePC <- PC + 4

op rs rt immediate

016212631



Datapath for Branch Operationsbeq rs, rt, imm16 Datapath generates condition (equal)

op rs rt immediate

016212631


32

imm16

PC

Clk

00

Ad

der

Mu

x

Ad

der

4nPC_sel

Clk

busW

RegWr

32

busA

32busB

5 5 5


Rs Rt

Eq

ual

?

Cond

PC

Ext

Inst Address


A Single Cycle Datapath

imm

16

32

ALUctr

Clk

busW

RegWr

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst

Exten

der

Mu

x

3216imm16

ALUSrcExtOp

Mu

x

MemtoReg

Clk

Data InWrEn32 Adr

DataMemory

MemWr

AL

U

Equal

Instruction<31:0>

0

1

0

1

01

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

=

Ad

der

Ad

der

PC

Clk

00

Mu

x

4

nPC_sel

PC

Ext

Adr

InstMemory


An Abstract View of the Critical Path Register file and ideal memory:

– The CLK input is a factor ONLY during write operation

– During read operation, behave as combinational logic: Address valid => Output valid after “access time.”

Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew

Clk

5

Rw Ra Rb

32 32-bitRegisters

Rd

AL

U

Clk

Data In

DataAddress

IdealData

Memory

Instruction

InstructionAddress

IdealInstruction

Memory

Clk

PC

5Rs

5Rt

16Imm

32

323232

A

B

Nex

t A

dd

ress


Given Datapath: RTL -> Control

ALUctrRegDst ALUSrcExtOp MemtoRegMemWr Equal

Instruction<31:0>

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel

Adr

InstMemory

DATA PATH

Control

Op

<21:25>

Fun

RegWr


Meaning of the Control Signals 1

Rs, Rt, Rd and Imed16 hardwired into datapath nPC_sel: 0 => PC <– PC + 4; 1 => PC <– PC + 4 + SignExt(Im16) || 00

Adr

InstMemory

Ad

der

Ad

der

PC

Clk

00

Mu

x

4

nPC_sel

PC

Extim

m16


Meaning of the Control Signals 2ExtOp: “zero”, “sign”

ALUsrc: 0 => regB; 1 => immed

ALUctr: “add”, “sub”, “or”

MemWr: write memory

MemtoReg: 1 => Mem

RegDst: 0 => “rt”; 1 => “rd”

RegWr: write dest register

32

ALUctr

Clk

busW

RegWr

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst

Exten

der

Mu

x

3216imm16

ALUSrcExtOp

Mu

x

MemtoReg

Clk

Data InWrEn32 Adr

DataMemory

MemWr

AL

U

Equal

0

1

0

1

01

=


Example: Load Instruction

32

ALUctr

Clk

busW

RegWr

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst

Exten

der

Mu

x

3216imm16

ALUSrcExtOp

Mu

x

MemtoReg

Clk

Data InWrEn32 Adr

DataMemory

MemWr

AL

UEqual

Instruction<31:0>

0

1

0

1

01

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

=

imm

16

Ad

der

Ad

der

PC

Clk

00

Mu

x

4

nPC_sel

PC

Ext

Adr

InstMemory

sign ext

addrt+4


An Abstract View of the Implementation

Logical vs. Physical Structure

DataOut

Clk

5

Rw Ra Rb

32 32-bitRegisters

Rd

AL

U

Clk

Data In

DataAddress

IdealData

Memory

Instruction

InstructionAddress

IdealInstruction

Memory

Clk

PC

5Rs

5Rt

32

323232

A

B

Nex

t A

dd

ress

Control

Datapath

Control Signals Conditions


A Real MIPS Datapath (CNS T0)


Instruction Fetch Unit at the Beginning of Add

Fetch the instruction from Instruction memory:

Instruction <- mem[PC]– This is the same for all

instructions

PC

Ext

Adr

InstMemory

Ad

der

Ad

der

PC

Clk00

Mu

x

4

nPC_sel

imm

16

Instruction<31:0>


The Single Cycle Datapath during Add

R[rd] <- R[rs] + R[rt] op rs rt rd shamt funct

061116212631

32

ALUctr = Add

Clk

busW

RegWr = 1

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst = 1

Exten

der

Mu

x

Mux

3216imm16

ALUSrc = 0

ExtOp = x

Mu

x

MemtoReg = 0

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = 0A

LU

InstructionFetch Unit

Clk

Zero

Instruction<31:0>

0

1

0

1

01<

21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel= +4


Instruction Fetch Unit at the End of Add

PC <- PC + 4– This is the same for

all instructions except: Branch and Jump

Adr

InstMemory

Ad

der

Ad

der

PC

Clk00

Mu

x

4

nPC_sel

imm

16

Instruction<31:0>


The Single Cycle Datapath during Or Immediate

R[rt] <- R[rs] or ZeroExt[Imm16]

op rs rt immediate

016212631

32

ALUctr =

Clk

busW

RegWr =

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst =

Exten

der

Mu

x

Mux

3216imm16

ALUSrc =

ExtOp =

Mu

x

MemtoReg =

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr =

AL

U


Clk

Zero

Instruction<31:0>

0

1

0

1

01<

21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel =


The Single Cycle Datapath during LoadR[rt] <- Data Memory {R[rs] +

SignExt[imm16]}

op rs rt immediate

016212631

32

ALUctr = Add

Clk

busW

RegWr = 1

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst = 0

Exten

der

Mu

x

Mux

3216imm16

ALUSrc = 1

ExtOp = 1

Mu

x

MemtoReg = 1

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = 0

AL

U


Clk

Zero

Instruction<31:0>

0

1

0

1

01<

21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel= +4


The Single Cycle Datapath during StoreData Memory {R[rs] + SignExt[imm16]} <-

R[rt]

op rs rt immediate

016212631

32

ALUctr =

Clk

busW

RegWr =

3232

busA

32

busB

55 5


Rs

Rt

Rt

RdRegDst =

Exten

der

Mu

x

Mux

3216imm16

ALUSrc =

ExtOp =

Mu

x

MemtoReg =

Clk

Data InWrEn

32

Adr

DataMemory

32

MemWr = A

LU


Clk

Zero

Instruction<31:0>

0

1

0

1

01<

21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel =


The Single Cycle Datapath during StoreData Memory {R[rs] + SignExt[imm16]} <- R[rt]

op rs rt immediate

016212631

ExtOp = 1

Instruction<31:0>

32

ALUctr = Add

Clk

busW

RegWr = 0

32

32

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst = x

Exten

der

Mu

x

Mux

3216imm16

ALUSrc = 1

Mu

x

MemtoReg = x

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = 1A

LU


Clk

Zero

0

1

0

1

01<

21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel= +4


The Single Cycle Datapath during Branchif (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0

op rs rt immediate

016212631

MemtoReg = x

32

ALUctr = Subtract

Clk

busW

RegWr = 0

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst = x

Exten

der

Mu

x

Mux

3216imm16

ALUSrc = 0

ExtOp = x

Mu

x

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = 0A

LU


Clk

Zero

Instruction<31:0>

0

1

0

1

01<

21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel= “Br”


Instruction Fetch Unit at the End of Branch

if (Zero == 1) then

PC = PC + 4 + SignExt[imm16]*4

else

PC = PC + 4

op rs rt immediate

016212631

Adr

InstMemory

Ad

der

Ad

der

PC

Clk00

Mu

x

4

nPC_sel

imm

16

Instruction<31:0>


Given Datapath: RTL -> Control

ALUctrRegDst ALUSrcExtOp MemtoRegMemWr Equal

Instruction<31:0>

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel

Adr

InstMemory

DATA PATH

Control

Op

<0:5>

Fun

RegWr


A Summary of Control Signalsinst Register Transfer

ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4

ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4”

SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4

ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4”

ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4

ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4”

LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4

ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”

STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4

ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4”

BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4

nPC_sel = “Br”, ALUctr = “sub”


A Summary of the Control Signals

op target address


op rs rt immediate

R-type

I-type

J-type

add, sub

ori, lw, sw, beq

jump

add sub ori lw sw beq jump

RegDst

ALUSrc

MemtoReg

RegWrite

MemWrite

nPCsel

Jump

ExtOp

ALUctr<2:0>

1

0

0

1

0

0

0

x

Add

1

0

0

1

0

0

0

x

Subtract

0

1

0

1

0

0

0

0

Or

0

1

1

1

0

0

0

1

Add

x

1

x

0

1

0

0

1

Add

x

0

x

0

0

1

0

x

Subtract

x

x

x

0

0

0

1

x

xxx

func

op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010Appendix A10 0000See 10 0010 We Don’t Care :-)


The Concept of Local Decoding

R-type ori lw sw beq jump

RegDst

ALUSrc

MemtoReg

RegWrite

MemWrite

Branch

Jump

ExtOp

ALUop<N:0>

1

0

0

1

0

0

0

x

“R-type”

0

1

0

1

0

0

0

0

Or

0

1

1

1

0

0

0

1

Add

x

1

x

0

1

0

0

1

Add

x

0

x

0

0

1

0

x

Subtract

x

x

x

0

0

0

1

x

xxx

op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010

MainControl

op

6

ALUControl(Local)

func

N

6ALUop

ALUctr

3

AL

U


The Encoding of ALUop

In this exercise, ALUop has to be 2 bits wide to represent:(1) “R-type” instructions

“I-type” instructions that require the ALU to perform:

(2) Or, (3) Add, and (4) Subtract

To implement the full MIPS ISA, ALUop has to be 3 bits to represent:(1) “R-type” instructions

“I-type” instructions that require the ALU to perform:

(2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi)

MainControl

op

6

ALUControl(Local)

func

N

6ALUop

ALUctr

3

R-type ori lw sw beq jumpALUop (Symbolic) “R-type” Or Add Add Subtract xxx

ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 xxx


The Decoding of the “func” Field


ALUop (Symbolic) “R-type” Or Add Add Subtract xxx

ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 xxx

MainControl

op6

ALUControl(Local)

func

N

6ALUop

ALUctr3


R-type

funct<5:0> Instruction Operation

10 0000

10 0010

10 0100

10 0101

10 1010

add

subtract

and

or

set-on-less-than

ALUctr<2:0> ALU Operation000001010110111

AddSubtract

AndOr

Set-on-less-than

Recall ALU ( P. 286 text):

ALUctr

AL

U


The “Truth Table” for the Main Control


RegDst

ALUSrc

MemtoReg

RegWrite

MemWrite

Branch

Jump

ExtOp

ALUop (Symbolic)

1

0

0

1

0

0

0

x

“R-type”

0

1

0

1

0

0

0

0

Or

0

1

1

1

0

0

0

1

Add

x

1

x

0

1

0

0

1

Add

x

0

x

0

0

1

0

x

Subtract

x

x

x

0

0

0

1

x

xxx

op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010

ALUop <2> 1 0 0 0 0 x

ALUop <1> 0 1 0 0 0 x

ALUop <0> 0 0 0 0 1 x

MainControl

op

6

ALUControl(Local)

func

3

6

ALUop

ALUctr

3

RegDst

ALUSrc

:


PLA Implementation of the Main Control

op<0>

op<5>. .op<5>. .<0>

op<5>. .<0>

op<5>. .<0>

op<5>. .<0>

op<5>. .<0>

R-type ori lw sw beq jumpRegWrite

ALUSrc

MemtoRegMemWrite

BranchJump

RegDst

ExtOp

ALUop<2>ALUop<1>ALUop<0>


Putting it All Together: A Single Cycle Processor

32

ALUctr

Clk

busW

RegWr

32

32

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst

Exten

der

Mu

x

Mux

3216imm16

ALUSrc

ExtOp

Mu

x

MemtoReg

Clk

Data InWrEn

32

Adr

DataMemory

32

MemWr

AL

U


Clk

Zero

Instruction<31:0>

0

1

0

1

01

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

MainControl

op

6

ALUControlfunc

6

3

ALUopALUctr

3RegDst

ALUSrc

:Instr<5:0>

Instr<31:26>

Instr<15:0>

nPC_sel


Drawback of this Single Cycle Processor

Long cycle time:– Cycle time must be long enough for the load instruction:

PC’s Clock -to-Q +

Instruction Memory Access Time +

Register File Access Time +

ALU Delay (address calculation) +

Data Memory Access Time +

Register File Setup Time +

Clock Skew

Cycle time for load is much longer than needed for all other instructions


° Single cycle datapath => CPI=1, CCT => long

° 5 steps to design a processor• 1. Analyze instruction set => datapath requirements

• 2. Select set of datapath components & establish clock methodology

• 3. Assemble datapath meeting the requirements

• 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.

• 5. Assemble the control logic

° Control is the hard part

° MIPS makes control easier• Instructions same size

• Source registers always in same place

• Immediates same size, location

• Operations always on registers/immediates

Control

Datapath

Memory

ProcessorInput

Output

Summary

Designing a Single Cycle Datapath & Datapath Control

Documents

Transcript of Designing a Single Cycle Datapath & Datapath Control