Design Test and Characterization of a Compact MEMSbased Frequency Synthesizer

8/13/2019 Design Test and Characterization of a Compact MEMSbased Frequency Synthesizer

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Design, test and characterization of a compact

MEMS-based frequency synthesizer

Faisal Saeed Ahmad

Department of Electrical Engineering

McGill University

Montral, Qubec, Canada

A thesis submitted to McGill University in partial fulfillment of the requirements of the

degree of Master of Engineering (Electrical Engineering)

January 2011

Faisal Saeed Ahmad, 2011


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Abstract

Extensive microelectronics research has been conducted over the past decade to

develop integrated replacements for high quality factor off-chip components. Micro-

electromechanical systems (MEMS) based technology offers great promise as a result of

improved reliability, microscale size, integration potential and eventually lower overall

cost. In this work, the design, optimization, characterization, and test of a MEMS-based

fully integrated frequency synthesizer serves to demonstrate a proof-of-concept for using

MEMS clamped-clamped beam resonators in front-end RF systems. Details regarding

system integration of the phase-locked loop, the MEMS resonator and the associated

sustaining amplifier highlight issues related to managing circuit interfaces, system level

performance and test methodology. Design and optimization of the different on-chip

synthesizer components including the charge-pump, loop filter and voltage controlled

oscillator, provides a thorough examination of the device evolution. System-level

simulation and testing, facilitated by the design of high quality printed circuit boards,

provides performance metrics that are benchmarked against conventional crystal-based

systems.


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Rsum

Au cours de la dernire dcnnie, des recherches approfondies ayant le but de

dvelopper des remplacements intgrs pour les composants facteurs de qualitsuprieurs ont vu le jour. Les microsystmes lectromcaniques (MEMS) ont le potentiel

de permettre une fiabilit amliore, une minituarusation, une grande d'intgration et

finalement une rduction de couts. Dans le cadre de ce travail, la conception,

l'optimisation, la caractrisation, et le test d'un synthtiseur de frquence entirement

intgr bas sur un MEMS est une preuve de concept de l'utilisation des rsonateurs

MEMS dans les systmes radio-frquence. Les dtails quant l'intgration de la boucle

verrouillage de phase, le rsonateur MEMS et l'amplificateur soutenant l'oscillation

reprsentent les problmes relis la gstion d'interfaces des circuits, la performance du

systme et la mthodologie de test. La conception at l'optimisation des diffrents

composants du synthtiseur, y compris le convertisseur pompe de charge, le filtre de

boucle et l'oscillateur contrl en tension, consiste en un examen minutieux de l'volution

du systme. Les simulations et les tests apports au niveau du systme et facilits par la

conception de circuits imprims de haute qualit, fournissent les paramtres de

performance ncessaires pour l'valuation de ce systme MEMS par rapport aux systmes

bass sur les cristaux de quartz conventionnels.


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Acknowledgements

First, I would like to thank my supervisor Dr. Mourad El-Gamal, who has provided

guidance and support throughout my graduate studies. His helpful advice over the past

years made this thesis possible.

Next, I would like to thank Dr. Frederic Nabki, a former student studying in the

Wireless ICs and MEMS research group at McGill. His work on the development of SiC

surface micromachining fabrication technology and associated MEMS clamped-clamped

beam resonators, as well as MEMS-based oscillators and frequency synthesizers served as the

foundation of this work. I would also like to thank Ph.D. student Karim Allidina for his

contributions and support to the frequency synthesizer project, particularly in the

development of charge pump circuitry, IC layout and laboratory testing. Finally, I would like

to thank Ph.D. student Paul Vahe-Cicek for his contributions to enhancing the performance of

the MEMS resonators in conjunction with Dr. Nabki. This thesis would not have been

possible without the insightful discussions and exchange of ideas with these three individuals.

In addition, I would like to thank my family and friends for their support throughout

this process. My always dedicated Valerie, my father Athar, my mother Gabriele and

siblings Tania, Farah and Tariq, as well as my aunt Tajie and brother-in-law Peter who all

provided endless encouragement throughout the development of this work. Finally, Iwould like to show my gratitude to my close friends, whose support over the past years

cannot go without mention.


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Contents

List of Figures................................................................................................................. viii

List of Tables..................................................................................................................... xi

Acronyms......................................................................................................................... xii

Chapter 1: Introduction.................................................................................................... 1

I. Contributions ................................................................................................................. 3

A. MEMS System Integration ....................................................................................... 3

B. Design of a High Performance RF VCO .................................................................. 3

C. High Quality PCB Development .............................................................................. 4

II. Synopsis .................................................................................................................... 5

Chapter 2: Synthesizer System Description and Noise Analysis................................... 7

I. The Frequency Synthesizer ........................................................................................... 8

A. Phase Frequency Detector (PFD) .............................................................................. 9

B. Charge Pump (CP) .................................................................................................. 10

C. Loop Filter .............................................................................................................. 12

D. Voltage Controlled Oscillator (VCO) ..................................................................... 15

E. Multimodulus Divider ............................................................................................. 17

F. Delta-Sigma () Modulator.................................................................................. 17

II. The MEMS-Based Reference Oscillator ................................................................ 18

A. The MEMS Resonator ............................................................................................ 19

B. MEMS Resonators versus Quartz Crystals ............................................................. 21

C. The Transimpedance Amplifier (TIA) .................................................................... 23

III. Synthesizer System Noise Analysis ........................................................................ 25

A. Component Phase Noise ......................................................................................... 26

1) Reference Oscillator Noise .................................................................................. 26

2) PFD Noise ........................................................................................................... 27

3) CP Noise .............................................................................................................. 27

4) Loop Filter Noise ................................................................................................ 28

5) VCO Noise .......................................................................................................... 29

6) Multimodulus Divider Noise ............................................................................... 29

7) Delta-Sigma () Modulator Noise.................................................................... 30


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B. Noise Shaping ......................................................................................................... 30

C. MEMS Resonator Phase Noise ............................................................................... 33

IV. Application Development ....................................................................................... 36

V. Conclusion .............................................................................................................. 36

Chapter 3: Integrated RF VCO Design and Optimization.......................................... 38

I. VCO Theory ................................................................................................................ 39

II. Phase Noise Theory ................................................................................................ 41

A. Leeson Phase Noise Model ..................................................................................... 42

B. Limitations of Leesons Phase Noise Model.......................................................... 44

C. An Alternative Phase Noise Model ......................................................................... 45

D. Phase Noise Simulation Models ............................................................................. 49

III. High Performance RF Oscillator Design and Optimization ................................... 50A. Baseline Oscillator Design ...................................................................................... 50

B. Phase Noise Minimization Techniques ................................................................... 52

1) Design and Optimization of the VCO Circuit Topology .................................... 52

2) Design and Optimization of the Integrated Inductor ........................................... 54

3) Optimization of the VCO Gain ........................................................................... 56

IV. Performance Evaluation .......................................................................................... 57

A. Simulation Results .................................................................................................. 57

B. Measured Results .................................................................................................... 60V. Conclusion .............................................................................................................. 61

Chapter 4: PCB Design, Characterization and Test..................................................... 63

I. Fully-Integrated Frequency Synthesizer PCB ............................................................. 64

A. PCB Design Overview ............................................................................................ 64

B. Design for Electromagnetic Compatibility ............................................................. 66

C. Specialized Off-Chip Circuitry ............................................................................... 68

1) Regulator Circuitry .............................................................................................. 68

2) Programming and Synchronization Circuitry ..................................................... 69

3) Off-Chip Loop Filter ........................................................................................... 70

D. PCB Design Evolution and Test Methodology ....................................................... 72

II. MEMS Resonator Demo PCB ................................................................................ 76

A. PCB Design Overview ............................................................................................ 76


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B. PCB Component Selection ..................................................................................... 78

C. Test Setup ................................................................................................................ 82

III. Conclusion .............................................................................................................. 83

Chapter 5: Experimental Results................................................................................... 84

I. MEMS-Based Frequency Synthesizer ........................................................................ 84

II. MEMS-Based Frequency Synthesizer with Off-Chip Loop Filter ......................... 95

III. MEMS Resonator Demo PCB ................................................................................ 97

A. Transimpedance Amplifier ..................................................................................... 97

B. Frequency Synthesizer ............................................................................................ 99

C. Performance Summary .......................................................................................... 101

IV. Conclusion ............................................................................................................ 102

Chapter 6: Conclusion................................................................................................... 103

I. Summary and Contributions ...................................................................................... 103

II. Future Directions .................................................................................................. 104

References....................................................................................................................... 106


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List of Figures

Figure 1: Frequency synthesizer block diagram including the MEMS reference oscillator 9

Figure 2: Phase frequency detector schematic diagram ..................................................... 10Figure 3: Charge pump circuit diagram ............................................................................. 11

Figure 4: Dual-path loop filter circuit schematic ............................................................... 12

Figure 5: Circuit schematic of the dual path loop filter adder ........................................... 14

Figure 6: Voltage controlled oscillator circuit schematic (Device 4) ................................ 16

Figure 7: Accumulator-based delta-sigma modulator schematic diagram......................... 18

Figure 8: Scanning electron micrograph (SEM) of a 45 m long by 25 m wide CC-beam

resonator (left) and a corresponding cross-section illustrating the beam to electrode gap

spacing (right) .................................................................................................................... 20

Figure 9: Resonator transfer characteristic (left) and linear circuit model (right) ............. 20

Figure 10: CC-beam cross-section showing material definition and device construction 21

Figure 11: Transimpedance amplifier schematic diagram ................................................. 24

Figure 12: Component noise shaping for TCXO, charge-pump, loop filter and RF VCO 31

Figure 13: Simulated PLL output phase noise and individual component contributions

(TCXO Reference) ............................................................................................................. 33

Figure 14: MEMS oscillator phase noise profile ............................................................... 34

Figure 15: Simulated PLL output noise and individual component contributions (MEMS

reference) ........................................................................................................................... 35

Figure 16: Waveforms and corresponding ISFs for an LC oscillator (left) and a ring

oscillator (right) ................................................................................................................ 46

Figure 17: Baseline VCO Schematic (left) and Micrograph of Fabricated Device (right) 51

Figure 18: Complementary VCO schematic ...................................................................... 53

Figure 19: Comparison of intertwined inductors of baseline VCO (left) with differential

inductor (right) ................................................................................................................... 56

Figure 20: Redesigned VCO Circuit Schematic (left) and Corresponding Micrograph

(right) ................................................................................................................................. 57

Figure 21: Simulated oscillation frequency versus tuning voltage for the redesigned VCO

............................................................................................................................................ 59


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Figure 22: Comparison of the measured phase noise of the baseline and redesigned VCOs

............................................................................................................................................ 60

Figure 23: Photograph of test PCB for PLL device 3 ........................................................ 64

Figure 24: Packaged PLL IC (left) and packaged MEMS resonator die (right) ................ 65

Figure 25: Voltage regulator circuit schematic .................................................................. 69

Figure 26: Pulse generating circuit schematic ................................................................... 70

Figure 27: Fourth order active loop filter circuit schematic .............................................. 71

Figure 28: Simulated synthesizer output phase noise with TCXO reference and off-chip

loop filter ............................................................................................................................ 71

Figure 29: PLL device 4 laboratory test setup ................................................................... 73

Figure 30: Photograph of test PCB for PLL device 4 ........................................................ 74

Figure 31: Schematic CLP vacuum packaged solution ..................................................... 75

Figure 32: Block diagram of MEMS resonator demo PCB ............................................... 77

Figure 33: Photograph of the MEMS resonator demo PCB .............................................. 78

Figure 34: Passive loop filter circuit schematic ................................................................. 80

Figure 35: Simulated output phase noise for demo board synthesizer with TCXO

reference using ADIsimPLL .............................................................................................. 80

Figure 36: Circuit schematic of MEMS resonator connected in Pierce oscillator

configuration ...................................................................................................................... 81

Figure 37: MEMS demo PCB laboratory test setup .......................................................... 82

Figure 38: Device 1 synthesizer die (2.5 mm by 2.5 mm) ................................................. 85




Figure 42: Device 4 synthesizer die micrograph identifying the different system

components ........................................................................................................................ 86

Figure 43: 11.6 MHz MEMS-based reference oscillator phase noise ............................... 88

Figure 44: Phase noise comparison for an 1800 MHz output (device 4) ........................... 89

Figure 45: Output phase noise comparison for fractional-N and integer-N operation ...... 89

Figure 46: Synthesizer output phase noise at 1800 MHz for the different devices ........... 90


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Figure 47: Typical example of VCO control voltage during 120 MHz change in frequency

(device 3) ........................................................................................................................... 91

Figure 48: Output spectrum of the synthesizer for frequencies spaced by 1.25 MHz about

1.8 GHz (device 3) ............................................................................................................. 92

Figure 49: Measured output spectrum of the synthesizer finely tuned in steps of 160 Hz

(approx. 0.09ppm) about 1.8 GHz (device 3) .................................................................... 92

Figure 50: Measured effect of dithering on fractional spurs (device 2) ............................ 93

Figure 51: Simulated synthesizer phase noise with on-chip and off-chip loop filter (TCXO

reference) ........................................................................................................................... 96

Figure 52: Measured synthesizer phase noise with on-chip and off-chip loop filter (device

4 - TCXO) .......................................................................................................................... 96

Figure 53: Sustaining amplifier measured open poop gain for MEMS resonator demo

PCB .................................................................................................................................... 98

Figure 54: Sustaining amplifier open loop gain measurement setup ................................. 98

Figure 55: Measured and simulated output phase noise at 1800 MHz for MEMS resonator

demo PCB .......................................................................................................................... 99

Figure 56: Measured output phase noise at 1802.4 MHz for MEMS resonator demo PCB

.......................................................................................................................................... 100


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List of Tables

Table 1: Evolution of charge pump currents for different synthesizer devices ................. 15

Table 2: Summary of loop filter and synthesizer loop characteristics (Device 4) ............. 15Table 3: Transimpedance amplifier performance summary .............................................. 25

Table 4: Skin depth of aluminum for different frequency values ...................................... 55

Table 5: Comparison of VCO simulation results ............................................................... 58

Table 6: VCO measured performance comparison to recently published VCOs .............. 61

Table 7: Typical local oscillator (LO) frequency for different wireless standards ............ 79

Table 8: Crystek VCO typical performance parameters [49] ............................................ 79

Table 9: MEMS resonator oscillator performance summary (data from [3]) .................... 87

Table 10: Frequency synthesizer performance summary and benchmarking .................... 94

Table 11: Comparison between integrated and discrete loop filter implementations ........ 97

Table 12: MEMS resonator demo PCB frequency synthesizer performance summary .. 101


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Acronyms

AGC automatic gain control

AM amplitude modulation

ASITIC analysis and simulation of inductors and transformers for integrated circuits

BNC bayonet Neill-Concelman

CLP chip-level packaging

CMOS complimentary metal-oxide semiconductor

COTS commercial off-the-shelf

CP charge pump

DC direct current

DIP dual in-line package

EMC electromagnetic compatibility

EMI electromagnetic interference

FBAR film bulk acoustic resonator

FM frequency modulation

FoM figure-of-merit

FPGA field programmable gate array

GSM global system for mobile communications

GPS global positioning system

IC integrated circuit

I/O input/output

ISF impulse sensitivity function

LC inductor capacitor

LCC leadless chip carrier

LDO low drop-outLTI linear time-invariant

LTV linear time varying

MASH multi-stage noise shaping

MEMS micro-electro mechanical system

MiM metal-insulator-metal


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N divider ratio

NMOS n-type metal oxide semiconductor

PC personal computer

PCB printed circuit board

PED personal electronic device

PFD phase frequency detector

PLL phase-locked loop

PM phase modulation

PMOS p-type metal oxide semiconductor

PN phase noise

PVT pressure, voltage and temperature

Q quality factor

RF radio frequency

RMS root mean square

SiC silicon carbide

SoC system-on-chip

SMA subminiature version A

SMT surface mount

SONET synchronous optical networking

TCXO temperature compensated crystal oscillator

TIA transimpedance amplifier

TSPL true single phase logic

UMTS universal mobile telecommunications system

VCO voltage controlled oscillator

VGA variable gain amplifier

WLAN wireless local area network

WLP wafer-level packaging


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Chapter 1

Introduction

For modern radio applications, performance is often dependent on the utilization of

high quality factor off-chip passives. Selected for their excellent spectral purity and low

insertion loss, these off-chip components typically also lead to increased power

consumption, larger form factor, and higher system cost. As a result, extensive research

has been conducted over the past decade to develop integrated replacements for off-chip

components. Micro-electromechanical systems (MEMS) based technology, covering a

wide range of devices and systems, offers great promise as a result of improved

reliability, microscale size, integration potential and eventually, lower overall cost due to

economies of scale. In addition to serving as the resonant tank for low-frequency

reference oscillators, such high-Q MEMS-based devices are also potentially applicable to

RF oscillators, switches, tunable capacitors and a wide range of filtering applications.

There is also the potential to revolutionize front-end transceiver architectures entirely,

with large quantities of high-Q MEMS devices used to create RF channel select filter

networks, as proposed in [1].

The fully integrated frequency synthesizer application developed by McGill's

Wireless IC & MEMS laboratory in [2] and [3] serves to demonstrate a proof-of-concept

for using MEMS-based clamped-clamped beam resonators in front-end RF systems. In

the near term, these MEMS-based oscillators are targeted towards less stringent wireline


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and wideband wireless applications, whereas the ultimate objective is to provide noise

performance and frequency stability that is on par with modern TCXOs.

The drive behind MEMS technology is not simply miniaturization. The emergence of

small form-factor MEMS based oscillators commercially has placed increased pressure

on crystal oscillator manufacturers to develop smaller devices. Virtually inconceivable a

few years ago, crystal oscillators are commercially available as small as 2.0x1.6 mm2,

without sacrificing performance and cost [4]. Temperature Compensated Crystal

Oscillators (TCXO) are also available in this small form factor [4] and provide an

excellent frequency stability of 2.5 ppm. As a result, the key for MEMS technology to

become commercially competitive is to achieve monolithic integration of resonators by

depositing and patterning films directly above the CMOS circuits, thus removing the need

for off-chip passives. This objective requires low-temperature processes that are limited

to materials and chemicals that are compatible with CMOS post-processing. The low

temperature low-stress silicon carbide surface micromachining fabrication developed by

Nabki et al. in [5] was a first step towards achieving these goals. The second step is the

design and characterization of the engineering application, upon which much of this

project is based. Performance in terms of frequency stability, phase noise and power

consumption are paramount to MEMS-based oscillators becoming a technically viable

alternative to crystal oscillators.

The importance of this work is that it provides detailed characterization of a

programmable MEMS-based oscillator, including design features such as the resonator

driving mechanism and oscillator programming methodology. Although MEMS based

reference and RF oscillators are beginning to emerge commercially from companies like

Discera and SiTime, no detailed specifications are readily available in the public domain

[4].

The author's role in the project development was a complement to the work

conducted by Dr. Frederic Nabki on developing the MEMS resonator technology and a

fully-integrated frequency synthesizer as part of his Ph.D. dissertation. Specifically, the

author's contribution consisted of the original dual-path loop filter design based on [6],

design of a high performance RF VCO, all activity related to printed circuit board (PCB)

design, optimization, characterization and test, as well as an independent endeavor to


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develop a small form-factor easy-to-use PCB dedicated to the rapid prototyping of the

MEMS resonators. The next section provides a summary of the three main contributions

of this work to microelectronics and MEMS research.

I.CONTRIBUTIONSThe three primary contributions of the work presented in this thesis are as follows:

A.MEMS System IntegrationA significant challenge in the development of a MEMS-based frequency synthesizer

is addressing the system integration issues involved in combining the phase-locked loop,

the MEMS resonator, the associated sustaining amplifier and required off-chip circuitry.

Issues related to managing circuit interfaces, system level performance (e.g. noise,

power), electromagnetic compatibility (EMC) and test methodology all required careful

consideration to achieve successful integration of the frequency synthesizer system. This

integration represents an important step towards System-on-Chip technology (SoC)

whereby the MEMS resonator would be DC sputtered directly above the CMOS

electronics.

B.Design of a High Performance RF VCORegardless of the type of reference oscillator that is used to source the frequency

synthesizer, the far from carrier noise will be dominated by the RF VCO. Beyond the

loop bandwidth of the phase-locked loop, noise from the phase frequency detector (PFD),

charge pump (CP) and reference are all filtered out, with the VCO noise and thermal

noise remaining. As a result, a state-of-the-art RF VCO design is paramount to achieving

the stringent phase noise requirements set by different wireless communication standards.

A thorough review of modern phase noise theory and recently published VCO designs

produced a process for topology and inductor optimization that was applied to an LC

cross-coupled pair. Improved inductor quality factor, from 4.9 to 10.9, combined with achange in circuit topology and a reduction in VCO gain translated into a phase noise

improvement from -115.5 dBc/Hz at 600 kHz offset from the carrier for the baseline to -

123.4 dBc/Hz for a complimentary cross-coupled LC VCO.


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C.High Quality PCB DevelopmentA series of high quality printed circuit boards were developed for the four device

iterations of the MEMS-based frequency synthesizer. In addition to supporting the system

test methodology and providing a programming interface for the various operating modes,

the PCBs needed to provide a configuration that allowed for switching between different

reference sources (MEMS and TCXOs). The PCB designs were also required to

accommodate both a chip-level packaged (CLP) solution and a standard PCB level

solution where the MEMS resonator and PLL/TIA IC are packaged separately. To

achieve the aforementioned objectives, careful selection of off-chip ICs, connectors and

lumped elements was needed, in addition to careful component layout in order to

minimize the potential for electromagnetic compatibility issues (e.g. crosstalk). For ease

of assembly, a standard thickness (1.5748 mm) FR4 laminate with silk screen and solder

mask layers was selected. A separate, small form-factor PCB using only commercial off-

the-shelf (COTS) surface mount components was designed for the purpose of rapid

prototyping of the MEMS resonators, as has been done in a number of prior publications,

including [7].

Further details regarding the above listedcontributions will be addressed in subsequent

chapters of the thesis, including specifics relating to design, optimization and performance.

The next section provides an overview of those chapters.The work contained in this thesis has led to a conference publication and a prominent

engineering journal publication. At the IEEE Custom Integrated Circuits Conference

(CICC) in February 2008, an article entitled A Compact and Programmable High-

Frequency Oscillator Based on a MEMS Resonator (pp. 337-340) described the second

iteration of the MEMS-based frequency synthesizer design described herein. A collective

effort, the authors specific contribution consisted of the integrated loop filter design,

system integration of components at the chip and board level, design of the printed circuit

boards, as well as experimental test and characterization of the complete system. In the

August 2009 edition of the IEEE Journal of Solid-State Circuits (JSSC), an article entitled

A Highly Integrated 1.8 GHz Frequency Synthesizer Based on a MEMS Resonator

(vol. 44, pp. 2154-2168) offered a more in-depth examination of the MEMS-based

frequency synthesizer, complemented by improved experimental data gathered from the


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third iteration of the device. The author provided the same contributions as listed above

for the CICC publication, with the addition of the design of the high performance RF

VCO that served to satisfy the stringent out-of-band phase noise specifications of the

DCS-1800 standard.

II. SYNOPSISChapter 2 provides an overview of the MEMS-based frequency synthesizer system,

including a detailed description and design evolution of each component. Also included

are a description of the MEMS clamped-clamped beam resonators, the process used to

fabricate them and the transimpedance amplifier (TIA) used to sustain oscillation. This

high-level system description provides a basis for presenting the contributions detailed in

the following Chapters. Finally, Chapter 2 closes with a system noise analysis based onCadence noise simulation and ideal noise transfer functions for a PLL system driven by a

TCXO, as well as for the same system driven by the MEMS-based reference oscillator.

Chapter 3 describes the design and optimization of the high-performance integrated

RF oscillator. The chapter begins with some basic VCO theory, followed by a discussion

of noise sources in oscillators and phase noise theory in general. The drawbacks of

Leesons phase noise model and some background theory on Hajimiris time invariant

approach are presented. Subsequently, different design and optimization strategies are

applied to a baseline LC cross-coupled pair in order to minimize phase noise and meet the

stringent DCS-1800 requirements. Finally, simulation and measured results of the free-

running VCO are provided, including a review and comparison to the current state-of-the-

art in integrated LC VCO design.

Chapter 4 describes the design of two PCBs used for characterization and test of the

fully integrated frequency synthesizer and MEMS resonators described in Chapter 2.

Whereas the first PCB design is dedicated to the PLL/TIA IC developed in-house, the

second PCB is a small form fit easy-to-use PCB designed for rapid prototyping of MEMS

resonators and built exclusively using commercial off-the-shelf surface mount

components. Included in this section are issues related to specialized PCB circuitry,

electromagnetic compatibility, test methodology and design evolution.


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Chapter 5 provides measured results for the aforementioned PCB circuits and

integrated devices, including benchmarking to the current state-of-the-art in fully-

integrated synthesizer design. The measured data is also compared to simulated data

presented in Chapters 2 and 3.

To conclude, Chapter 6 provides a summary of the contributions and the potential for

future work, including a synthesizer linearization scheme, further PLL optimization, and

MEMS resonator development.


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Chapter 2

Synthesizer System Description

and Noise Analysis

The purpose of this Chapter is to present an overview of the fully integrated

synthesizer system with MEMS-based reference oscillator, detailing the different building

blocks, including their circuitry and design evolution through the four device iterations.

Whereas the first edition of the synthesizer IC developed as part of this work was fully

functional, it fell short of DCS-1800 phase noise specifications and suffered from other

issues related to acquisition time and stability. For subsequent iterations, modificationswere made to correct these issues, as well as to improve the design, particularly in the

interest of phase noise performance. For device four, modifications were also made to the

component pin out to accommodate a novel vacuum packaging solution, which will be

described in Chapter 4.

Previous designs, such as the integrated synthesizer in [6], utilized a conventional off-

chip crystal reference oscillator. The design presented herein operates using a MEMS-

based reference oscillator, providing the potential for a completely integrated system. The

benefits of integration include a smaller form factor, shorter interconnects and reduced

parasitics largely associated with the elimination of off-chip passives. The IC incorporates

all synthesizer circuitry, as well as the sustaining amplifier of the reference oscillator,

which can be wire bonded to the MEMS resonator within the same package.

Alternatively, the amorphous silicon carbide used for fabrication of the resonator may be


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DC sputtered directly above the CMOS electronics, providing a truly fully integrated

solution. Whereas thin-film bulk acoustic wave resonators (FBAR) have also

demonstrated the capability to be used above-IC [8], these devices require larger areas,

have limited frequency tuning capability and suffer from other process related drawbacks,

as described in [3].

Following the description of synthesizer components, this Chapter provides an

overview of the MEMS clamped-clamped beam resonators developed by Nabki et al. and

detailed in [9], as well as the design of the transimpedance amplifier used here to sustain

oscillation. The MEMS resonators used in this work are limited to fundamental

frequencies ranging from 4 to 30 MHz, although the process may also be applied to

higher frequency structures. More importantly, the process is also readily extensible to

more complex MEMS structures capable of achieving quality factors in excess of 10,000.

In the near term, the primary challenges for MEMS devices to become commercially

viable include issues related to power handling, insertion loss and temperature stability.

Finally, this Chapter concludes with a detailed noise analysis of the synthesizer

system, including strategies for optimizing output phase noise performance. The noise

contributed by each PLL building block to the system output noise is evaluated using

Cadence noise simulations, with noise shaping applied using the ideal noise transfer

functions based on the point of injection. The noise analysis is conducted for a system

driven by a TCXO reference oscillator, as well as by a MEMS-based version. In each

case, the dominant noise sources are identified. This simulated data will serve as a basis

of comparison for measured results in Chapter 5.

I.THE FREQUENCY SYNTHESIZERThe frequency synthesizer is a type II charge-pump based PLL with a 4th order loop

and architecture as shown in Figure 1. The highly integrated design includes an on-chip

dual-path loop filter and LC VCO, eliminating the need for discrete components. Thedelta-sigma () fractional-N synthesizer architecture provides an output frequency that

can vary by a fractional amount of the input reference frequency, permitting the reference

to exceed the channel spacing of the communication system in question. In an integer-N

configuration, the reference frequency must be equal to the channel spacing, which is 200

kHz for the GSM standard. Since stability considerations limit the bandwidth of a type II


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PLL to roughly one-tenth the reference frequency [10], the loop bandwidth of an integer-

N synthesizer is significantly limited, resulting in longer acquisition times and higher in-

band phase noise. For the fractional-N configuration, the higher reference frequency

permits a larger PLL loop bandwidth, translating into improved lock times and better in-

band phase noise performance. Also, the reference spurs in the output spectrum appear

further from the carrier and thus benefit from filtering of the PLL loop. The drawback is

that the fractional-N configuration will also produce fractional spurs that appear close to

the carrier and are difficult to filter out, requiring careful design of the division sequence.

The operation and circuit design of the individual frequency synthesizer components

shown in Figure 1 will be detailed in the following sub-sections, including their design

evolution along the four device iterations.

Figure 1: Frequency synthesizer block diagram including the MEMS reference oscillator

A.Phase Frequency Detector (PFD)The PFD circuit outputs a DC voltage proportional to the phase and frequency

difference between the two input signals, as opposed to an ideal phase detector that

detects phase differences only. As a result, the PFD provides a significantly improved

lock time and acquisition range, two important system-level performance parameters. A


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typical phase frequency detector produces two control signals, up and down, that are

related to the time difference between the rising edges of the reference oscillator and

divided RF oscillator waveforms. The up and down signals are fed to the charge pump to

indicate whether the charge on the loop filter capacitors should be increased or decreased,

translating to a modification of the VCO control voltage.

The PFD circuit used here is a conventional design utilizing a pair of D flip-flops and

an AND gate, as shown in the Figure 2 below. An additional delay (not shown) is also

included in the reset path to ensure that there is no dead zone. The dead zone is when the

PFD is not sensitive to small changes in phase because the switching time of the charge

pump currents is longer than the propagation delay though the reset path of the PFD. The

control signal generator in Figure 2 is a PFD output stage that was originally proposed in

[6] and is used to convert the two up and down signals to a set of control signals designed

to reduce charge injection and clock feedthrough effects in the charge pump.

The phase frequency detector circuit did not undergo any significant changes during

the optimization of the frequency synthesizer from iteration one to four.

Figure 2: Phase frequency detector schematic diagram [3]

B.Charge Pump (CP)The role of the CP is to charge or discharge the loop filter capacitor in order to

generate a tuning voltage for the VCO. The conventional CP design utilizes two switched

current sources that are controlled by the up and down signals from the PFD. For the

implementation used here (Figure 3), eight PFD control signals are used to reduce the

non-ideal effects of charge feedthrough and charge injection, which in turn reduces ripple

on the control line and spurious levels in the output spectrum. To minimize charge

feedthrough, each switch is implemented using complimentary NMOS and PMOS


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transistors. To reduce charge injection, the eight control signals are timed such that there

is a small overlap between the time when the output branch (M11-M14) turns on and the

time when the dummy branch (M5-M8) turns off, and vice-versa [3]. Transistors M1, M2,

M15and M16form the CP current source, whereas transistors M3, M4, M9and M10mirror

the presence of switches in the output branch, improving current match between the

biasing and output circuitry.

Figure 3: Charge pump circuit diagram

The initial version of the CP for the first iteration of the synthesizer was as shown in

Figure 3, without the active amplifier. The addition of the active amplifier between the

two branches is used to eliminate any voltage mismatch that may exist between the two

when the switches are off [11]. As such, when the switches turn on, charge sharing

between the dummy branch and output branch is minimized. The active amplifier is

implemented using a single stage op-amp in unity-gain configuration. Without this active

amplifier, the acquisition of phase lock is delayed since the amount of charge that is

transferred to the loop filter capacitor is smaller, requiring more cycles to achieve lock.

For device four, the charge pumps were resized to improve the in-band noise performance

of the synthesizer, by maximizing the output current for a given CP noise profile, as

indicated in [12].


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In order to be used with the dual-path loop filter, two separate current-ratioed charge

pumps are needed, as well as a third for use with a discrete off-chip loop filter, to be

detailed in Chapter 4. The three charge pumps are identical, except that their current

source transistors M1, M2, M15and M16 are sized appropriately to provide the necessary

output current.

C.Loop FilterThe purpose of the loop filter is to stabilize the loop, as well as to shape the output

spectrum in order to meet system-level phase noise and lock time requirements. The

response of the PFD and CP combination to a phase step is a linear ramp, meaning that

the open-loop transfer function contains a pole at the origin [10]. Since the VCO also

contributes a pole to the transfer response around the loop, a stabilizing zero is required

from the loop filter. In the simplest case, this can be achieved by a series combination of a

capacitor and resistor connected from the charge pump output to ground. In practical

cases, this arrangement is not sufficient since a substantial amount of ripple will remain

on the control line, as well as possible feedthrough of the reference signal to the VCO,

increasing spurious levels in the output waveform. To mitigate, additional filtering and

capacitors to ground are needed, requiring further stability analysis. As an alternative, an

active loop filter may be used in cases where a switch in polarity is needed, or when the

VCO control voltage range exceeds the CP supply voltage, which is a common issue in

discrete synthesizer designs. The drawback of the active loop filter is the added noise

contribution from the op-amp.

Figure 4: Dual-path loop filter circuit schematic


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To use either the conventional passive or active loop filter configurations above

would require a large capacitance to provide the necessary low frequency stabilizing zero,

which is not amenable to on-chip integration [3]. As a result, the fourth order dual-path

loop filter architecture initially proposed in [13], and later in [6], is used (Figure 4). The

amplifier A1 is an integrator consisting of a single-stage PMOS differential pair with

active load, whereas A2 is a customized adder circuit to be described below.

The dual-path loop filter reduces the capacitance required for the low frequency

stabilizing zero by a factor equivalent to the ratio between the CP currents fed to each

branch, denoted by the variableBin Figure 4 and the equations below. In addition to the

integrator's pole from the upper branch, the pole and stabilizing zero from the parallel RC

and adder function, a third pole is added via the low-pass filter formed byR1and C1. The

purpose of this additional pole is to improve filtering at offsets far from the carrier, thus

reducing ripple that can increase spurious levels at the VCO output. The overall transfer

function and time constants of the dual-path loop filter are as given in Equation 3 below.

As shown, the effect of the adder operation is that the effective capacitance of the

stabilizing zero (z) is significantly larger than the required on-chip value.

PZTUNE VBVV (1)

IN

PP

P

Z

TUNE ICsRCsR

RB

sCV

111

1

1

1 (2)

11111

CsRCsRsC

BCCsR

I

V

ppz

zpp

IN

TUNE

(3)

ZPPZ BCCR 1P PPP CR2 113 CRP

The implementation of the adder circuit (A2) is given in Figure 5 below. The

differential pair formed by M17and M18removes the DC offset (VREF), whereas M20and

M21source bias currents equivalent to those of the differential pair so that any difference

between the integrator and low-pass filter output voltages is mirrored to M23via M22[3].

The common-drain stage M41converts the integrator output voltage (VZ) into a current,

which adds to the drain current of M40. Note that the body of M41is tied to source in order

to eliminate the body effect and maximize voltage swing.


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Figure 5: Circuit schematic of the dual path loop filter adder (A2)

The disadvantage of the dual-path loop filter is that the active components contribute

to increasing the in-band noise of the PLL. On the other hand, as opposed to the

conventional op-amp based loop filter, the thermal noise from the loop filter resistors is

reduced to zero since no current flows throughRpwhen the synthesizer is in lock because

the DC operating voltage of both branches is set to VREF. Furthermore, as mentioned

previously, another drawback is that the dual-path architecture necessitates two current-

ratioed charge pumps, increasing the required chip area and power consumption of the

synthesizer.

The loop filter design determines the PLL system bandwidth, which in turn defines

the spectral noise profile of the PLL. To minimize the total integrated noise in the PLL

output, the loop filter cutoff frequency is typically chosen to be the point of intersection

between the in-band PLL noise and the VCO noise [12]. For this application, the large

divider ratio associated with the relatively low frequency of the MEMS reference (10

MHz), combined with the quantization noise from the -modulator, leads to a relatively

high in-band noise value which requires a small loop bandwidth (< 50 kHz) to preserve

the far-from-carrier noise.

From synthesizer device 1 to device 4, modifications to the loop filter design were

made at each iteration to accommodate changes to the charge pump current and VCO

gain in order to optimize the phase noise profile of the output spectrum. The most


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significant modification was made for device four, where the multiplier ratio B was

reduced from 12 to 4. To optimize the in-band noise of the synthesizer loop, the CP

current was increased from 2.5 A to 15 A (Table 1), with the noise contribution

remaining relatively constant. In order to limit the increase in on-chip loop filter

capacitance required to achieve this increase, the multiplier ratio was reduced to 4 and the

VCO was reduced from 225 MHz/V for device 3 to 120 MHz/V for device 4. A

secondary effect of reducing the gain of the VCO was to reduce the modulation noise

from the varactor. A summary of the dual-path loop filter parameters and overall

synthesizer loop characteristics is given in Table 2 below. Note that the stability of the

loop was ensured with a phase margin of greater than 50 across the synthesizer output

frequency range.

Table 1: Evolution of charge pump currents for different synthesizer devices

Charge Pump 1

Integrator Branch

Charge Pump 2

LPF Branch

Charge Pump 3

Off-Chip

Devices 1, 2 & 3 2.5 A 30 A 110 A

Device 4 15 A 60 A 110 A

Table 2: Summary of loop filter and synthesizer loop characteristics (Device 4)

Loop Filter ParametersSynthesizer Loop Parameters

(11.6 MHz Reference Frequency)

Charge Pump Current 1 (A) 15 Order 4

Charge Pump Current 2 (A) 60 VCO Gain (MHz/V) 120

Current Multiplier 4 Output Resolution (Hz) 11

Total On-Chip Capacitance (pF) 1959 Output Frequency Range (GHz) 1.7-2.0

Zero Frequency (kHz) 6 Cutoff Frequency (kHz) 31

Second Pole Frequency (kHz) 150 Loop Bandwidth (kHz) 51

Third Pole Frequency (kHz) 150 Phase Margin (degrees) 57

D.Voltage Controlled Oscillator (VCO)

The parameters of the VCO, such as output power, frequency range and tuning gain

each have an important role to play in the overall PLL system architecture. In particular,

the VCO phase noise performance is critical to meeting system level noise specifications

since the noise outside the PLL bandwidth is not filtered. As a result, the oscillator design


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is largely driven by the challenging DCS-1800 phase noise specification at 600 kHz offset

of -116 dBc/Hz, while minimizing power consumption and chip area.

Figure 6: Voltage controlled oscillator circuit schematic (Device 4)

The RF oscillator for devices 1 and 2 was implemented using a single top-fed cross-

coupled pair configuration with intertwined inductors and PMOS accumulation mode

varactors. A 5-bit digitally controlled capacitor bank was also included for coarse tuning

in order to ensure the desired output range was maintained over PVT variations. For

device 3, the topology was re-designed to optimize for phase noise by utilizing

complimentary cross-coupled pairs and a differential tank to improve voltage swing, as

well as half-circuit symmetry to reduce flicker noise conversion in the3

/1 f region. The

tank inductor was also redesigned in terms of size and shape for best phase noise

performance. For device 4, the gain of the VCO was reduced with the objective of

improving phase noise performance and reducing the overall loop gain and thus the

capacitance required to achieve the low frequency stabilizing zero. The gain was reduced

by modifying the varactor design and including two fixed value capacitors on each side of

the differential tank. To achieve the reduced tuning range objectives, the digitally


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controlled capacitor bank was also reduced to 2 bits. The circuit schematic for the

oscillator implementation of device 4 is provided in Figure 6 above.

Chapter 3 provides a detailed examination of the high-performance RF VCO design

and optimization, including a review of the different oscillator designs and different phase

noise models.

E.Multimodulus DividerThe divider in the feedback loop of the PLL is used to divide down the RF output so

that it can be compared to the reference by the PFD. The frequency synthesizer design

presented here uses a programmable 6-bit multimodulus pulse-swallow divider. A delta-

sigma modulator is used to randomize the choice of modulus and suppress fractional

spurs by shaping the spectrum so that most of the energy content appears at large

frequency offsets. The divider architecture, which consists of a prescaler, program

counter and swallow counter, is similar to the design presented in [14]. To increase speed

of operation, the programmable counters and prescaler implemented using True Single

Phase Logic (TSPL).

Note that no major modifications were made to the multimodulus divider from device

1 through to device 4.

F.Delta-Sigma () ModulatorThe -modulator shapes the noise spectrum, reducing the noise level close to the

carrier and forcing more energy to higher frequency offsets where it can be suppressed by

the synthesizer loop filter. This feature is particularly important for reducing fractional

spurs that are characteristic of fractional-N frequency synthesizers. The -modulator

achieves this feat by rapidly switching between multiple divider values, while

maintaining the average value to synthesize the correct frequency.

The -modulator is a digital accumulator-based single-loop 3rd-order modulator

with multiple feed-forward, which enables fractional-N division (Figure 7). The

modulator's 4-bit output permits continuous fine control of the synthesizer's output

frequency over a larger range than would be feasible with a single-bit. Furthermore, the

use of multi-bit modulation also provides a greater range of outputs than a comparable


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multi-bit MASH architecture, minimizing the impact of PFD non-linearity and reducing

charge pump on-time when the synthesizer is in fractional-N lock [3].

Figure 7: Accumulator-based delta-sigma modulator schematic diagram [3]

To minimize the impact of switching noise on the synthesizer output spectrum during

lock, the calculation occurs on the opposite edge of the clock compared to the phasecomparisons of the PFD. A dithering feature has also been included to reduce the

quantization noise effects. As shown in Figure 7, the modulator has a 24-bit input

resulting in a stable mean output range of 3.5 to 11.5 with 20-bit dividing each integer

step. The resulting output resolution is as given in Equation 4, which results in a

theoretical value of approximately 11 Hz for an 11.6 MHz reference frequency. The

reason for such a high resolution is that it provides the potential to improve output

frequency stability, particularly in the presence of frequency drift in the MEMS reference

oscillator. The implementation of such a feature would require the addition of an

automatic frequency control loop to dynamically control the -modulator [3].

202

reffResolution (4)

Note that no major modifications were made to the -modulator from device 1

through to device 4.

II. THE MEMS-BASED REFERENCE OSCILLATORThe reference oscillator for the frequency synthesizer system shown in Figure 1

consists of a MEMS resonator and a sustaining amplifier connected in a positive feedback

loop. Alternatively, a negative feedback configuration could also have been used, with the

sustaining amplifier contributing a 180 degree phase shift, as in the case of Pierce


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oscillator. The drawback of the Pierce configuration is that additional appropriately sized

shunt capacitors are needed to provide the additional phase shift around the loop.

In Figure 1, the application of a DC bias voltage (Vp) to the MEMS resonator enables

electrostatic transduction of a harmonic input voltage, exciting the first flexural vibration

mode and generating an output current from the device. As such, the sustaining amplifier

that is used to compensate for the large motional resistance of the MEMS device is

required to be of the transimpedance type, that is current in and voltage out. In this

section, design details of both the MEMS resonator and transimpedance sustaining

amplifier (TIA) are discussed.

A.The MEMS ResonatorThe clamped-clamped (CC) beam resonators used here are among the simplest

resonant MEMS structures, consisting of a horizontal beam that is anchored at both

extremities above an input electrode (Figure 8). The output current that is filtered by the

mechanical resonance of the device is taken from the structure's extremities. The

magnitude of the current produced is a function of the beam's displacement ((t)), the

beam-to-electrode overlap area (AE) and beam-to-electrode gap spacing (go), as shown in

Equation 5. The resonant frequency (fo) of the device is determined by geometric

properties, such as beam thickness (TB) and beam length (LB), as well as the resonator

structural material properties, such as density () and Young's modulus (E) (Equation 6).

The resonant frequency is also related to the polarization voltage, represented in (6) by

the electrostatic tuning function (). Compared to a fixed frequency crystal reference, a

MEMS resonator has the added advantage of electrostatic frequency tuning, typically

with a range of approximately 10% [9].

The MEMS resonator can be modeled using the lumped element circuit given in

Figure 9. The typical resonator transfer characteristic, also in Figure 9, displays a pair of

resonant peaks. The series resonant peak, located at fo, is larger in magnitude than the

parallel resonance formed by the feedthrough capacitance (Co). Although this linear

model can be easily integrated into conventional circuit simulators, the drawback is that

mechanical and electrostatic nonlinearities such as Duffing behavior and resonant

frequency shifting with bias voltage are not included. These effects can be accounted for

by incorporating additional nonlinear relations into a behavioral model, as is done in [15].


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Such a model is useful for system level optimization of the reference oscillator,

particularly with regards to predicting frequency tuning and phase noise performance.

Figure 8: Scanning electron micrograph (SEM) of a 45 m long by 25 m wide CC-beam resonator (left)

and a corresponding cross-section illustrating the beam to electrode gap spacing (right) [3]

dt

td

g

VAti

o

pEo

o

2

(5)

p

B

Bpo V

E

L

TVf 103.1)(

2 (6)

Figure 9: Resonator transfer characteristic (left) and linear circuit model (right)

The structural material used here for fabrication of the MEMS CC-beam resonator is

silicon carbide (SiC) (Figure 10), which is known to have superior mechanical properties

than silicon [3]. Whereas other research teams have used polysilicon as structural material

(e.g. CC-beams in [16]), SiC is preferable on account of its higher acoustic velocity that

permits higher resonant frequencies for equally sized devices [9]. Similarly, for the same

resonant frequency the larger SiC device would have greater power handling capability,

leading to lower insertion loss and improved noise performance. Prior to the work

conducted by Nabki et al. in [5] and [9], the use of SiC was limited due to fabrication

processes requiring high temperature and/or materials that are incompatible with CMOS.

f0Transm

ission


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For the novel MEMS process detailed in [5] and used here for CC-beam resonator

fabrication, amorphous SiC is DC sputtered at low temperature (< 300C) utilizing

materials and chemicals that are entirely compatible with CMOS processing.

Figure 10: CC-beam cross-section showing material definition and device construction [3]

The resonators fabricated for this work have a thickness of 2 m, a width of 25 m

and lengths ranging from 24 mto 64 m, corresponding to resonant frequencies of 30.5

MHz to 4 MHz, respectively. Including test pads, the entire MEMS structure measures

350 m by 130 m. With the addition of the area required for the transimpedance

amplifier, the area still compares favorably to typical crystal oscillators. The original

resonators used in conjunction with device two had a gap spacing of 200 nm, requiring a

larger polarization voltage to achieve a low motional resistance. For devices three and

four, the resonator gap was reduced to 100 nm, enabling operation with polarizationvoltages as low as 2V for an 8.3 MHz device, a significant reduction from the 26V

required for the original version. In [16] a resonator's polarization voltage is shown to be

proportional to the fourth power of the gap size, consistent with the reduction observed

here. To realize the gap reduction, careful attention is needed during fabrication,

particularly with regards to gap uniformity, etch cleanliness and the release process [3].

The drawback of a smaller gap spacing is reduced power handling capability, affecting

linearity and potentially degrading phase noise performance.

B.MEMS Resonators versus Quartz CrystalsMEMS resonators operate somewhat differently than the conventional quartz crystals

they are being designed to replace. Whereas MEMS resonators rely on electrostatic

transduction, crystals use piezoelectric transduction. The greater efficiency of

piezoelectric transduction results in a smaller motional resistance, typically around 30


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for MHz crystals, compared to 2 to 26 k for the MEMS CC-beams described here. A

similar disparity exists for quality factor, with the MEMS resonators tested here ranging

from 900 to 1600, compared to conventional AT-cut crystals that range from 104to 10

5

[3]. Higher quality factors, which translate into lower jitter and lower power

consumption, have been reported for polysilicon CC-beam resonators in [16], albeit using

a thermal budget that is incompatible with CMOS post-processing. More complex

resonant MEMS devices (e.g. disk resonators in [1]) have also been shown to provide

high quality factors, in excess of 10,000 in some cases. These more complex MEMS

structures could potentially be fabricated using the same low-temperature silicon carbide

CMOS-compatible process described here without changes to the process methodology

[3].

For reference oscillators, output frequency stability over time and temperature is

imperative to providing an environmentally robust solution. A typical uncompensated

MEMS resonator has a frequency drift of 640 ppm over an 80C range [3]. On the other

hand, the AT-cut quartz crystal is the only known resonant element which can provide

less than 50 ppm frequency stability over temperature without compensation [4]. For a

TCXO, which is a crystal based oscillator that uses a thermistor or equivalent means to

generate a correction voltage that compensates for frequency drift, stability is 2.5 ppm

over temperature (-35C to + 85C). For the MEMS resonators characterized and tested

here, thermal compensation is incorporated by means of an integrated heater (Figure 10)

to improve frequency stability and extend tuning range. Note that the frequency stability

that is ultimately required from the reference oscillator depends on the communication

protocol in question. Whereas wireline protocols and wideband wireless protocols can

generally tolerate frequency accuracies of greater than 100 ppm, narrowband protocols

such as 3G cellular typically require 1.5 ppm in initial frequency accuracy and 2.5 ppm

over temperature [17].

Power handling is another area where quartz crystals outperform MEMS resonators,

with drive levels on the order of 100 W compared to only a few microwatts for MEMS

devices [3]. Greater power handling corresponds to a potentially larger voltage swing

across the resonator and thus superior phase noise performance.


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Finally, with regards to manufacturing, a quartz crystal requires several months to be

grown. Fortunately, these crystals have achieved sufficient widespread use to make them

economical. For the MEMS resonators presented herein, being fully compatible with

standard CMOS post-processing provides them with a much shorter cycle time that is

comparable with standard integrated circuits.

C.The Transimpedance Amplifier (TIA)The purpose of the TIA is to compensate for the high motional resistance (Rx) of the

MEMS resonator and hence sustain oscillation in the loop. To achieve steady-state

oscillation, two conditions described by the well-known Barkhausen stability criterion

must be simultaneously met: 1) the loop gain must be equal to unity and 2) the phase shift

around the loop must be zero or an integer multiple of 2. Although steady-state

oscillation requires a unity loop gain, a value of 2 to 3 is typically required to guarantee

startup. To meet the phase shift requirement, a bandwidth that is an order of magnitude

greater than the frequency of oscillation is needed to ensure small phase shift around the

positive feedback loop.

In addition, to minimize the phase noise in the oscillator output spectrum, the TIA

design requires low input and output resistances to minimize loading of the resonator

quality factor, as shown in Equation 7, where Ri and Ro are the input and output

resistances of the TIA, respectively. Also in the interest of noise, the TIA circuitry needs

to be equipped with automatic gain control (AGC) capability to prevent large oscillations

from exerting the MEMS resonator non-linearities. Such non-ideal effects can degrade

phase noise both close to the carrier and far-out if the amplitude is not appropriately

optimized, as demonstrated in [7] and [15].

x

oi

UnloadedLoad ed

R

RR

QQ

1

(7)

The TIA operates by amplifying the resonator output current and supplying the

associated output voltage waveform back to the MEMS device to sustain oscillation

(Figure 11). A second output is used to drive the synthesizer reference input in order to

minimize the effect on the oscillator loop gain.


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The input stage of the TIA is based on a gm-boosted common-gate amplifier, which

serves the dual purpose of providing a large gain and small input resistance to reduce

loading of the resonator's Q-factor. The variable gain amplifier stage, which consists of a

differential pair with common-mode feedback to stabilize the output voltage at mid-rail,

provides a large adjustable gain in response to VCTRLfrom the AGC. The AGC circuitry,

consisting of an envelope detector circuit and comparator circuit, controls the variable

gain amplifier. The variable gain amplifier feeds an output buffer that has a small output

resistance, serving to minimize loading effects on the resonator. A performance summary

of the TIA circuit is provided in Table 3. Note that the given power consumption does not

include test buffers, and that the highest gain corresponds to the lowest bandwidth and

vice-versa.

Figure 11: Transimpedance amplifier schematic diagram

The transimpedance amplifier design underwent relatively minor modifications

during the design evolution. It is important to note that this circuit only underwent three

iterations since the TIA for device one was of an entirely different design that will not be

considered here. For device two, the basic configuration described above was

implemented. For the third iteration, the layout was reworked to widen the input traces in

order to tolerate higher input currents from the MEMS device. Additional external buffers

were also included to facilitate testing and the power supply was completely separated

from the rest of the IC synthesizer components to reduce noise coupling. For device four,


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capacitive compensation was added to the TIA, which resulted in a slightly smaller

bandwidth, but also improved stability. In addition, on-chip decoupling capacitors were

included to permit the CMOS synthesizer/TIA IC and resonator die to be packaged

together without the use of external capacitors. Finally, also for device four, the buffers

were reworked to reduce the circuit's power consumption.

Table 3: Transimpedance amplifier performance summary

Performance ParameterSimulated Value

(4 pF Loads)

Input Resistance () 100

Output Resistance () 60

Gain (k) 11.2 to 398.1

Bandwidth (MHz) 74 to 217

Power Consumption (mW) 2.8

Supply Voltage (V) 2

Chip Area (mm2) 0.24

III. SYNTHESIZER SYSTEMNOISE ANALYSISThere are two types of noise that are of concern for synthesizer designers: spurious

noise and phase noise. Deterministic in nature, spurious noise is typically caused by

periodic disturbances in the supply voltage or control line voltage, the latter of which can

be caused by regularities in the divider sequence or charge injection from the output stage

of the PFD or CP. As mentioned previously, the synthesizer design implemented here

uses dithering to reduce spurious associated with the divider sequence, whereas dummy

branches are used to minimize the effects of charge injection from the PFD and CP.

Contrary to spurious noise, phase noise is caused by random noise sources, such as

thermal noise, device flicker noise and shot noise. To minimize phase noise, a number of

strategies were employed, which are the main subject of this section. Whereas spurious

noise appears as easily recognizable spikes in the output spectrum, phase noise appears as

a skirt around the carrier frequency.

By reducing the phase noise in the PLL system, higher modulation rates may be used,

resulting in increased capacity. Lower phase noise also translates to reduced interferer

effects such as reciprocal mixing, permitting narrower channel spacing and more efficient


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use of bandwidth. As a result, the objective of every synthesizer design is to minimize

phase noise, while also minimizing power consumption and chip area. This section will

focus on design strategies for minimizing output phase noise of fully integrated

synthesizer circuits.

A.Component Phase NoisePredicting PLL output phase noise, through simulation and sometimes measurement,

is an important part of synthesizer design. Each system component needs to be analyzed

to determine the noise voltage or current it generates. This noise value can then be

multiplied by the appropriate noise transfer function, depending on the location of

injection in the loop, with the result providing the component's contribution to the

synthesizer output phase noise. Assuming the different noise sources in the system are not

correlated, the output phase noise spectrum can then be calculated using superposition.

Note that this assumption fails if the dominant source of noise is common to the different

system components, as would be the case if substrate or supply noise were strongest [18].

In the following sub-sections, each PLL component is reviewed in the context of its

contribution to synthesizer output phase noise.

1)Reference Oscillator NoiseThe reference oscillator noise is an important contributor to the output phase noise of

the system. Depending on the in-band noise requirements, different types of reference

sources may suffice. For GSM, the spot phase noise for the reference at 1 kHz offset from

the carrier is a stringent -130 dBc/Hz, which has typically required the use of a crystal

based oscillator such as a TCXO. According to Leeson's phase noise model, oscillator

phase noise is determined by the loaded quality factor of the tank, the device noise factor

and the average output power. The main difference between a reference oscillator and an

RF oscillator is in the quality factor of the tank, which can be three orders of magnitude

higher for the reference. Other phase noise models also exist, which consider the time-

varying and non-linear properties of the oscillator. These models, as well as other

oscillator phase noise concepts, are closely examined in Chapter 3.

When fed into the synthesizer loop, the reference phase noise is multiplied by the

closed loop gain of the PLL, which is equivalent to 20log(N)within the loop bandwidth.

As a result, the motivation has been to minimize the divider ratio by maximizing the


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reference frequency. The fractional-N architecture, in which the output frequency can be

produced at fractional multiples of the reference frequency, was developed with this

objective in mind.

2) PFD NoiseThe noise from the PFD undergoes the same noise transfer function as the reference,

except that the PFD typically has a significantly lower noise voltage and is therefore not a

major contributor to output phase noise in the PLL system [18]. Nonetheless, as with all

active devices, particular attention should be paid to minimize device flicker noise, as

well as substrate and supply noise.

3) CP NoiseThe CP noise contribution to the PLL output phase noise is determined by the

magnitude of the current noise and the PFD dead zone pulse width. Whereas the CP noise

magnitude is determined by device noise, the effect of the dead zone pulse width is less

obvious. As mentioned previously, in order to ensure that the PLL is sensitive to small

differences in input phase, a delay is added to the reset path of the PFD flip flops.

Although the average current to the loop filter remains zero, this small phase difference

causes the CP to source and sink current even when the PLL is in lock. The noise injected

by the CP during lock is given by Equation 8 below, where dz is the delay in the reset

path and T is the period of the reference signal [12]. This leads to two important

conclusions about CP noise: 1) The dead-zone pulse width should be minimized, and 2)

The charge pump will inject more noise for higher reference frequencies.

2

,

2

, 2 noiseCPdz

CPn IT

i

(8)

Equation 9 illustrates the noise transfer function for the CP current noise, where G(s)

is the open loop gain,H(s)is the feedback factor, Z()is the loop filter transfer function,

KVCOis the VCO gain, Nis the divider ratio andICPis the charge pump current. Observe

that the output phase noise contribution from the CP can be minimized by maximizing the

output current for a given noise level. Note that optimization of the CP is such a way also

requires adjustment to loop filter component values if the same loop parameters

(bandwidth, phase margin, etc.) are to be maintained.


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VCOCP

VCO

CPCPn

out

KZN

Ij

KZ

sHsG

sG

Isi

s

)(

)(2

)()(1

)(2

)(

)(

,

(9)

4) Loop Filter NoiseThe loop filter noise contribution varies depending on the particular design approach.

For discrete circuit implementations, there is the option of using a passive loop filter or an

active loop filter. While the passive version benefits from lower noise, consisting only of

thermal noise from loop filter resistors, it requires a very large capacitance to provide the

necessary low-frequency zero. For the active design, device noise associated with the op-

amp and thermal noise from the resistors typically provides higher total noise at the VCO

input, albeit with slightly smaller capacitance values. The other advantage of the active

design is that the VCO control voltage is limited only by the op-amp supply voltage,

permitting its use with RF oscillators that require extended tuning voltages, often 15 V or

more. Although typically restricted to discrete designs, these oscillators can achieve the

desired frequency range with a very low tuning sensitivity, allowing for improved phase

noise performance. Note that for both active and passive instances, the size of resistors

used should be kept to a minimum to minimize thermal noise contributions and thus the

system noise floor. For fully integrated loop filter designs, even the capacitance

associated with the conventional single op-amp active design is too large for effective on-

chip integration. As such, the dual-path approach is selected, requiring the addition of a

significant amount of active circuitry to save on overall chip area, increasing device

flicker and shot noise.

The noise transfer function for the loop filter noise, which is the same as noise on the

VCO control line, is as given in Equation 10 below. As can be observed the noise

contribution from the loop filter is strongly related to the gain of the VCO, and is also

shaped differently than for the previously mentioned PLL components. The loop filter

transfer function,Z(), has a strong influence on the noise shaping, as well as other PLLsystem performance parameters, such as lock time. Noise shaping will be reviewed in-

depth in the next section.

VCOCP

VCOVCO

LFn

out

KZN

Ij

K

sHsGj

K

sv

s

)()()(1

12

)(

)(

,

(10)


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5) VCO NoiseNoise from the VCO is determined by several factors, as shown in Leeson's equation

(Equation 11). Resonator implementation, varactor design and active circuitry all have an

important role in determining the VCO's contribution to output phase noise. The transfer

function of the VCO contains a pole at the origin, which shapes the noise injected by the

active and passive devices in the oscillator circuit. As such, the noise close to the carrier

decreases at a rate of3

/1 f due to flicker

Design Test and Characterization of a Compact MEMSbased Frequency Synthesizer

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