Design of VCOs in Deep Sub-micron Technologies
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Design of VCOs in Deep Sub-micron Technologies Design of VCOs in Deep Sub-micron Technologies
Evan Kjell Jorgensen
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Design of VCOs in Deep Sub-micronTechnologies
by
Evan Kjell Jorgensen
A Thesis Submitted in Partial Fulfillment of the Requirements for theDegree of Master of Science
in Electrical and Microelectronic Engineering
Supervised by
Professor Dr. P. R. MukundDepartment of Electrical and Microelectronic Engineering
Kate Gleason College of EngineeringRochester Institute of Technology
Rochester, New YorkMay 2015
Approved by:
Dr. P. R. Mukund, ProfessorThesis Advisor, Department of Electrical and Microelectronic Engineering
Dr. James Moon, ProfessorCommittee Member, Department of Electrical and Microelectronic Engineering
Dr. Robert Pearson, ProfessorCommittee Member, Department of Electrical and Microelectronic Engineering
Thesis Release Permission Form
Rochester Institute of TechnologyKate Gleason College of Engineering
Title:
Design of VCOs in Deep Sub-micron Technologies
I, Evan Kjell Jorgensen, hereby grant permission to the Wallace Memo-
rial Library to reproduce my thesis in whole or part.
Evan Kjell Jorgensen
Date
iii
Dedication
I would like to dedicate this thesis to my father Frank Nils Jelmert
Jorgensen for his encouragement and support throughout my life. Without
his persistence in conveying to me the importance of higher education I
may not be where I am today.
In addition, the love, joy, strength and courage of my twin brother Ethan
Stian Jorgensen has always helped ward off discouragement and motivated
me to keep trying when things get tough.
iv
Acknowledgments
Throughout my graduate education Dr. Mukund has been an excellent
advisor and professor. He understands what hard work and dedication can
bring to ones life. The feedback and advise provided by him, for academics
and career path, has been invaluable. I am grateful for the support and
motivation provided by Dr. Mukund.
In addition I would like to thank Dr. Moon for his incredible quality of
teaching in the advanced device physics courses, and well as advising
during my thesis project. His dedication to education and meticulous
attention to detail inspired me to strive for such a level of dedication in all
that I do.
Thanks to all the Microelectronics Engineering professors I had during my
undergraduate career for their dedication to the students and program.
Thanks to Anand Gopalan, Fred Heaton, and John Eble at Rambus for their
support, and GlobalFoundries for fabrication of our test chip.
Thanks to my colleagues and friends at RIT for giving me a welcome
distraction from work when stress levels were high.
v
AbstractDesign of VCOs in Deep Sub-micron Technologies
Evan Kjell Jorgensen
Supervising Professor: Dr. P. R. Mukund
This work will present a more accurate frequency prediction model for
single-ended ring oscillators (ROs), a case-study comparing different ROs,
and a design method for LC voltage-controlled oscillators (LCVCOs) that
uses a MATLAB script based on analytical equations to output a graphical
design space showing performance characteristics as a function of design
parameters. Using this method, design trade-offs become clear, and the
designer can choose which performance characteristics to optimize. These
methods were used to design various topologies of ring oscillators and LCV-
COs in the GlobalFoundries 28 nm HPP CMOS technology, comparing
the performance between different topologies based on simulation results.
The results from the MATLAB design script were compared to simulation
results as well to show the effectiveness of the design methods.
Three varieties of 5 GHz voltage controlled ring oscillators were de-
signed in the GlobalFoundries 28 nm HPP CMOS technology. The first
is a low current low dropout regulator (LDO) tuned ring oscillator designed
with thin oxide devices and a 0.85 V supply. The second is a high cur-
rent LDO-tuned ring oscillator designed with medium oxide devices and
vi
a 1.5 V supply. The third is varactor-tuned ring oscillator with no LDO,
and 0.85 V supply. Performance comparison of these ring oscillator sys-
tems are presented, outlining trade-offs between tuning range, phase noise,
power dissipation, and area. The varactor-tuned ring oscillator exhibits 8.89
dBc/Hz (with power supply noise) and 16.27 dBc/Hz (without power supply
noise) improvement in phase noise over the best-performing LDO-tuned
ring oscillator. There are advantages in average power dissipation and area
for a minimal tradeoff in tuning range with the varactor-tuned ring oscillator.
Four multi-GHz LCVCOs were designed in the GlobalFoundries 28 nm
HPP CMOS technology: 15 GHz varactor-tuned NMOS-only, 9 GHz varactor-
tuned self-biased CMOS, 14.2 GHz digitally-tuned NMOS-only, and 8.2
GHz digitally-tuned self-biased CMOS. As a design method, analytical ex-
pressions describing tuning range, tank amplitude constraint, and startup
condition were used in MATLAB to output a graphical view of the design
space for both NMOS-only and CMOS LCVCOs, with maximum varactor
capacitance on the y-axis and NMOS transistor width on the x-axis. Phase
noise was predicted as well. In addition to the standard varactor control
voltage tuning method, digitally-tuned implementations of both NMOS and
CMOS LCVCOs are presented. The performance aspects of all designed
LCVCOs are compared. Both varactor-tuned and digitally-tuned NMOS
LCVCOs have lower phase noise, lower power consumption, and higher
tuning range than both CMOS topologies. The varactor-tuned NMOS LCVCO
vii
has the lowest phase noise of -97 dBc/Hz at 1 MHz offset from 15 GHz cen-
ter frequency, FOM of -172.20 dBc/Hz, and FOMT of -167.76 dBc/Hz. The
digitally-tuned CMOS LCVCO has the greatest tuning range at 10%. Phase
noise is improved by 3 dBc/Hz with the digitally-tuned CMOS topology
over varactor-tuned CMOS.
viii
Contents
Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . iv
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . 4
2 VCOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 52.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 72.3 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . 92.4 LC Voltage-Controlled Oscillator . . . . . . . . . . . . . . . 122.5 VCO Characteristics . . . . . . . . . . . . . . . . . . . . . 17
2.5.1 Center Frequency and Tuning Range . . . . . . . . . 172.5.2 Phase Noise and Jitter . . . . . . . . . . . . . . . . 192.5.3 Power Consumption and Area . . . . . . . . . . . . 212.5.4 Manufacturability . . . . . . . . . . . . . . . . . . . 22
3 Overview of VCOs Designed in This Work . . . . . . . . . . 233.1 Ring Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 23
ix
3.1.1 LDO-tuned Ring Oscillator . . . . . . . . . . . . . . 233.1.2 Varactor-tuned Ring Oscillator . . . . . . . . . . . . 26
3.2 NMOS-only LCVCO . . . . . . . . . . . . . . . . . . . . . 273.2.1 Varactor-tuned . . . . . . . . . . . . . . . . . . . . 273.2.2 Digitally-tuned . . . . . . . . . . . . . . . . . . . . 28
3.3 Self-biased CMOS LCVCO . . . . . . . . . . . . . . . . . 303.3.1 Varactor-tuned . . . . . . . . . . . . . . . . . . . . 303.3.2 Digitally-tuned . . . . . . . . . . . . . . . . . . . . 31
4 Design Methodology . . . . . . . . . . . . . . . . . . . . . . 324.1 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.1 Frequency and Propagation Delay . . . . . . . . . . 324.1.2 Phase Noise . . . . . . . . . . . . . . . . . . . . . . 354.1.3 Gate Resistance . . . . . . . . . . . . . . . . . . . . 39
4.2 NMOS-only and Self-biased CMOS LCVCOs . . . . . . . . 444.2.1 Frequency and Tuning Range . . . . . . . . . . . . 454.2.2 Tank Amplitude Constraints . . . . . . . . . . . . . 464.2.3 Startup Condition . . . . . . . . . . . . . . . . . . . 474.2.4 Phase Noise . . . . . . . . . . . . . . . . . . . . . . 48
5 Results and Discussion . . . . . . . . . . . . . . . . . . . . . 505.1 Ring Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 505.2 LCVCOs . . . . . . . . . . . . . . . . . . . . . . . . . . . 575.3 Physical Design and Test Plan . . . . . . . . . . . . . . . . 63
6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
x
A Tuning Range and Phase Noise of all LCVCOs over ProcessCorners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
xi
List of Tables
4.1 Typical mobility and field values for surface electrons andholes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1 Summary of results for ring oscillators . . . . . . . . . . . . 575.2 Summary of results . . . . . . . . . . . . . . . . . . . . . . 63
xii
List of Figures
2.1 Basic VCO symbol. . . . . . . . . . . . . . . . . . . . . . . 52.2 Simple 2-port feedback circuit with amplifier and feedback
network . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.3 Block diagram of PLL . . . . . . . . . . . . . . . . . . . . 72.4 Block diagram of CDR . . . . . . . . . . . . . . . . . . . . 82.5 Block diagram of frequency synthesizer . . . . . . . . . . . 92.6 Single-ended ring oscillator . . . . . . . . . . . . . . . . . . 102.7 Differential ring oscillator . . . . . . . . . . . . . . . . . . 122.8 Ideal parallel LC circuit . . . . . . . . . . . . . . . . . . . . 132.9 Parallel LC circuit with losses and active negative resistance 152.10 LC oscillator with cross-coupled differential pair . . . . . . 152.11 LC VCO using varactors . . . . . . . . . . . . . . . . . . . 162.12 Illustration of phase noise of a real oscillator . . . . . . . . . 20
3.1 Replica compensated LDO topology from [19] . . . . . . . 243.2 Single-ended ring oscillator with inter-nodal varactors . . . . 263.3 Varactor-tuned NMOS-only LCVCO . . . . . . . . . . . . . 273.4 Digitally-tuned NMOS-only LCVCO . . . . . . . . . . . . 293.5 Varactor-tuned CMOS LCVCO . . . . . . . . . . . . . . . . 303.6 Digitally-tuned CMOS LCVCO . . . . . . . . . . . . . . . 31
4.1 Inter-stage input and parasitic capacitances . . . . . . . . . . 334.2 Gate and channel resistance [28] . . . . . . . . . . . . . . . 40
xiii
4.3 KCL on ring oscillator stage including input and parasiticcapacitances . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1 Frequency versus number of stages . . . . . . . . . . . . . . 505.2 Predicted and simulated phase noise for 7, 9, 11, 13, and 15
stage ring oscillators . . . . . . . . . . . . . . . . . . . . . 515.3 Tuning range of VCOs . . . . . . . . . . . . . . . . . . . . 535.4 Power supply sensitivity of LDO in VCO1 and LDO in VCO2 545.5 Output noise versus frequency for all VCOs without PSN . . 555.6 Phase noise versus offset frequency for all VCOs with and
without PSN . . . . . . . . . . . . . . . . . . . . . . . . . . 565.7 NMOS LCVCO design space . . . . . . . . . . . . . . . . . 575.8 CMOS LCVCO design space . . . . . . . . . . . . . . . . . 585.9 Tuning range of varactor-tuned NMOS and CMOS LCVCOs 595.10 Tuning range of digitally-tuned NMOS and CMOS LCVCOs 605.11 Predicted phase noise of all LCVCOs . . . . . . . . . . . . 615.12 Simulated phase noise of all LCVCOs . . . . . . . . . . . . 625.13 Layout of all VCOs . . . . . . . . . . . . . . . . . . . . . . 645.14 Top level test chip layout . . . . . . . . . . . . . . . . . . . 65
A.1 Tuning Range of VT NMOS LCVCO . . . . . . . . . . . . 74A.2 Phase Noise of VT NMOS LCVCO . . . . . . . . . . . . . 75A.3 Tuning Range of DT NMOS LCVCO . . . . . . . . . . . . 75A.4 Phase Noise of DT NMOS LCVCO . . . . . . . . . . . . . 76A.5 Tuning Range of VT CMOS LCVCO . . . . . . . . . . . . 76A.6 Phase Noise of VT CMOS LCVCO . . . . . . . . . . . . . 77A.7 Tuning Range of DT CMOS LCVCO . . . . . . . . . . . . 77A.8 Phase Noise of DT CMOS LCVCO . . . . . . . . . . . . . 78
1
Chapter 1
Introduction
1.1 Motivation
The rapid growth in global communications networks has driven the demand
for high-performance communications systems that are faster and consume
less power. In fiber optic channels, the interface circuits at the emitting
and receiving ends need to be fast enough to take full advantage of the
speed of the fiber optic system. Within-high performance mobile devices,
microprocessors require a phase-locked loop (PLL) for frequency synthesis
to generate a stable clock, clock and data recovery (CDR) for high speed
IO’s, and wireless transceiver front-end circuitry that must be capable of
modulating high-speed analog signals incoming from the antenna. Voltage-
controlled oscillators (VCOs) are used within PLLs for these applications,
and in modern devices, must achieve center frequencies in the GHz range
[1–8].
In such applications, the VCO must have low phase noise first and fore-
most, low power consumption, and must be implemented within a reason-
able area. CMOS VCOs are typically designed using a ring oscillator (RO)
2
or an LC resonant voltage-controlled oscillator (LCVCO). LC oscillators
generally have better phase noise performance due to the high quality fac-
tor (Q) achievable with an LC resonant network; however, high-Q designs
require high quality on-chip inductors, increasing the cost and complexity
of the CMOS process. In addition, LC oscillators can achieve a higher
maximum frequency compared to a ring oscillator in the same process. The
ring oscillator is advantageous in tuning range, area, and manufacturability.
Even though the concept of the VCO is fairly straightforward, there are still
difficulties in the design, especially in advanced scaled deep sub-micron
CMOS technologies. The continued scaling of CMOS technologies wors-
ens short-channel effects, increases process variation and device mismatch,
increases the influence from parasitic components, and increases flicker and
thermal noise [9].
The design of VCOs includes trade-offs in speed, power, area, and ap-
plication. Accurate models and analytical expressions are needed in or-
der to shorten and simplify the design process. Without accurate models,
the designer will not be able to make informed decisions on which design
variables affect important performance parameters and may have to rely
on iterative and time-consuming simulations. This is not a recommended
design approach. Furthermore, assembling analytical expressions together
into a numerical computing environment such as MATLAB and generating a
graphical view of the design space can give the designer a powerful insight,
making the initial design as time-efficient as possible.
3
This thesis will present design methodologies using analytical expres-
sions within MATLAB generating a graphical output of the design space
including important performance parameters as a function of design vari-
ables for both ring oscillators and LCVCOs. The design method for the
ring oscillators uses existing expressions for frequency based on stage delay,
and with the addition of parasitics and gate resistance terms. The LCVCO
design method includes expressions for frequency, tuning range, startup
condition, and tank amplitude constraint, derived for two separate LCVCO
circuit topologies. Using these design methods, ring oscillators and LCV-
COs of various topologies are designed and compared, with results shown
in this thesis.
1.2 Contributions
The key contributions of this work are:
1. A model using analytical expressions in MATLAB to predict the center
oscillation frequency of ring oscillators as a function of the number
of stages. The model accounts for parasitic capacitances and gate
resistance in addition to the standard stage delay components. Phase
noise is predicted as well.
2. A design methodology for NMOS-only and self-biased CMOS LCV-
COs using MATLAB to produce graphical outputs of the design space.
This is a multi-faceted design approach that shows parameters such
4
as tuning range, tank amplitude constraints, and startup condition as a
function of maximum varactor capacitance and transistor gate width in
graphical form on a single plot, giving the designer a complete view
of the design space. This method is derived for both current-biased
NMOS-only and self-biased CMOS LCVCO topologies.
3. A case study showing the disadvantages of using an LDO for tuning
and regulation on ring oscillators in a deep sub-micron technology.
4. A new LCVCO tuning method incorporating a digitally-tuned capaci-
tor bank (on both NMOS-only and self-biased CMOS LCVCOs).
5. A detailed performance comparison of ring oscillators and LCVCOs
in a deep sub-micron technology.
6. A test chip in the GlobalFoundries 28 nm HPP CMOS process to
experimentally validate designs and simulation results. Testing will
take place upon completion of fabrication in early June 2015.
1.3 Thesis Organization
This work is organized as follows: Chapter 2 presents the theory behind
both ring oscillators and LCVCOs; Chapter 3 presents the VCOs designed
in this work; Chapter 4 presents the design methodologies used for both ring
oscillators and LCVCOs; Chapter 5 shows results from design methods and
simulation; Chapter 6 presents conclusions.
5
Chapter 2
VCOs
2.1 Introduction
The voltage-controlled oscillator (VCO) is a circuit where the output is a
single-ended or differential periodic oscillating output voltage the frequency
of which is dependent on an input control voltage. A basic VCO symbol is
shown in Figure 2.1.
Figure 2.1: Basic VCO symbol.
The underlying equation for the operation a VCO is given by (2.1).
fV CO = f0 +KV COVctrl (2.1)
6
where f0 is the center frequency of the VCO, KV CO is the gain of the VCO,
Vctrl is the input control voltage to tune or change the output frequency
fV CO. The gain of the VCO determines how much Vctrl will affect the
frequency of the VCO, shown in (2.2).
KV CO =δfcδVctrl
(2.2)
As described in [10], for stable oscillation to occur the VCO must satisfy
the Barkhausen stability criteria for a 2-port feedback system shown in
Figure 2.2.
A
β(jω)
Vin Vout
Figure 2.2: Simple 2-port feedback circuit with amplifier and feedback network
The loop gain of the feedback system must satisfy the relationship in
(2.3)
|βA(jω)| = 1 (2.3)
and phase must satisfy (2.4)
∠βA(jω) = 2πk k = 1, 2, ..., n (2.4)
7
The VCO is a critical circuit block used in phase-locked loops (PLLs).
Common applications of PLLs are in frequency synthesis and clock and
data recovery circuits (CDR) where they are used as a local VCO. The
two main categories of VCOs include the ring oscillator and the LC os-
cillator (LCVCO). The LCVCO is generally capable of higher maximum
oscillation frequencies as well as better phase noise performance compared
to ring oscillators. Ring oscillators are advantageous in tuning range and
manufacturability.
2.2 Applications
The VCO is commonly used as a key component of the PLL, as shown in
Figure 2.3.
PhaseDetectorKd
Low-passFilterF (s)
VCOKv
XiVe Vc Xo
Figure 2.3: Block diagram of PLL
The PLL is a circuit that synchronizes the frequency and phase of its
output signal to the frequency and phase of a reference input signal [11].
The phase detector produces a DC output Ve that is proportional to the phase
difference of the input signal Xi and the VCO output signal Xo. The low-
pass filter attenuates any high frequency variation in Ve, giving a clean DC
8
signal, Vc, to the VCO. This signal controls the frequency of oscillation of
the VCO, decreasing or increasing until the frequency of Xo matches that
of Xi. When the difference in angular frequency of the input and output
(ωi−ωo) is much lower than the loop gain (K = KdKv), the PLL is in lock.
One common application for PLL is the clock and data recovery circuit
(CDR) shown in Figure 2.4 [7].
PhaseDetectorKd
ChargePump
Low-passFilterF (s)
VCOKv
DecisionCircuit
Din
CLK
Dout
Figure 2.4: Block diagram of CDR
As in the PLL, the phase detector compares the phase of the incoming
data (Din) to the phase of the clock (CLK) generated by the VCO. The
difference is converted into a voltage signal and applied to the charge pump.
The charge pump sends a signal through the low-pass filter, delivering a
clean DC signal to the VCO control input to either increase or decrease the
frequency of the VCO output CLK. The CLK signal drives a decision circuit
that re-synchronizes the output data (Dout) to reduce jitter.
Another application of the PLL is in the frequency synthesizer circuit
shown in Figure 2.5.
9
PhaseDetectorKd
Low-passFilterF (s)
VCOKv
÷ N
frefVe Vc fout
Figure 2.5: Block diagram of frequency synthesizer
The frequency synthesizer is widely used in radio communications and
wireless devices as a source of stable oscillation for the frequency modula-
tion and demodulation of signals. The frequency synthesizer is a PLL with
a frequency divider in the feedback path, giving the capability of generating
an accurate local oscillator whose frequency can be changed in small in-
crements. The phase detector inputs must be at the same frequency for the
PLL to lock. For this to occur, fref must be equivalent to fout/N ; therefore,
fout = N · fref . The divider multiple, N, can be incremented to enable
operation on different channels.
2.3 Ring Oscillator
A ring oscillator is a series of N delay stages where the output of the last
stage is connected to the input of the first stage in a feedback loop. For
stable oscillation, the ring must follow the Barkhausen criteria where the
ring must provide a multiple of 2π phase shift and unity voltage gain at the
10
desired oscillation frequency. Each delay stage provides π/N phase shift,
and the remaining π phase shift is provided by the DC inversion [12]. Ring
oscillators can be made of single-ended or differential delay stages. Single-
ended ring oscillators (Figure 2.6) must have an odd number of stages to
provide DC inversion for oscillation.
...N...
...N...
Figure 2.6: Single-ended ring oscillator
The frequency of oscillation is determined by the number of stages, N,
and the stage delay, td as shown in (2.5).
f0 =1
2N · td(2.5)
where stage propagation delay is
td = ηRDSeffCL (2.6)
11
Since propagation delay is the time between mid-level input and mid-
level output level, η = ln(0.5) = 0.69.
RDSeff =
1βn(VDD−V tn) + 1
βp(VDD−V tp)
2(2.7)
where βn = µnCoxnWL n
and βp = µpCoxpWL p
is the effective channel resistance
through which the load capacitance CL = Cin + Cpara of each stage is
charged or discharged depending on when the inverter is high or low.
To incorporate frequency control in the ring oscillator, either N or td
must be varied. Since it is impractical to implement a circuit that can vary
the number of stages for frequency tuning, td must be varied. One way
is to control the amount of current that is available to charge CL by using
current-starved inverters as the delay stage. This requires four transistors
stacked between VDD and GND and can prove difficult and impractical in
deep sub-micron CMOS technologies with sub-1V power supplies.
A single-ended VCO as in Figure 2.6 can be tuned by regulating VDD
with a voltage regulator such as a low dropout regulator (LDO), or by fixing
VDD and controlling varactors between each delay stage. The LDO tuning
method has good power supply noise rejection from the LDO, but has a dis-
advantage in that it requires more voltage headroom and uses significantly
more area and power. The varactor tuning method uses less area and power,
but leaves the power supply more vulnerable to noise.
12
Differential ring oscillators (Figure 2.7) are advantageous since their dif-
ferential delay stage topology provide good common-mode noise rejection.
−
+−
+−
+−
+−
+−
+−
+−
+
Figure 2.7: Differential ring oscillator
This topology must have an even number of stages if the output of the last
stage is cross-coupled before being fed back to the input of the first stage,
and an odd number of stages if the last stage output is not cross-coupled.
A common stage topology for the differential ring oscillator consists of a
source-coupled pair with a resistive load driven by a current source. An
operational amplifier is often required in a negative feedback error ampli-
fier configuration with an external reference voltage for biasing an active
resistive load. This stage topology can be difficult to realize across process
corners and supply variation in sub-1V technologies.
2.4 LC Voltage-Controlled Oscillator
The ideal LC oscillator consists of an inductor (L), capacitor (C) driven by
an AC voltage source, shown in Figure 2.8.
13
V (t) L C
Figure 2.8: Ideal parallel LC circuit
The reactances are given by (2.8)
XL = ωL and XC =1
ωC(2.8)
For oscillation to occur, the reactances must be equal. Setting the two
equal and solving for ω gives
ω0 =1√LC
or f0 =1
2π√LC
(2.9)
Ideal inductors and capacitors are not physically attainable because there
are losses in the form of a positive parasitic series resistance Rs. Quality
factor for the LC tank can be described as the ratio of energy stored to energy
dissipated per cycle [10, 13].
QE =ωEstored
Pdiss(2.10)
where
14
Estored =LsI
2max
2(2.11)
and
Pdiss =RsI
2max
2(2.12)
giving tank quality factor
Qtank =ωLsRs
(2.13)
where Rs is the parasitic series resistance associated with the inductor. This
series resistance Rs can be converted into a parallel resistance Rp described
as
Rp =LsCRs
= Q2tankRs (2.14)
Although Rs is a more accurate representation of the actual physical
losses of an integrated inductor, the equivalent parallel representation Rp is
often easier to work with when considering other elements of the LCVCO.
The parasitic resistance Rp must be canceled out by a negative resistance
that is equal in magnitude [10]. Figure 2.9 shows an LC tank with parallel
15
parasitic resistance Rp and negative resistance −Rp.
L C Rp −Rp
Figure 2.9: Parallel LC circuit with losses and active negative resistance
A common method of realizing this compensating negative resistance in
a monolithic LC oscillator is with a cross-coupled differential pair as shown
in Figure 2.10.
L C Rp Rp C L
−2/gm
Figure 2.10: LC oscillator with cross-coupled differential pair
The 2-port resistance seen between the two drain nodes of the active
devices is −2/gm [10]. This negative resistance must be equivalent to the
positive resistance 2Rp from the LC tank losses for steady oscillation. From
(2.8) the oscillation frequency is dependent on L and C. Since monolithic
inductors are not tunable, frequency control must come from C. This can be
achieved using varactors as in Figure 2.11.
16
L
Cv
Vctrl
Cv
L
−2/gm
Figure 2.11: LC VCO using varactors
The topology shown in Figure 2.11 is known as NMOS-only biased with
a current source to ground. An NMOS FET is often used as the current
mirror. This topology can also be biased with a current source to the supply,
where a PMOS FET would be used as the current mirror. Other topologies
include PMOS-only differential pair with either current source to ground or
the supply.
The NMOS-only topology provides higher maximum center frequencies
over those using PMOS differential pairs due to higher electron mobility. It
also gives a higher output voltage swing, of up to twice the supply level, due
to the inductors being tied to the supply. This can be beneficial in reducing
phase noise through signal maximization, but if not carefully designed can
cause degradation due to hot electron effects or gate oxide breakdown, lead-
ing to poor reliability [10]. Topologies with the current source to ground
17
have the smallest sensitivity to noise on the ground line but high sensitivity
to noise on the supply, and the opposite can be said about those with the
current source to the supply.
2.5 VCO Characteristics
There are several important performance characteristics of VCOs that the
designer must be aware of to choose which topology is most beneficial
depending on the intended application. These include center frequency
and tuning range, phase noise and jitter, power consumption and area, and
manufacturability. Manufacturability includes ease of integration with stan-
dard CMOS technologies and digital circuitry, and the effect of process
variations.
2.5.1 Center Frequency and Tuning Range
Frequency characteristics of a VCO include center frequency and tuning
range. The center frequency is the frequency at which the VCO can operate
in the middle of the range of its control voltage, given by (2.1). Higher cen-
ter frequencies are desired as the demand for higher speed communications
systems and serial data transfer rates increases.
The tuning range is the range in which oscillation can be varied around
the center frequency, usually measured in percentage of the center frequency.
A VCO with a center frequency of 5 GHz and a tuning range from 4.5 GHz
to 5.5 GHz would have a tuning range of 20%. A tuning range is necessary
18
for chips or systems that need to operate over a range of frequencies. Tuning
range is also important since the frequency of a VCO can vary due to process
variations. If the frequency of the fabricated VCO is slightly different than
the intended frequency, as long as the tuning range encompasses the desired
frequency of operation, the VCO is still useful.
Higher center frequency is more easily achieved with an LCVCO due to
the inverse relationship to the LC product (2.9) and the fact that those values
can be made extremely low. Oscillation frequencies of up to 50 GHz have
been reported in [14]. The frequency of LCVCOs is limited by the need of
active devices to compensate for LC tank losses and maintain oscillation.
The maximum center frequency of ring oscillators is much lower. Using the
design method presented in Section 4.1, the oscillation frequency of an 11
stage single-ended ring oscillator in 28 nm technology is calculated to be
around 5.5 GHz.
Although ring oscillators are not capable of as high frequencies as LCV-
COs, their tuning range is often much greater. From (2.5)-(2.7) it is apparent
that there are parameters such as VDD and CL (through use of varactors) that
can be physically varied to change frequency. Tuning ranges of 10-50%
are often achievable. In the case of LCVCOs, the capacitance of the tank
varactors is often the only frequency-related parameter that can physically
be varied, limiting the tuning range. Given this, and the higher oscillation
frequency, the tuning range of LCVCOs will typically be less than that of
ring oscillators.
19
2.5.2 Phase Noise and Jitter
The output of an ideal sinusoidal oscillator can be described as
Vout(t) = V0cos[2πfct+ φ] (2.15)
where V0 is a constant amplitude, fc is the center frequency, and φ a fixed
phase. In real oscillators there are internal noise sources such as thermal
(white noise), flicker (1/f ) noise, shot noise, as well as noise from external
sources on the power supply and ground. Both of these will cause fluc-
tuations in the amplitude and phase terms of (2.15). These terms become
functions of time, and now the output of a real oscillator can be represented
as
Vout(t) = V0(t)cos[2πfct+ φ(t)] (2.16)
The fluctuations in time introduced by V0(t) and φ(t) result in sidebands
in a symmetrical distribution around fc as shown in Figure 2.12 [13].
20
Figure 2.12: Illustration of phase noise of a real oscillator
In the time domain, these frequency fluctuations are described as jitter,
usually in units of time (seconds or period cycles). Jitter is described as the
variance (σ2τ ) of the Gaussian distribution of the output signal period with a
mean value of τ = 1/ωc. Jitter characterized by the single sideband noise
spectral density and normalized to the carrier signal power in the frequency
domain is known as phase noise. Phase noise has units of dBc/Hz. In Figure
2.12, the solid center line represents the power density of the frequency
spectrum of an ideal oscillator, while the symmetrical envelopes around the
center line represent the sideband noise power spectral density originating
from jitter in the output waveform of a real oscillator. It is important to
minimize phase noise in VCOs in order to maintain a high signal-to-noise
ratio in whatever signal the VCO is modulating or demodulating.
Phase noise in a general form can be described by (2.17)
21
L(fc,∆f) = 10 · log[Psideband(fc + ∆f, 1Hz)
Pcarrier
](2.17)
which is the ratio of the power in a 1 Hz bandwidth at an offset ∆f from the
carrier, fc, divided by the power of the carrier. More detailed expressions
describing phase noise as a function of noise sources and parameters for
specific oscillator topologies have been derived in [15,16] and are presented
in later sections.
Phase noise can also be related to quality factor, Q, as shown in (2.18).
L(fc,∆f) = 10 · log[
2kT
Pcarrier·(
fc2Q∆f
)](2.18)
An LCVCO has a higher Q than a ring oscillator due to the high energy
storage per cycle in the LC tank, with the only energy dissipation occurring
due to the series resistance losses. In a ring oscillator, the energy is stored
in the equivalent capacitance of the next stage. In each cycle, the energy is
fully charged and then discharged, significantly reducing Q. Typical Q val-
ues of ring oscillators are 1.3-1.4 [17], while those of LCVCOs are usually
an order of magnitude higher [18].
2.5.3 Power Consumption and Area
Power consumption is an important criterion in VCO designs. Phase noise
can be minimized by increasing the current and amplitude of an output
22
signal, resulting in higher power consumption. However, low power con-
sumption may be desired as part of an overall system level power budget,
presenting a trade-off. In terms of VCO topology, LCVCOs have far greater
power consumption due to the need for higher currents to drive the LC tank,
especially at higher frequencies. Ring oscillators typically have lower power
consumption. Area is an important factor because it translates directly
into cost. Due to the size of integrated inductors relative to other devices,
LCVCOs usually require more area than ring oscillators.
2.5.4 Manufacturability
Manufacturability of the VCO describes ease and ability to design and fab-
ricate the VCO in a way that is integrated with other analog and digital
circuitry on the same chip in standard CMOS processes. If area is a top
priority, ring oscillators will be preferred. Other factors such as supply noise
rejection and resistance to process variation are important as well. If a VCO
must be integrated on a chip with circuitry that may present a high amount
of noise to the power supply, a differential topology or supply regulator may
be needed for supply noise rejection. Ring oscillators are more susceptible
to process variation than LCVCOs; however, with their larger tuning range,
they can still be usable.
23
Chapter 3
Overview of VCOs Designed in This Work
As part of this work, several varieties of VCOs – both ring and LC – were
designed in the GlobalFoundries 28 nm HPP CMOS technology.
3.1 Ring Oscillators
3.1.1 LDO-tuned Ring Oscillator
A common method of tuning a ring oscillator is by varying VDD with a low
dropout regulator (LDO). This serves the dual purpose of tuning and supply
noise rejection. Two separate LDO voltage regulators have been designed in
this 28 nm CMOS technology using the topology shown in Figure 3.1. One
uses thin oxide devices and a 0.85 V supply, and the other uses medium
oxide devices and a 1.5 V supply. Both use the replica compensated LDO
topology from [19], shown in Figure 3.1.
24
Figure 3.1: Replica compensated LDO topology from [19]
Conventional voltage regulators suffer from bandwidth and supply re-
jection limitations. This topology uses the replica compensation technique
proposed by Elad Alon et al. [19] to improve the phase noise of the VCO
through improved bandwidth and supply noise rejection. This topology has
been shown to improve supply noise rejection of the LDO by more than 30
dB over a 1 GHz bandwidth, and phase noise of the VCO by 8-10 dBc [20].
To improve the supply noise rejection of the regulator, the output pole
must be the dominant pole [20]. The output pole is the parallel combination
of the decoupling capacitor on the output and the output resistance. Once
the bandwidth of the amplifier has been increased by the negative feedback
the output pole becomes dominant [19]. The error amplifier consists of a
cross-coupled NMOS differential pair sharing the same PMOS active mirror
load. The amount of bias current in the differential pair and the width of the
NMOS transistors determine the loop gain of the regulator system [19]. It is
25
important to have a high gain and high bandwidth amplifier for good supply
noise rejection [19]. The product of the minimum supply rejection (Rmin)
and the regulator bandwidth (wbw) is independent of the feedback gain k and
is given by
Rmin · wbw = waAaAoRvdd (3.1)
where Aa and Ao represent the amplifier gain and output stage gain, respec-
tively, andRvdd is the inverse of open-loop supply sensitivity of the regulator
(Rvdd = 1/Svdd).
A parallel combination of diode-connected PMOS and NMOS transistors
forms the replica load that replicates the I-V characteristics of the actual
VCO. The VCO current can be expressed as
Ivco = 2(Ionp||Ionn) (3.2)
where Ionn and Ionp are the saturated drain currents of the NMOS and PMOS
in a CMOS inverter based ring oscillator. If the oscillators are sized in
such a way that both rise current and fall current are exactly the same
then the system will give minimum phase noise, which is explained by
Hajimiri et al. [15]. This replica load is preferred since it does not generate
any switching noise and offers lower parasitics, increasing bandwidth for
the RC output filter [19]. Since it is not loaded by the output decoupling
26
capacitor, it provides a faster feedback path to the input, improving supply
noise rejection [20].
3.1.2 Varactor-tuned Ring Oscillator
An alternative method of tuning a ring oscillator is by varying the internodal
capacitance using varactors placed at the output node of each delay stage,
shown in Figure 3.2.
Cv Cv
...N...
Figure 3.2: Single-ended ring oscillator with inter-nodal varactors
One advantage of this topology is higher output swing, from GND to
VDD, from not using a voltage regulator. Higher output swing enables better
phase noise performance. A disadvantage is that without use of a regulator,
the ring oscillator is more susceptible to power supply noise. This can be
mitigated through use of a separate, clean power supply for the oscillator, as
well as placing decoupling capacitors on the supply.
27
3.2 NMOS-only LCVCO
3.2.1 Varactor-tuned
A varactor-tuned NMOS-only LCVCO (VT NMOS) topology was used
as shown in Figure 3.3. A single symmetric spiral inductor with Ltank
inductance and center-tap to VDD was used in all LCVCOs.
Cv
Vctrl
CvIref
Ltank
−2/gm
Figure 3.3: Varactor-tuned NMOS-only LCVCO
28
3.2.2 Digitally-tuned
A digitally-tuned NMOS-only LCVCO (DT NMOS), shown in Figure 3.4,
was designed using four banks of varactors where Cv2 = 2Cv1, Cv3 = 4Cv1,
and Cv4 = 8Cv1 that are controlled through 4-bit external bias voltages Vb1,
Vb2, Vb3, and Vb4, where Vb1 is the LSB and Vb4 the MSB. Each bias voltage is
either 0 V or 0.85 V, making the corresponding capacitance either minimum
or maximum. Doing so gives the LCVCO a wider tuning range and better
selectivity.
29
Cv1Vb1 Cv1
Cv2Vb2 Cv2
Cv3Vb3 Cv3
Cv4Vb4 Cv4
Iref
Ltank
−2/gm
Figure 3.4: Digitally-tuned NMOS-only LCVCO
30
3.3 Self-biased CMOS LCVCO
3.3.1 Varactor-tuned
A self-biased CMOS LCVCO (VT CMOS), shown in Figure 3.5, was de-
signed utilizing both PMOS and NMOS cross-coupled differential pairs
with no current source bias. A quadrature LCVCO using this topology
was introduced in [21] and later in [22]. Removing the current source
maximizes signal swing and eliminates the phase noise source associated
with the current source [13, 23], and reduces flicker noise terms as all core
transistors are now in GHz switching bias condition [24].
CvVctrl Cv
−2/gmp
Ltank
−2/gmn
Figure 3.5: Varactor-tuned CMOS LCVCO
31
3.3.2 Digitally-tuned
A digitally-tuned variation of the CMOS LCVCO (DT CMOS) was de-
signed as well, as shown in Figure 3.6. This circuit uses the same digital
tuning scheme as the digitally-tuned NMOS-only LCVCO from Section
3.2.2.
Cv1Vb1 Cv1
Cv2Vb2 Cv2
Cv3Vb3 Cv3
Cv4Vb4 Cv4
−2/gmp
Ltank
−2/gmn
Figure 3.6: Digitally-tuned CMOS LCVCO
32
Chapter 4
Design Methodology
4.1 Ring Oscillator
The following expressions were used in MATLAB to predict the center os-
cillation frequency of ring oscillators as a function of the number of stages,
and to predict phase noise. The model accounts for parasitic capacitances
and gate resistance in addition to the standard stage delay components.
Design variables such asWp,Wn, L, VDD, andN are inputs, and technology
dependent parameters such as Cox, µn, and µp are constants.
4.1.1 Frequency and Propagation Delay
The basic expression for the center frequency of a ring oscillator is given by
f0 =1
2Ntd(4.1)
where N is the number of stages and
td = ηRDSeffCL (4.2)
is the propagation delay of a single inverter stage. Since propagation delay
33
is the time between mid-level input and mid-level output, η = ln(0.5) = 0.69.
The inter-stage load capacitance, CL = Cin +Cpara, is the capacitance seen
at each node between stages. For the varactor-tuned ring oscillator, the term
Cpara will include the mid varactor capacitance Cv.
The following RC components for propagation delay are considered at
the points on the inverter voltage transfer characteristic when either the
NFET is in triode and PFET in cutoff (Vout low and Vin high), or the PFET
in triode and NFET in cutoff (Vout high and Vin low).
RDSeff =
1βn(VDD−V tn) + 1
βp(VDD−V tp)
2(4.3)
is the effective (average) channel resistance through which the load capac-
itance is charged or discharged depending on whether Vin is low or high.
The terms βn = µnCoxnWL n
and βp = µpCoxpWL p
.
Figure 4.1 shows the inter-stage input and parasitic capacitances con-
tributing to the CL in propagation delay.
CvCdbn
Cdbp
Cgsn
Cgsp
Cgdp
Cgdn
Figure 4.1: Inter-stage input and parasitic capacitances
34
The input capacitance terms
Cin = Cgsn + Cgsp (4.4)
where
Cgsn =1
2WnLCoxn +WnCovn (4.5)
and
Cgsp =1
2WpLCoxp +WpCovp (4.6)
The terms Covn and Covp are the NMOS and PMOS gate overlap capaci-
tances per area.
The parasitic capacitance term is
Cpara = Cdbn + Cdbp + Cgdn + Cgdp + Cv (4.7)
which includes drain-body capacitance terms
Cdbn = CjnLWn + Cjswn(2L+ 2Wn) (4.8)
35
and
Cdbp = CjpLWp + Cjswp(2L+ 2Wp) (4.9)
where Cj is the zero-bias junction capacitance per unit area and Cjsw is the
zero-bias sidewall junction capacitance per perimeter length,
as well as gate-drain capacitance terms
Cgdn = WnLCoxn +WnCovn (4.10)
and
Cgdp = WpLCoxp +WpCovp (4.11)
The usual factor of 1/2 in the gate-drain capacitance terms is multiplied
by 2 due to the Miller-effect as CM = C(1 + |Av|) where Av is -1.
4.1.2 Phase Noise
In [15], the expression for the phase noise of a single-ended CMOS ring
oscillator is derived from the impulse sensitivity function (ISF). The ISF
represents the sensitivity of the output waveform to a perturbation at any
point in time. The perturbation is a current impulse in the form of injected
charge that causes an instantaneous change in voltage, ∆V = ∆qCL
due to
36
∆q on the load capacitance CL. This change in voltage results in a shift in
transition time that can be described as a change in phase.
The single-sideband phase noise spectrum due to a single noise current
source [16] is
L {∆f} =Γ2rms
8π2∆f 2
i2n/∆f
q2max
(4.12)
Γrms is the rms impulse sensitivity function,
i2n∆f
= 4kTγgd0 = 4kTγµCoxW
L∆V (4.13)
is the single-sideband power spectral density of the noise current source.
The term γ is the noise factor. It is typically 0.66 for long-channel devices
in saturation, and twice that for short-channel devices [25, 26]. For this
design, γ = 1.33 was assumed.
From Hajimiri et al. [15], assuming the thermal noise sources from delay
stage devices are uncorrelated and the waveform of each node is the same
except for the overall phase shift, the total phase noise fromN noise sources
becomes
L {fc,∆f} =8
3η
kT
P
VDDVchar
f 2c
∆f 2(4.14)
where P is power dissipation including crowbar current drawn from the
37
supply during transitions [15], shown in (4.15).
P = 2ηNVDDqmaxf0 (4.15)
During a single period, each node is charged to qmax and discharged back
to zero. The crowbar current is the extra current drawn from the supply to
ground that does not contribute to the charging of qmax.
Vchar is the characteristic voltage of the MOSFET, given by
Vchar =EcL
γ(4.16)
and Ec is the critical electric field at which carrier velocity is saturated,
also known as Esat, from the short-channel MOSFET model. Note that
phase noise is inversely proportional to power dissipation and increases
quadratically with oscillation frequency. In addition, there is only a small
dependence on the number of stages. If additional delay stages (seen as
noise sources) are added, the peak current at transition (and thus power)
must be increased in order to maintain the same oscillation frequency and
phase noise should not change significantly.
The critical field Esat can be expressed as
Esat =Esatn + Esatp
2(4.17)
where
38
Esatn =2vsatnµeffn
(4.18)
and
Esatp =2vsatpµeffp
(4.19)
Typically vsatn = 9x106 cm/s and vsatp = 8x106 cm/s.
Effective mobilities are described as
µeffn =µn0
1 +(Eeffn
E0n
)vn (4.20)
and
µeffp =µn0
1 +(Eeffp
E0n
)vp (4.21)
Table 4.1 shows values for the terms in (4.20) and (4.21), reported by
[27, 28].
Table 4.1: Typical mobility and field values for surface electrons and holes
Parameter Electron Holeµ0 (cm2/Vsec) 670 160E0 (MV/cm) 0.67 0.7
v 1.6 1.0
The effective fields, Eeffn and Eeffp are expressed as
39
Eeffn =Vgs − Vtn
6toxn+Vtn + Vz
3toxn(4.22)
and
Eeffp =|Vgs| −
∣∣Vtp∣∣6toxp
+
∣∣Vtp∣∣+ Vz
3toxp(4.23)
where Vz = 0.2 V.
4.1.3 Gate Resistance
There is an additional polysilicon gate resistance Rg present at high fre-
quencies that affects the center frequency outside of the normal propagation
delay, td (4.2). This due to non-quasi-static (NQS) effects where there is
a finite response time of the charge in the channel with respect to the gate
bias [29]. This response time is due to the distributed channel and gate
resistances. A basic model of this is shown in Figure 4.2.
Reltd is the effective sheet resistance of the gate electrode and Rch is the
channel resistance. For this purpose Reltd will be referred to as Rsh and can
be expressed as
Rsh =Rsh1Rsh2
Rsh1 +Rsh2(4.24)
where Rsh1 is the sheet resistance of the gate polysilicon and Rsh2 is the
40
Figure 4.2: Gate and channel resistance [28]
sheet resistance of the gate salicide.
The gate resistance Rg can be expressed as
Rg = Rsh
((dCGL
)+
(Weff
mL
))(4.25)
where dCG is the gate-to-contact distance, L is gate length, Weff is the
effective gate width of the inverter, and m is a multiplier of 3 [30].
The following treatment, applied to a differential ring oscillator, has been
presented in a MS thesis by S. Docking [31]. Here the same steps will be
applied to the single-ended ring oscillator.
The gate resistance affects the circuit at the input of the next stage through
the voltage drop across Rg onto Cin. This shifts the time that the output
voltage swing crosses the midpoint of VDD/2. The output voltage waveform
can be described as
41
Vout(t) =VDD
2
(1 + sin
(2πft− π
(1 +
1
N
)))(4.26)
and
t0 =N + 1
2Nf(4.27)
is the time at which Vout is at mid-swing and is equivalent to VDD/2.
The voltage on Cin at mid-swing due to the drop across Rg is now
Vout(t0)− ICin(t0)Rg =
VDD2
(4.28)
The current ICin(t) is found by applying KCL at the output node accord-
ing to Figure 4.3.
ICin(t) = IRDSp
(t) + ICpara(t)− IRDSn
(t) (4.29)
where
ICpara(t) = Cpara ·
d(VDD − Vout(t))dt
(4.30)
is the current necessary to discharge Cpara.
42
CinICinCparaICpara
IRDSp
IRDSn
Vout(t)
+−VDD
Figure 4.3: KCL on ring oscillator stage including input and parasitic capacitances
Now the terms
IRDSp(t)− IRDSn
(t) = IRDSeff(4.31)
where IRDSeffis the total current through RDSeff charging CL during a
transition and is constant. Thus it does not affect the frequency and will
be discarded. Now ICin(t) = ICpara
(t).
The derivative
d(VDD − V out(t))dt
= 2πfVDD
2cos
(2πft− π
(1 +
1
N
))(4.32)
Substituting (4.32) into (4.30) results in
43
ICpara(t) = −Cpara2πft
VDD2cos
(2πft− π
(1 +
1
N
))(4.33)
Substituting both (4.26) and (4.33) into (4.28) gives
sin
(π
2ft0N −N − 1
1
)+ 2πfRgCparacos
(π
2ft0N −N − 1
1
)= 0
(4.34)
Solving (4.34) for t0 results in
t0 =πN + π − arctan(2πf ·RgCpara)N
2πfN(4.35)
and if 2πfRgCpara) << 1, arctan(2πfRgCpara) becomes 2πfRgCpara,
resulting in
t0 =πN + π − 2πf ·RgCparaN
2πfN(4.36)
which further simplifies to
t0 =N + 1
2Nf−RgCpara (4.37)
If Rg is 0, (4.37) is identical to (4.27). This is also the same result for the
differential ring oscillator in [31]. At this point in [31], (4.33) is integrated
44
with (4.37) as a lower integration limit. The result is eventually
(1− ISSRgCpara
Vsw(Cin + Cpara)
(2−N
(1
2− 1
π
))+
2√
2N
π
)(4.38)
This is the gate resistance multiplier for a differential ring oscillator
which is multiplied onto the existing frequency expression (4.1). In (4.38),
notice the term ISS/Vsw where ISS tail current and Vsw is the voltage swing.
For this to be applied to the single-ended ring oscillator, ISS can be replaced
by IDS and Vsw by VDS resulting in 1/RDSeff . Now (4.38) becomes
(1− RgCpara
RDSeff(Cin + Cpara)
(2−N
(1
2− 1
π
))+
2√
2N
π
)(4.39)
where (4.39) is the gate resistance frequency multiplier for a single-ended
ring oscillator.
4.2 NMOS-only and Self-biased CMOS LCVCOs
The following analytical expressions were used in MATLAB to create a
design script for an NMOS-only LCVCO. Design variables such asCV ,Wn,
L, and VDD are inputs, and technology dependent parameters such as Cox,
µn, and µp are constants. Parameters such as center frequency and tuning
range, output voltage amplitude constraints, and stable startup condition are
used to construct a two-dimensional graphical view of the design space
45
with CVmaxon the y-axis and Wn on the x-axis. This method is based on
concepts presented by D. Ham and A. Hajimiri in [32]. The following
sections include terms from both NMOS and PMOS devices. For the case
of designing the NMOS-only LCVCO, the PMOS terms are omitted.
4.2.1 Frequency and Tuning Range
The center frequency of the LCVCO is given by
ω =1√
LtankCtankor f =
1
2π√LtankCtank
(4.40)
The equivalent tank capacitance
Ctank = 0.5 (CNMOS + CPMOS + CL + Cv + Cload) (4.41)
where capacitances from active devices are
CNMOS = 4Cgdn + Cgsn + Cdbn (4.42)
and
CPMOS = 4Cgdp + Cgsp + Cdbp (4.43)
Upper and lower frequency limit specifications can be set such that
46
ωmin ≥1√
LtankCtank,max(4.44)
for the lower limit, and
ωmax ≤1√
LtankCtank,min(4.45)
for the upper limit
4.2.2 Tank Amplitude Constraints
The LCVCO has two modes of operation: current-limited and voltage-
limited. In the current-limited regime the tank amplitude Vtank grows lin-
early with the bias current Ibias until it reaches the voltage-limited regime
[33]. In the voltage-limited regime the tank amplitude is limited by the
supply voltage or the point at which active devices leave saturation. The
tank amplitude constraint is determined based on the boundaries of LCVCO
operation between the current-limited and voltage-limited regime.
The minimum tank amplitude constraint is
Vtank,min =Ibias
gtank,max(4.46)
where
47
gtank = 0.5 (gon + gop + gv + gL) (4.47)
For the case of the self-biased CMOS LCVCO, the bias current Ibias is
not an independently chosen design variable as it varies based on device
size. Instead, Ibias is calculated using the short-channel MOS model satura-
tion current equation for each width within the range of widths chosen for
the design space.
The inductor conductance is
gL =1
Rp+
Rs
ω2L2ind
(4.48)
and varactor conductance is
gv = ω2C2vRv (4.49)
So maximum tank conductance gtank,max occurs at Cv,max.
4.2.3 Startup Condition
For oscillation startup, the effective negative conductance from the active
devices gactive must be at least as large as the product of small-signal loop
gain α and effective tank conductance gtank. To ensure this is met un-
der worst-case process and temperature variations, a minimum small-signal
48
loop gain of αmin = 3 is required. The startup condition is now
gactive ≥ αmingtank,max (4.50)
where
gactive = 0.5 (gmn + gmp) (4.51)
The expressions for tuning range (4.44) and (4.45), tank amplitude con-
straint (4.46), and startup condition (4.50) are solved for Cv,max in terms of
Wn and then plotted over a range of Wn.
4.2.4 Phase Noise
Phase noise for a cross-coupled LCVCO topology is given by [16]
L{∆f} =1
8π2f 2off
· 1
q2max
·∑n
(i2n
∆f· Γ2
rms,n
)(4.52)
where foff is the frequency offset from the center frequency and qmax is the
total charge swing of the tank.
qmax = V0Ctank (4.53)
and (4.52) becomes
49
L{∆f} =1
8π2f 2off
· 1
V 20 C
2tank
·∑n
(i2n
∆f· Γ2
rms,n
)(4.54)
The summation of i2n∆f thermal noise terms represent the noise power
spectral density due to cross-coupled pair drain current thermal noise [30],
inductor thermal noise, and varactor thermal noise and are given as
i2M,d
∆f= 4kTγ(gd0,n + gd0,p) (4.55)
i2ind∆f
= 4kTgL (4.56)
i2var∆f
= 4kTgv,max (4.57)
The term Γrms = 1/√
2 for a sinusoid waveform. Using (4.54), (4.55),
(4.56), and (4.57), phase noise can be approximated.
50
Chapter 5
Results and Discussion
5.1 Ring Oscillators
Figure 5.1 shows modeled frequency versus number of stages, with and
without gate resistance Rg, and simulated frequency.
Figure 5.1: Frequency versus number of stages
The model without Rg overestimates frequency by about 15%. With Rg,
the model predicts simulated frequency to within 1-2%.
51
Figure 5.2 shows predicted phase noise from (4.14) as well as simulated
phase noise for 7, 9, 11, 13, and 15 stage varactor-tuned ring oscillators.
Figure 5.2: Predicted and simulated phase noise for 7, 9, 11, 13, and 15 stage ringoscillators
Simulated phase noise follows predicted phase noise fairly close beyond
the 1 MHz offset frequency. Within the 1 MHz offset, simulated phase
noise is worse than predicted due to flicker noise contributions not being
accounted for in (4.14).
52
For the LDO versus no-LDO experiment, three 5 GHz ring VCO sys-
tems were designed and simulated. All simulation results were done using
models that include estimates of parasitics based on the SKILL code within
device p-cells. The first (VCO1) consists of a 7 stage LDO regulated ring
oscillator where the LDO was designed with thin oxide devices and corre-
sponding 0.85 V supply. Maximum transition current and thus power was
lower for this system due to a 0.15 V maximum headroom loss from the
output stage of the LDO, reducing maximum voltage on delay stages to 0.7
V instead of 0.85 V.
The second (VCO2) is a 15 stage LDO regulated ring oscillator that was
designed in an attempt to increase current by using medium oxide devices
capable of supporting 1.5 V VDD in the LDO. Current was substantially
higher in this system since up to 0.85 V can now be achieved on delay stages
due to the 1.5 V supply enabled on the LDO devices. Both LDO regulated
VCOs from systems 1 and 2 use the same topology from Figure 3.1. The
third (VCO3) is an 11 stage varactor-tuned ring oscillator receiving full 0.85
V supply on the delay stages.
Figure 5.3 shows the tuning range of all VCOs.
53
Figure 5.3: Tuning range of VCOs
The tuning range of varactor-tuned VCO3 is lower than that of the LDO-
tuned VCOs, but has greater selectivity since it is over a wider voltage range.
Figure 5.4 shows power supply noise sensitivity of the LDOs used in
VCO1 and VCO2.
54
Figure 5.4: Power supply sensitivity of LDO in VCO1 and LDO in VCO2
Power supply sensitivity of VCO2 is lower than that of VCO1. The
common-mode gain and bandwidth of the output RC filter are significant
factors in determining the supply sensitivity of the regulator. The common-
mode gain of the LDO with VCO2 is less than the LDO with VCO1 by at
least 15 dB. Also the low-pass RC filter formed by the output resistance
and decoupling capacitor of the LDO shows higher bandwidth for LDO
with VCO1 than the LDO with VCO2. Lower bandwidth of the low-pass
filter helps in the attenuation of high-frequency noise, improving the supply
sensitivity of the regulator.
Figure 5.5 shows output noise for all VCOs.
55
Figure 5.5: Output noise versus frequency for all VCOs without PSN
Notice VCO2 and VCO3 have significantly less output noise around
the noise corner, and VCO3 has slightly less than VCO2. Flicker noise
from FET devices is inversely proportional to input capacitance, so the
higher noise of VCO1 is likely due to lower capacitance as devices are sized
smaller since they are driving less current.
Figure 5.6 shows phase noise for all VCOs with and without power
supply noise (PSN). Power supply noise is modeled as device noise reflected
back into the system at VDD. VCO1 and VCO2 have PSR due to their LDOs
regulating VDD on the delay stages; VCO3 has no LDO thus no PSR.
56
Figure 5.6: Phase noise versus offset frequency for all VCOs with and without PSN
Phase noise for VCO1 and VCO2 is nearly the same with and without
PSN, showing the PSR qualities of the LDOs functioning as expected. Phase
noise for VCO3 with PSN is worse than without PSN, as expected. Despite
this, the phase noise of VCO3 is significantly better than VCO1 and VCO2
even with PSN.
Table 5.1 shows a summary of results for tuning range, phase noise,
average power dissipation, and active area.
57
Table 5.1: Summary of results for ring oscillators
VCO1 VCO2 VCO3Tuning Range (%) 90% 80% 40%
Phase Noise (1 MHz) with PSN (dBc/Hz) -53.79 -57.35 -66.24Phase Noise (1 MHz) without PSN (dBc/Hz) -53.96 -57.59 -73.86
Pavg (µW) 77 1940 750Active area (µm2) 311.2 11730 28.6
5.2 LCVCOs
Figure 5.7 shows the design space for the NMOS LCVCO.
Figure 5.7: NMOS LCVCO design space
Figure 5.8 shows the design space for the CMOS LCVCO.
58
Figure 5.8: CMOS LCVCO design space
The valid design space in Figures 5.7 and 5.8 is below the upper tuning
range limit, above the lower tuning range limit, below the tank amplitude
constraint, and below the startup condition. The designer may start by
choosing a set of values for Wn and Cv,max to fall within this area on the
graph. Stable oscillation is almost guaranteed at this point, but the design
still may not be optimized. Optimization can be achieved through sensitiv-
ity analysis with respect to the desired output specification, or by running
parametric analysis in simulation.
The following simulation results were obtained using models that include
estimates of parasitics based on the SKILL code within device p-cells. For
59
clarity, only typical process corners are shown here; however the following
simulations done over process corners can be seen in Appendix A. Figure
5.9 shows the tuning range of both the varactor-tuned NMOS-only and self-
biased CMOS LCVCOs.
Figure 5.9: Tuning range of varactor-tuned NMOS and CMOS LCVCOs
The center frequency of the VT NMOS LCVCO is 15 GHz, while that
of the VT CMOS LCVCO is 9 GHz. The NMOS-only topology shows a
tuning range of 6%, while the CMOS topology shows a tuning range of 5%.
Figure 5.10 shows the tuning range of the both the DT NMOS and DT
CMOS LCVCOs. The bias scheme to demonstrate tuning range is done
using a 4-bit square wave voltage input where Vhigh = 0.9 V and Vlow = 0 V.
60
The bias voltage source frequencies are such that fb3 = 2 · fb4, fb2 = 4 · fb4,
fb1 = 8 · fb4, showing all 24 = 16 combinations in a given time interval.
Figure 5.10: Tuning range of digitally-tuned NMOS and CMOS LCVCOs
The center frequency of the DT NMOS is 14.2 GHz with a 9% tuning
range. This is a 50% increase over the VT NMOS LCVCO. The center
frequency of the DT CMOS is 8.2 GHz with a 10% tuning range. This is a
100% increase over the VT CMOS LCVCO.
Figure 5.11 shows predicted phase noise for all LCVCOs.
61
Figure 5.11: Predicted phase noise of all LCVCOs
Phase noise of both varactor-tuned CMOS and NMOS topologies is pre-
dicted to be roughly the same, around -90 dBc/Hz at 1 MHz offset. Both
digitally-tuned CMOS and NMOS topologies are predicted to have worse
phase noise due to the decrease in output voltage swing outweighing the
increase in added capacitance. The digitally-tuned topologies are predicted
to offer a significant improvement in tuning range.
Figure 5.12 shows the simulated phase noise of all LCVCOs.
62
Figure 5.12: Simulated phase noise of all LCVCOs
The VT NMOS-only LCVCO has the lowest phase noise, with -97 dBc at
1 MHz offset from 15 GHz. The DT NMOS topology has -94 dBc at 1 MHz
offset from 14.5 GHz. The decrease in phase noise is due to a decrease in
output swing from 1.7 V to 1.5 V due to added capacitance. The VT CMOS
has -80 dBc at 1 MHz offset from 9 GHz, and DT CMOS is slightly better
at -83 dBc at 1MHz offset from 8.2 GHz. The simulated phase noise for
the self-biased CMOS topologies is slightly worse than predicted; however
simulated phase noise was improved by 3 dBc with the DT CMOS topology
over the VT CMOS topology. The decrease in voltage swing from the added
capacitance is not as significant so phase noise improves.
63
Table 5.2 shows a summary of results for tuning range (TR), phase noise
at 1 MHz offset (PN), static DC power dissipation (PDC), figure of merit
(FOM), and tuning-range-normalized figure of merit (FOMT). FOM and
FOMT are given by
FOM = L(foff)− 20 · log(f0
foff
)+ 10 · log
(PDC
1mW
)(5.1)
FOMT = FOM − 20 · log(TR
10
)(5.2)
Table 5.2: Summary of results
NMOS NMOS DT CMOS CMOS DTfc (GHz) 15 14.2 9 8.2TR (%) 6 9 5 10
PN 1 MHz (dBc/Hz) -97 -94 -80 -83PDC (mW) 6.8 6.8 17 17
FOM (dBc/Hz) -172.20 -168.72 -146.78 -148.97FOMT (dBc/Hz) -167.76 -167.81 -140.76 -148.97
5.3 Physical Design and Test Plan
Figure 5.13 shows the physical layout of all VCOs, including all LCVCOs,
5, 7, 9, 11, 13, and 15 stage ring oscillators, and the two LDO-ring oscillator
combinations. The octagonal structures are the symmetric spiral inductors,
one for each of the four LCVCOs.
64
Figure 5.13: Layout of all VCOs
The top level test chip layout is shown in Figure 5.14. There are addi-
tional circuits that were designed by colleagues, including current sources,
opamps, and a bandgap voltage reference circuit.
65
Figure 5.14: Top level test chip layout
The positive and negative outputs from each LCVCO are sent through
CML buffers and a transmission-gate muxing configuration to GSSG RF
probe pads. The outputs from the LDOs and ring VCOs are sent through
tapered inverter buffers and a transmission-gate muxing configuration to
bond pads.
The LCVCOs will be tested for tuning range and phase noise using a
network analyzer probing the GSSG RF pads. The 6 varactor-tuned ring
VCOs will be tested for center frequency versus number of stages using an
66
oscilloscope connected to the bond pads. The 3 VCOs from the LDO versus
no LDO case study will be tested for tuning range and phase noise to verify
conclusions made from simulation results.
67
Chapter 6
Conclusions
Analytical expressions were used in MATLAB to create a frequency predic-
tion model for single-ended varactor-tuned ring oscillators based on inter-
stage capacitance and gate resistance contributions. Phase noise was pre-
dicted as well. It was found that frequency is overestimated by roughly 15%
without accounting for gate resistance. With the effects of gate resistance,
frequency can be estimated to within 1-2%. The phase noise prediction was
fairly accurate beyond the 1 MHz offset frequency. Within 1 MHz offset
frequency simulated phase noise is worse than predicted due to flicker noise
contributions not being accounted for in prediction expressions.
For the case study of LDO-tuning versus no LDO-tuning, three 5 GHz
ring VCO systems were designed and simulated in the GlobalFoundries 28
nm HPP CMOS technology: VCO1 - low current thin oxide 0.85 V LDO
regulated, VCO2 - high current medium oxide 1.5 V LDO regulated, and
VCO3 - varactor tuned with no LDO. Results are summarized in Table 5.1.
VCO2 achieves better phase noise and tuning range than VCO1 as a
result of using medium oxide devices within the LDO, enabling up to 0.85
V across the delay stages and overall higher current and power dissipation
68
during delay stage transition. However, there is a 25X increase in power and
37X increase in area.
VCO3 outperforms VCO2 and VCO1 in phase noise and area while still
maintaining 750 µW power dissipation (lower than VCO2) and 20% tuning
range. The lower phase noise of VCO3 is due to higher current and power
dissipation during delay stage transition, as well as fewer noise sources from
not relying on an LDO for tuning and using varactors instead. In this 28 nm
technology with 0.85 V supply, and likely other advanced-scaled deep sub-
micron CMOS technologies at a similar frequency, a varactor-tuned ring
oscillator may be preferred over LDO-tuned ring oscillator. Although re-
sults were presented using only typical process conditions, corners analysis
has been done. Phase noise is not significantly affected by corners. Tuning
range is shifted but still includes the 5 GHz center frequency within the
range of Vctrl.
Four varieties of multi-GHz LCVCOs were designed and simulated in
this 28 nm CMOS technology: 15 GHz varactor-tuned NMOS-only, 9 GHz
varactor-tuned self-biased CMOS, 14.2 GHz digitally-tuned NMOS-only,
and 8.2 GHz digitally-tuned self-biased CMOS. Analytical expressions de-
scribing tuning range, tank amplitude constraint, and startup condition were
compiled in MATLAB and used to output a graphical view of the valid
design space for NMOS-only and self-biased CMOS LCVCOs. Phase noise
was predicted as well. A digital tuning method that improves tuning range,
selectivity, and in one case phase noise, was presented for both LCVCO
69
topologies.
Simulation of all four LCVCOs was done with results summarized in
Table 5.2. The VT NMOS-only LCVCO shows best phase noise of -97
dBc/Hz at 1 MHz offset from 15 GHz, FOM of -172.20 dBc/Hz, FOMT
of -167.76 dBc/Hz, and 6% tuning range. The DT NMOS shows slightly
worse phase noise and FOM, but nearly equivalent FOMT to that the VT
NMOS due an improved tuning range of 9%. The CMOS topologies both
show lower phase noise than both NMOS varieties, but phase, tuning range,
FOM, and FOMT were improved with the DT CMOS topology over the VT
CMOS.
A test chip containing all of these circuits was designed and taped-out
for fabrication in this 28 nm technology. Testing and characterization will
take place upon delivery in June 2015.
70
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Appendix A
Tuning Range and Phase Noise of all LCV-COs over Process Corners
Figure A.1: Tuning Range of VT NMOS LCVCO
75
Figure A.2: Phase Noise of VT NMOS LCVCO
Figure A.3: Tuning Range of DT NMOS LCVCO
76
Figure A.4: Phase Noise of DT NMOS LCVCO
Figure A.5: Tuning Range of VT CMOS LCVCO
77
Figure A.6: Phase Noise of VT CMOS LCVCO
Figure A.7: Tuning Range of DT CMOS LCVCO
78
Figure A.8: Phase Noise of DT CMOS LCVCO