Analog Signal Processing in Deep SubmicronCMOS Technologies using Inverters

K.R.RaghunandanDepartment of Electrical and

Computer EngineeringThe University of Texas at Austin

Austin, Texas - 78712Email: raghunandan@utexas.edu

Dr. Nan SunDepartment of Electrical and

Computer EngineeringThe University of Texas at Austin

Austin, Texas - 78712Email: nansun@mail.utexas.edu

Dr. T.R.ViswanathanDepartment of Electrical and

Computer EngineeringThe University of Texas at Austin

Austin, Texas - 78712Email: tviswanathan@ece.utexas.edu

Abstract—Analog signal-processing in deep sub-micron tech-nologies poses many challenges arising from both low supplyvoltage and intrinsic voltage-gain of short channel devices. Class-AB CMOS transconductance obtained by a pair of complemen-tary transistors is a widely used power efficient building blockbecause it has linear v − i characteristics. This is topologicallythe same as the logic inverter of CMOS digital systems. Thisblock enables the basic signal-processing operations of addition,subtraction, scaling and integration. Replica-circuits are used tokeep the large process, voltage and temperature (PVT) variationsunder control. Thus we can perform analog signal-processingat a level of precision required for designing high-speed datacommunication systems. This paper discusses this in a canonicalfashion. Simulation results using device models for 65 nm CMOSprocess are presented to validate these ideas.

I. INTRODUCTION

This paper presents a new mindset that moves away from theestablished design-approach based on the use of operational-amplifiers that is essential for high precision low speed appli-cations. The traditional thinking relies on the notion of infinite-gain negative-feedback to obtain highly precise operationsneeded for instrumentation. While this tradition will continuein the primary areas of audio and video signal processing sys-tems, high speed data communication requires a new approachthat exploits the speed provided by emerging technologies.Fortunately, the precision requirements here are less due to thesimplicity of digital data representation. For example, it is wellknown that data-converters for these applications need only6-bits of resolution and linearity of 5-bits is often adequate.Thus infinite gain feedback must be supplanted by finite-gain feedback configurations keeping errors within a tolerablelevel. In this paper we present building blocks that use CMOSinverters and trans-linear current mirrors for these high speedapplications requiring upto 6-bits of resolution. This requiresan open loop gain of −64 that cannot be achieved with a singleinverter. Three inverters in tandem cannot be used as thatwill make a ring oscillator. The ring amplifier proposed in [1]addresses this problem by creating a dead zone in one of theinverters of the ring to bias it at the edge of stability. However,it cannot be used for amplification in continuous time due toits settling behavior. We introduce a new building block tosolve this problem that has a good phase margin upto several

GHz. The system clock is used in conjunction with on-chipcapacitors and a bandgap voltage reference to generate preciseDC reference currents. Unless otherwise stated, minimallysized devices with low-threshold voltages and thin-oxides areused. The ”unit inverter” having Wn/Ln = 80nm/60nm andWp/Lp = 240nm/60nm in the 65-nm process technology arechosen for simulation.

II. CMOS INVERTER: ANALOG PROPERTIES

A CMOS inverter is a voltage-amplifier. When its inputand output terminals are shorted, the resulting potential isdefined as its logical threshold VLT and the quiescent currentflowing in it is defined as ILT . Consider the inverter shown inFig.1(a) that is driven by a signal source vIN and its outputoperating into a voltage source of value equal to VLT . Thevalue m in the symbol gives the number of unit invertersconnected in parallel. Its behavior approximates that of alinear transconductance element acting as a voltage controlledcurrent sink with a transconductance of gm and an outputconductance of go. The current into the output node, iOUT

is given by:

iOUT = (iN − iP ) = gm(vIN − VLT ) (1)

When current mirrors are used to invert the currents beforeaddition, as in Fig. 1(b), iP and iN change sign beforesubtraction and we get a transconductance acting as a voltagecontrolled current source, represented by the symbol of aninverter without the inversion circle.

A. Decoupling gm and go

Both gm and go of the inverter increase with ILT suchthat their ratio, defined as the intrinsic gain (A), decreaseswith ILT . Thus, choosing ILT to increase the gm comes atthe expense of a decrease in intrinsic gain. This limitationis alleviated by canceling the quiescent current at the outputstage of Fig. 1(b). This modification, shown in 2, enables usto achieve an open loop gain with reasonable phase marginsfor applying negative feedback at high frequencies as shownlater.

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(a) (b)

Fig. 1. CMOS inverter as (a) current sink (top) and symbol (bottom) (b)current source (top) and symbol (bottom)

(a) (b)

Fig. 2. Improvement of intrinsic gain by quiescent current cancellation

B. Comparison with a Differential Pair

Consider the arrangement in Fig.3 showing the implemen-tation of a transconductance based on an inverter [Fig.3] anda diff-pair [Fig.3]. The following observations can be madefor the two circuits with minimum sized transistors - (1)The inverter provides higher transconductance as comparedto the diff-pair for a given bias current. (2) The inverterprovides larger input swing for a given linearity requirementthan the diff-pair as higher overdrive voltages can be accom-modated on the input transistors for a given supply voltage.(3) The well-known benefits of a differential-pair, namely highCMRR/PSRR are less pronounced for minimally sized devicesdue to device mismatches in the input pair and/or active load.These properties are easily achieved using pseudo-differentialarrangements using inverters by trading off power. Therefore,the inverter based approach offers a suitable alternative byproviding better trade-off in terms of linearity, bandwidth andpower consumption for high speed operation.

C. Generation of Supply Voltage

The analog supply voltage VDDR for the inverters is gener-ated using replica biasing to compensate for PVT variations.VDDR is generated so that all the inverters biased have eithera well defined ILT derived from a reference current source ora well defined VLT derived from a reference voltage source.The symbols VDDR{I} and VDDR{V } are used respectivelyto denote the two cases. The circuit for generation of thetwo types of VDDR is shown in Fig. 4. When randommismatches make it impossible to match adjacent devices, itbecomes necessary to multiplex the same circuit as replicausing switches, and capacitors to store the voltage information.

(a) (b)

Fig. 3. Comparison of transconductance based on (a) CMOS inverter (b)Diff-pair

This implementation is shown in Fig. 5.

(a) (b)

Fig. 4. Generation of VDDR: (a) Idea (b) Implementation for VDDR{I}and VDDR{V }

Fig. 5. Generation of VDDR using sampled data approach

D. Controlling VLT

As shown in Fig.1(a), the logical threshold VLT can beconsidered as a non-inverting input to the inverter and canbe dynamically adjusted to provide negative feedback. Fig.6shows 3 methods for controlling the VLT of the inverterbased on - 1) varying the supply voltage (VDDA Control),2) varying the relative strengths of PMOS and NMOS devices(K Control) and 3) adding a voltage offset at the input of theinverter (Offset Control). In each of the techniques, the devicesizes (α) and threshold options (LV T , RV T or HV T ) arechosen to adjust the nominal value around which the dynamic

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control of vLT is intended. A comparison of the three methodsof control is shown in Table I.

Fig. 6. Methods of VLT Control: (a) VDDA Control (b) K Control (c)Offset Control: Shift-down (left) Shift-up (right)

TABLE ISUMMARY OF THE METHODS OF vLT CONTROL

Method VDDA control K control Offset controlRange VTN to VLT0

a 0 to VDDRb 0 to VLT0 or

VLT0 to VDDR

gm gm < gm0c gm << gm0 gm = gm0

Power d ≈ nominal > nominal > nominal

PSRRe > nominal > nominal ≈ nominalaVLT of basic inverter bWeaker control when NMOS or PMOS enter sub-threshold

region cgm of basic inverter dExcluding the replica eWith reference to VDD

E. Scaling currents and voltages

Consider an inverter with a small-signal voltage vin, level-shifted by an amount equal to VLT , applied to its input anddelivering an output-current into a diode connected inverter[Fig. 7(a)]. The output voltage is, then, a scaled version ofvin riding over the quiescent voltage of VLT . The small-signalvoltage-gain Av taking into account the output conductancesof the inverters is given by:

Av =mgm

ngm + (m+ n)go(2)

The dependence on go is due to finite voltage swing at theoutput of the first inverter which causes a proportional currentto flow through it [Fig. 7(b)].

(a) (b)

Fig. 7. (a) Voltage gain; Output as: inverting (top) and non-inverting (bottom)(b) Small-signal equivalent circuit

To obtain a current gain element the positions of the resistorand the inverter are interchanged. Thus the input-current flowsinto a diode-connected inverter generating a voltage that isapplied to the transconductance. When the latter is fed into apoint operating at a dc voltage equal to VLT , we get a linearcurrent gain Ai that is relatively insensitive to process andtemperature similar to a traditional current mirror [Fig. 8].The expression for Ai is given by:

Ai =ngm

m(gm + go)(3)

(a) (b)

Fig. 8. (a) Current gain with output as voltage controlled current : source(top) and sink (bottom) (b) Small-signal equivalent circuit

In short channel technologies, go is appreciable causing A tobe low and have substantial variation across PVT. For example,the value of A in the 65-nm process is about 10. Therefore,the values of Av and Ai shown above deviate considerablyfrom the desired value of m/n. Fig. 9 shows a way to improvethem by using negative feedback to virtually set the voltage atthe output of the first inverter to be close to VLT . The voltageand current gains of the modified circuits are given by:

Av =mg2m

ng2m + (m+ n)g2o(4)

Ai =ng2m

m(g2m + g2o)(5)

Thus modest values of Av and Ai in the range of 2 to 6 areobtained by choosing the ratio m/n.

(a) (b)

Fig. 9. A more accurate method of scaling: (a) voltage (b) current

With these basic building blocks we can add, subtract, scaleand integrate voltages or currents. Addition and subtraction aredone in the current domain. When voltages are to be addedthey are converted into currents, added and then convertedback to a voltage. When converting a sum of currents intovoltage, the scale factors contain go as well as an offset equalto VLT . For voltages, the level shift equal to VLT required atthe input is generated by using the simple circuit shown inFig. 10. Here, the feedback loop ensures that the level shift atthe output corresponds to the VLT of the inverter.

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(a) (b)

Fig. 10. Level-shifter circuit: (a) Based on replica (b) Sampled DataImplementation

III. BUILDING BLOCKS BASED ON INVERTERS

In this section we present basic analog blocks designedusing inverters biased by the appropriate VDDR. The choice ofthe circuits are made based on the following trade-offs - Forhigh speed low resolution requirements, topologies with min-imal number of devices are chosen. PSR at high frequencieswas considered. Traditional approaches use a large decouplingcapacitor at the supply node to get reasonable PSR at highfrequencies. A maximum decoupling capacitance of 5pF wasassumed to limit total device area. Different methods of VLT

control are used wherever they are needed. The building blocksare summarized along with their simulation results in Fig.11.

IV. SYSTEM LEVEL CONSIDERATIONS

The simulated results are for a low-leakage bulk CMOSprocess, optimized for designing digital circuits. The averagevalue of the threshold voltages for the low-threshold devicesis approximately 300mV . The PMOS and NMOS devicesexhibit poor matching and their analog characteristics arenot very well controlled. This limitation will be less in amixed signal process with well controlled device parameters,especially threshold voltages of the low-threshold transistors[2]. This is expected to improve further with advancedprocesses that will have symmetric threshold voltages forPMOS and NMOS devices [3], [4].

V. CONCLUSIONS

In this paper, we have presented a canonical approach fordesigning analog and mixed signal circuits using inverters forhigh speed analog signal-processing. A key idea is to obtainPSR for the circuits using locally generated supply voltages.Design of several building blocks have been demonstratedwith adequate precision for a 6-bit ADC. Currently, work onthe integration of these blocks to realize a Nyquist rate 6-bitADC operating at sampling frequency of several gigahertzwith minimal power dissipation, is in progress.

ACKNOWLEDGMENT

The authors would like to thank Silicon Laboratories Inc.for funding this research.

REFERENCES

[1] B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U.-K. Moon, “Ring amplifiers for switched capacitor circuits,” Solid-StateCircuits, IEEE Journal of, vol. 47, no. 12, pp. 2928–2942, Dec 2012.

Fig. 11. Building blocks using inverters

[2] P. Stolk and e. Tuinhout, “Cmos device optimization for mixed-signaltechnologies,” in Electron Devices Meeting, 2001. IEDM ’01. TechnicalDigest. International, 2001, pp. 10.2.1–10.2.4.

[3] D. Flandre, J.-P. Raskin, and D. Vanhoenacker-Janvier, “SOI CMOStransistors for RF and Microwave applications,” International Journalof High Speed Electronics and Systems, vol. 11, no. 04, pp. 1159–1248,2001.

[4] S. Vitale, P. Wyatt, N. Checka, J. Kedzierski, and C. Keast, “FDSOIProcess Technology for Subthreshold-Operation Ultralow-Power Elec-tronics,” Proceedings of the IEEE, vol. 98, no. 2, pp. 333–342, 2010.

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