Design of Single Stage JFET Amplifier
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Design of single stage JFET amplifier 1: Design for device parameter variations 2: Design for midpoint biasing 3: Design for Zero thermal drift 4: Graphical methord [Do not write text i ncluded in squa re bracket ] Type 1:Design against device parameter variations Step1: Selection of biasing circuit We select voltage divider (P.D) bias circuit as it provides stable quiescent point against device parameter variations [Draw the figure] Step 2:Selection of Idq Given Id min & Id max Idq = (Idmin + Id max)/2 Step 3: Selection of Vgsq Id = Idss * sqr(1- (Vgs/Vp)) Vgs = Vp * (1 - sqrt(Id/Id ss)) Calculate Vgs max by substituting Vp max , Id max & Idss max inVgs Similarly calculate Vgs min Vgsq = (Vgs max + Vgs min)/2 Step 4: Selection of Rs Rs = (mod(Vgs max) - mod(Vgs min))/(Idq max - Idq min) Step 5: Selection of Rd gm = gmo(1 - (Vgs/Vp typ)) Gain of JFET amplifier, mod(Av) = gm * RL' If RL is given RL' = (rd) parallel (Rd) parallel (RL) If RL is not given assume RL = infinity RL' = (rd) parallel (Rd) Calculate Rd from above [If required gain(Av) is greater than a specified value, select higher std value] [If required gain(Av) is equal to a specified value, select nearest standard value] Step 6: Selection of Vdsq Case 1: Vo is given & Vdd is not given Providing 15% margin we get Vdsq = 1.15 * (mod(Vp typ) + Vo peak) Case 2: Vo is not given & Vdd is given
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8/8/2019 Design of Single Stage JFET Amplifier
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