design flow se
Transcript of design flow se
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VHDL to Place-and-RouteDesign Flow Tutorial
By: Wei Lii TanAdvisor: Dr. Robert Reese
This revision: October 28, 2001
Mississippi State University
Dallas Semiconductor
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Major Changes in This Revision
Deleted all references to Design Planner. Edited design flow to use Silicon Ensemble for
floorplanning, Qplace and Wroute.
Added explanation forDisplay Options and Find
forms.
Added section on checking for shorts between
VDD and GND in the ICFB section.
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Introduction
This tutorial will guide you through the synthesis
of a fully placed-and-routed design from a VHDL
entity.
The tutorial will use the following CAD tools:
- Synopsys Design Compiler
- Cadence Silicon Ensemble
- Cadence ICFB- Modelsim QHDL
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Introduction
The following conventions will be used in
this tutorial:
- File names will be in italics, e.g./ccs/issl/micro/users/tan/myfile.vhd
- User input (e.g. what you need to type)
will be in boldface, e.g. type swsetup
cadence-ncsu
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The Example Design
The design we will be using as an example for thistutorial is a VHDL model of a Dallas
Semiconductor DS1620k temperature sensing kit.
The interface reads the temperature from the
DS1620k, then outputs the data to a seven-segment digit display.
The design also includes some simple gates for
debugging, such as a NAND gate, NOR gate,inverter, and a DFF.
A simple counter is included in the design too.
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The Example Design
The main top-level signals in the design are: inv_in, inv_out: input and output for simple
inverter
nand2in_a, nand2in_b, nand2_out: inputs andoutput for simple NAND gate.
nor2in_a, nor2in_b, nor2_out: inputs and outputfor simple NOR gate.
_csb_6_ to _csb_0_: Signals for MSB of theseven-segment digit display.
_lsb_6_ to _lsb_0_: Signals for LSB of the seven-segment digit display.
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Copying Example Files
Copy the entire directory
/ccs/issl/micro/users/tan/tutorials/design_flow into
your work directory *important*All directories will start with
your_work_directory/design_flow, unless
specified otherwise.
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Design Flow
Synopsys Design Compiler
Modelsim
Cadence Silicon Ensemble
Cadence ICFB
Modelsim
VHDL Model
Verilog Model
Verilog Model
DEF File
Verilog Model
VHDL -> Verilog
Conversion
Verilog Verification
Place-and-Route
Export to Other Formats,
SPICE Verification
Verilog Verification
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Synopsys Design Compiler
This tool will convert a VHDL model to a Verilogmodel. It requires the use of the following user-
provided files:
- Library file, in .db format.
- Script file (file extension .script)
- The VHDL file to be converted to Verilog.
At this stage, we will be using Design Compiler to
generate a Verilog model, without pads, of aVHDL file called topchip_gold_nopads.
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Synopsys Design Compiler
The VHDL file that we will be using istopchip_nopads.vhd.
Using a script file with Design Compiler,
we will convert this VHDL model toverilog.
The next page shows the script file used to
compile topchip_nopads.vhd. The script file
is called topchip_nopads.script
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Synopsys Design Compiler Script File
link_library=target_library={jennings_pads_noqn.db}
define_design_lib tempsense -path
/ccs/issl/micro/users/tan/dallas1/sc_tests/myfiles/vhdl2/rtl/tempsense
analyze -work tempsense -f vhdl{ ../rtl/tempsense/topchip_final_components.vhd../rtl/tempsense/bin2bcd_mod.vhd ../rtl/tempsense/pulse.vhd../rtl/tempsense/twoscomp.vhd ../rtl/tempsense/sev_seg_display.vhd../rtl/tempsense/ds1620_i.vhd ../rtl/tempsense/simple_gate.vhd../rtl/tempsense/topchip_count4.vhd}
read -f vhdl ../rtl/tempsense/topchip_gold_nopads.vhdset_flatten true
max_area 0.0
current_design topchip_gold_nopads
compile -ungroup_all -map_effort medium
dont_touch_network CLK
dont_touch_network clk
dont_touch_network find(pin, */r)
set_max_fanout 8.0 find(design, topchip_gold_nopads)
compile -incremental_mapping -map_effort medium
check_design
verilogout_single_bit = true
write -f verilog -output ../gate/topchip_gold_nopads_noqn.v
quit
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Why use a script file?
Using a script file with dc_shell is
equivalent to typing the exact commands in
dc_shell interactively.
A script file automates the process of typing
in all the commands manually.
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What is the .db file for?
The database (.db) file holds information
about the standard cell library used to
implement the VHDL design.
It provides information about the standard
cells: the names of the standard cells,
input/output ports, as well as timing
characteristics and functionality.
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Design Compiler
Change to the directorysynopsys/run_syn
Type swsetup synopsys
Type dc_shell f topchip_nopads.script
The -f option tells design compiler to use ascript file, and not run in interactive mode.
5. After design compiler finishes (it should take
about 5 minutes to finish the compilation), a
verilog netlist file called topchip_nopads.v
should be created in the directorysynopsis/gate.
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Design Compiler
Note: If a verilog netlist file with the samename exists in the target directory, design
compiler will overwrite it.
Now that we have a verilog file, our nextstep would be to simulate the verilog netlist
to check for errors.
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Modelsim The next step in the design flow is simulating
the verilog netlist that was generated usingSynopsys Design Compiler.
Change to the qhsim directory, and type swsetupmodelsim.
If the qhsim/workdirectory does not exist, createone by typing qhlib work.
- The qhlib work command creates a
directory called work, and also storesModelsim information in the work directory.This directory will be the object directory forstandard cells and top-level designs that are
compiled using Modelsim.
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Modelsim Before we compile our top-level design
(topchip_nopads.v), we need to compile thestandard cells that make up topchip_nopads.v. Inthe qhsim directory, type:
qvlcom ../synopsys/gate/libcells.v.
4. Type:qvlcom ../synopsys/gate/topchip_nopads.v.This will compile our top-level design file.
5. Now, type:
qvlcom ../synopsys/gate/tb_topchip_nopads.v.This will compile the testbench for our design.The testbench supplies input vectors needed totest the functionality of our design.
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Modelsim To enter Qhsim and simulate our design, type:
qhsim tb_topchip_nopads. Note that the
argument after the qhsim command refers to
the Verilog module name of our design, not the
file name. After you do step 6, you should see a screen that
looks like Figure 1. In the command window,
type view signals and view wave
. These commands bring up the signalsand waves windows respectively.
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Figure 1: Modelsim Command Window
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7/31/2001 WLTFigure 2: Simulation Results Waveform
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Silicon Ensemble
We will now move on to using SiliconEnsemble.
1.Make sure that you are in thecadence/dp_se/run directory.
2.In the terminal window, type:
swsetup cadence-sesedsm &
This will start Silicon Ensemble.
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Importing the LEF File (Silicon
Ensemble)1.In Silicon Ensemble, click onFile ->
Import -> LEF.
2.In the Import LEF form, select the file../tech/jennings_ami06_pads_noqn.lef, then
click on OK.
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Importing a Verilog netlist into
Silicon Ensemble In the main window, click onFile ->
Import -> Verilog
Click on Browse to choose the verilogsource file.
Add the file synopsys/gate/libcells.v by
double-clicking on that file, and thenclicking on OK in the File form.
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Figure 3: The File Form
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Importing a Verilog netlist into
Silicon Ensemble Back in the Import Verilog form, fill in
the information according to Figure 4.
Then, click on OK. This will import the standard cell
information into Silicon Ensemble.
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Figure 4:
The Input
Verilog
Form
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Importing a Verilog netlist into
Silicon Ensemble Now, click onFile -> Import -> Verilogagain.
Click on Browse. In the File form, delete (by
pressing the DEL button) the libcells.v fromthe selected files list, and add
cadence/dp_se/netlist/topchip_nopads.v into
the selected files list.
Click on OK.
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Importing a Verilog netlist into
Silicon Ensemble In the Import Verilog form, type
topchip_nopads for the Verilog Top Module,and add jennings_ami06_pads_noqn to theCompiled Verilog Reference Libraries. The restof the information stays the same. (Refer Figure5, next slide).
Click on Yes when Silicon Ensemble asks if itis okay to overwrite the original content of thereference library we will not be destroyingdata, just adding to it.
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Figure 5:
The Input
Verilog
Form
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Floorplanning
In the main window, click onFlooplan ->Initialize Floorplan.
In the Initialize Floorplan window, click on the
Variables button. Another window, theEnvironment Variables form, will pop up.
In the Environment Variables form, change thevariablePLAN.LOWERLEFT.ORIGINto
TRUE. Click on OK in the Environmental Variablesform.
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Figure 6: The
Environment
Variables
Form
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Floorplanning
In the Init Floorplan form, set IO to CoreDistance to 40.00 microns for both Left/Rightand Top/Bottom.
Make sure the Flip every other row and Abut
Rows boxes are checked. Also, make sure all the other information isentered according to Figure 7 on the next slide.
If you press the Help button, you will get a
detailed explanation on what all the optionsmean.
Finally, hit the OKbutton.
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Figure 7: The Init Floorplan Form
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Figure 8: After Floorplan Initialization
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Floorplanning
We still need to add rows for the double-heightcells. In the main window, click onEdit -> Add-> Row
In the Add Row window, select dbl_core as theSite Type, and check the Flip and Abut EveryOther Row boxes.
Click on the Area button. Then, click and drag,in the main window, an area that approximately
covers all of the original row area. After you dothis the X-Y values should be filled inautomatically.
Click on the OKbutton.
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Figure 9: The Add Row Form
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Figure 10: After Adding Rows for Double-
Height Cells.
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Floorplanning
Finally, in the main window, click onFile
-> Save as
Save the design asfplan.
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Adding Supply Rings
In the main window, click onRoute -> Plan Power. In the Plan Power window, click on the Add Rings
button.
In the PP Add Rings window, change both the
horizontal and vertical Core Ring Width to 4.50. CoreRing Width refers to the width of the supply rings that
are between the I/O and Core sections.
Click on Help to get detailed explanations on all the
fields.
Click on OKin the PP Add Rings form, and click on
Close in the Plan Power form.
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Figure 11: After Adding Supply Rings.
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Adding Pins
To add top-level pins to the layout, clickonPlace -> Ios in the main window.
Choose random placing mode, and space
evenly (refer Figure 12, next slide). Thenclick on OK. This will place top-level
pins evenly around the perimeter of the
layout area.
Save your design as pins.
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Figure 12: The Place IO form
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Placing Cells (Qplace)
We are now ready to place cells onto our layout.Click onPlace -> Cells in the main window.
In the Place Cells window, uncheck all the
boxes, then click on OK. You may use timing or
power-driven placement in the future, but for
this tutorial we will use neither.
Qplace will take a few minutes to complete.
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Figure 13: After Cell Placement
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Viewing Layers (Silicon
Ensemble) To view nets, special
wires, pins, cell
boundaries etc. whileyou are working on
your design, make sure
all the appropriate Vs(visible) fields are
checked.
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Adding Filler Cells (Silicon
Ensemble)1. Click onPlace -> Filler Cells -> Add Cells.
2. In the SROUTE Add Filler Cells form, type in
FILL forModel, and fill forprefix.3. Make sure ONLY the North and Flip South
boxes are checked.
4. In the special pins section, add one entry forvdd
and one entry forgnd (refer to Figure 16 on the
next slide)
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Figure
16:
Add FillerCells
Form
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Adding Filler Cells (Silicon
Ensemble)5.Click on OK.
6.This will add filler cells to your design.
Filler cells provide n-well continuity foryour standard cells.
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7/31/2001 WLTFigure 17: After Adding Filler Cells
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Figure 18:
Sroute
FollowPins Form
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7/31/2001 WLTFigure 19: After SRoute Follow Pins
W t (Sili E bl )
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Wroute (Silicon Ensemble)
1. Click onRoute -> Wroute.
2. In the Wroute form, click on OK.
Wroute will run. This will take a few minutes tocomplete.
After this point, all the interconnect routing of thedesign has been done.
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Figure 20: After WRoute
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Viewing Different Layers in
Silicon Ensemble You wont be able to see the interconnect
metal layers in Figure 20 unless you enable
the layer to be viewable. Click on View -> Layers.
In the Layer Visibility form, click on All
Objects, then check all the layer checkboxes.
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Display Options
Silicon Ensemble allows you to customizethe view window to display/not display
certain parts of your design.
In the main window, click on View ->Display Options
Display Options
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Display Options Notice the top part of the Display Option form
allows you to select On, Here, Big, Small etc forthe Level. By choosing a level here and clickingon the checkboxes, the selection for that particularcheckbox will rotate between OFF and the levelyou chose.
For example, select Small for the level. Now,click once on the Cells checkbox in the Objectssection.
If the checkbox was originally set to On, it willswitch to Offafter the first time you click it. Clickon it again to set it to Small.
Click on Apply.
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Display Options
Your cell boundaries will now only bevisible when you are zooming into a smaller
portion of the design.
If you click on the Fitbutton in the main
window, you will not see the cell
boundaries any more.
Try zooming into a small area of the design.
The cell boundaries will be visible again.
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Display Options
The following explains the different levels:
- On: visible at any level.
- Here: visible at level that is currently
displayed in the main window.
- Big, medium, small: visible at big,
medium or small levels respectively.
- Off: not visible at any level.
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Checking Pin Names
You can easily check to see the names of the routed pins inthe standard cells using the Display Options form.
In the Names section of the Display Options form, set
Pins to On, orSmall.
Click on the Applybutton. The pin names will now bevisible.
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The Find Form
You can find cells, nets and pins etc. with theFind form. Click onEdit -> Find to access the
Find form.
On the Find form, set Type to Net.
Type msb_dp for the Name.
Set the background dimmer to 70, then click on
the Hilight button.
The display will be dimmed, while the msb_dpnet will be highlighted in the color selected in the
Find form.
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The Find Form
You can also give partialnames, e.g. msb* instead
ofmsb_dp. If you click
on the Show List
checkbox, you will see a
list of matching names.
Type_csb* for the net
name, click on Show
List, then click on Find.
You should see a list of
net names starting with
_csb.
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The Find Form
You can now click on each individual entryin the list, and highlight the particular net,
or select it.
The Find form, together with the DisplayOptions form, provide a convenient way of
debugging your overall routed design.
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Checking for Violations
Violations will appear as X marks on your
design. Be sure that there are no violations created
during the routing.
Silicon Ensemble will tell you the number of
violations created during Wroute (Refer to Figure
21, on the next slide). If there are any violations,
be sure to fix them before moving on. You shouldnot get any violations for this exercise.
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Figure 21: Total Number of Violations
Reported by Silicon Ensemble
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Export to DEF Format (Silicon
Ensemble)1. Click onFile -> Export -> DEF.
2. Type ../def_files/topchip_nopads_wrouted.def
for the DEF file name.3. Make sure the Allcheckbox is checked.
4. Click on OK.
This will create the DEF file
cadence/dp_se/def_files/topchip_nopads_wrouted.
def.
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Running SEDSM in Script Mode
When using SEDSM in interactive mode (like wejust did), SEDSM will echo back your commandsin the command-line window.
If you enter these commands into a text file, youcan run SEDSM inscript mode. To run SEDSM in
script mode, type the following in the
cadence/dp_se/run directory:sedsm b gd=ansi EXECUTE script.mac; &
wherescript.mac is the name of your script file.
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Running SEDSM in Script Mode
The cadence/dp_se/run directory has a script file
called topchip_nopads_se.mac which will
essentially perform all the procedures we did in
interactive mode, from importing the LEF file toexporting the topchip_nopads_wrouted.deffile.
To execute the script file, go the the
cadence/dp_se/run directory, and type:
sedsm b gd=ansi EXECUTEtopchip_nopads_se.mac; &
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Re-running SEDSM after a Crash
If Silicon Ensemble crashes while you are
running it, you need to delete all the .dtp
files in the cadence/dp_se/run directorybefore you run it again. The .dtp files are
the lock files for Silicon Ensemble
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Cadence ICFB
Cadence ICFB is the last CAD tool in this
design flow. In ICFB, our design can be
exported into a HSpice netlist, a Verilog
netlist, or GDSII / CIF formats, amongothers.
Cadence ICFB is potentially the most
powerful CAD tool among the tools in thisdesign flow, but it is also the most complex.
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Starting ICFB
If youve previously used Silicon Ensemble inyour currentxterm window, launch a newxtermwindow.
Change to the cadence/dfIIdirectory.
Type swsetup cadence-ncsu.
Type icfb & to launch ICFB.
You should see three windows pop up: the ICFB
Command Interpreter Window (CIW), theLibrary Manager window, and another windowstelling you about the changes for the latestversion of ICFB. Close the third window.
Importing DEF into ICFB
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Importing DEF into ICFB In the CIW, click onFile -> Import -> DEF.
Enter tutorial for Library Name,topchip_nopads for Cell Name, andautoRouted for View Name.
Enter../dp_se/def_files/topchip_nopads_wrouted.def for DEF File Name.
Make sure Silicon Ensemble is checked.
Refer to Figure 22 (next slide) for all other
options in the form. Click on OK. You will see some warning
messages (about not being able to findsite Coreand site Double core). Ignore these messages.
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7/31/2001 WLTFigure 23: topchip_nopads autoRouted view
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Importing DEF into ICFB
Open the autoRouted view of topchip_nopads.
In the autoRouted view, before you do anything,
click onDesign -> Save. This ensures that if
anything goes wrong, you can always come backto the autoRouted view.
Click on Tools -> Layout. This changes the tool
from abstract-editing mode to layout-editing
mode.
Importing DEF into ICFB
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p g Click onEdit -> Search
In the Search form, search forinst in current cellview,
with view name = abstract. Replace with view name ->layout. (Refer to Figure 24, next slide, click on addcriteria then choose view name criteria)
Click on Apply, then Replace All.
Close the search form, then click onDesign -> Saveas
Save the design in the same library and cell, but changethe view to layout.
When you close the editing window, you will be asked if
you want to save changes for the autoRouted view. Donot save any changes here or the autoRouted view will
be over-written.
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Viewing Layers in ICFB
Whenever in ICFBs layout editor, you can press
shift-fto increase the number of layers viewed, or
ctrl-fto decrease the number of layers viewed.
For example, if you press shift-fwhile viewingthe topchip_nopads layout, you will be able to see
the metal, poly, active etc. layers of the individual
standard cells. If you press ctrl-f, you will only be
able to see the boundaries of the individualstandard cells.
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Figure 25: topchip_nopads layout view
Extracting a Verilog Netlist
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Extracting a Verilog Netlist We need to extract a Verilog netlist out of
our placed-and-routed design to verifythat the place-and-route tools did their
jobs without errors.
This Verilog netlist will be simulatedusing Modelsim to verify for correct
functionality.
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Extracting a Verilog Netlist
Before starting this section, change to thedirectory/ccs/issl/micro/users/tan/tutorials/design_flow/cadence/dfII.
Then, type:
rm rf topchip_nopads.verilog
This will clear the Verilog netlister workdirectory.
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7/31/2001 WLTFigure 26: The Extractor Form
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Figure 27: Setup Environment Form
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Extracting a Verilog Netlist
You will see a warning message as shown below.Ignore this warning message, since we are notgoing to simulate our design using Cadence. Weare only going to use ICFB to extract a Verilog
netlist.
Extracting a Verilog Netlist
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Extracting a Verilog Netlist
The Verilog-XL Integration window will now pop up.
Click on Setup -> Netlist The Verilog Netlisting Options form will pop up. Click
on the More >>button. This will enable you to see allthe options for this form.
For the Netlist These Views field, enter: behavioralfunctional symbol verilog.
For the Stop Netlisting at Views field, enter:behavioral functional symbol.
Enter vdd and gnd forGlobal Power Nets and
Global Ground Nets, respectively. Make sure the netlist explicitly box is checked. Then,
Click on OK.
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Figure 28: Verilog Netlisting Options Form
Extracting a Verilog Netlist
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Extracting a Verilog Netlist Back in the Verilog-XL Integration window, click on
Simulation -> Start Interactive.
The first time you run the verilog netlist extraction, you will
get two errors regarding inherited nets for every instance you
have in your design (on the order of a few thousand errors for
our design). Ignore these errors - they are internal errors and
should be fixed in the latest version of ICFB. Click on
Simulation -> Start Interactive again; you will not get these
errors the second time.
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Extracting a Verilog Netlist
20. Ignore the warning shown below (click on
OK). We can ignore this warning because
we are not going to run Verilog simulationin ICFB.
Extracting a Verilog Netlist
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Extracting a Verilog Netlist
21. A text file called verilog.inpfiles, located in thenetlister work directory(cadence/icfb/topchip_nopads.verilog) iscreated. This file tells of the location of the
Verilog netlists generated.22. Using a text editor (pico, VI etc.), view the file
verilog.inpfiles.
23. The text file will tell you the location of the top-
level Verilog netlist it is going to be inihnl/cds?/netlist, where ? will be a number.
Extracting a Verilog Netlist
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Extracting a Verilog Netlist24. Copy the netlistfile from
cadence/dfII/topchip_nopads.verilog/ihnl/cds?,to cadence/dfII/gate.
In the directory/cadence/dfII/gate, rename thenetlistfile to topchip_nopads_se.v.
Use a text editor to view your verilog netlist. Ifthe top-level module oftopchip_nopads_se.v isnot topchip_nopads, edit it to that name.
27. The next section of this tutorial will demonstratehow to simulate this Verilog netlist usingModelsim. However, before we go into that,lets discuss some other issues regarding ICFB.
Extracting a Hspice Netlist
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The procedure for extracting a Hspice netlist is
similar to that of extracting a Verilog netlist, up
to the Extractor form. There is only one
difference for the Extractor form:
In the Extractor form, select Flat forExtract
Method instead ofMacro Cell.
Extracting a Hspice Netlist
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Extracting a Hspice NetlistAfter running the Extractor form, follow the
instructions below to generate a HSPICE netlist: Click on Tools -> Simulation -> Other. You
should see a new menu item - Simulationappear on your menu bar.
2. Click on Simulation -> Initialize.
3. Enter topchip_nopads.hspice for thesimulation run directory.
4. Click on OK.
5. Another Initialize Environment form shouldpop-up. This one has the full set of options tochoose from.
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Extracting a Hspice Netlist
In the Initialize Environment form,
choose hspice for the simulator name.
Enter Tutorial forLibrary Name,topchip_nopads forCell Name, and
extracted forView Name.
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Figure 29: Initialize Environment Form
Extracting a Hspice Netlist
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Extracting a Hspice Netlist Go back to the Layout editing window, and click
on Simulation -> Options Make sure the Use Hierarchical Netlister and
Re-netlist Entire Designboxes are checked,
and the others are left unchecked.
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Extracting a Hspice Netlist
Go back to the Layout editing window, and clickon Simulation -> Netlist/Simulate
Make sure that the netlist box is checked, and
the simulate box is not. Also, check the Run in
background box.
The remaining information should be already
filled in correctly for you. Make sure they match
up to that shown in Figure 30. (next slide)
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Figure 30: Netlist and Simulate Form
Extracting a Hspice Netlist
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Extracting a Hspice Netlist
Click on OK. Wait for a minute or so as ICFBworks in the background to generate the Verilognetlist.
A message telling you that the netlister has
succeeded should pop up after a minute or so. The HSPICE netlist will be located in the
directory that you specified as the run directory(for our case,
cadence/dfII/topchip_nopads.hspice), with thefilename netlist.
Verilog or Hspice?
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Verilog or Hspice? Forourcase, Verilog is a more practical choice.
Verilog is a switch-level language, which means it
does not model any parasitics of the design. This
makes simulation much faster than Hspice, which
models the parasitics of the system. Since we started out with a VHDL file, we can
assume that most of our designs will be relatively
complex (e.g. having more than a few thousand
transistors). Hspice simulation for designs of thisscale is too time consuming.
Verilog or Hspice?
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For example, if we were to simulate our
topchip_nopads design using Hspice for 150 us, itwould take more than 24 hours to simulate.Verilog simulation using Modelsim takes less than1 second.
Conclusion: Hspice is great for detailedsimulations (especially for analog systems), butfor complex, purely digital systems, Verilogsimulation is much more practical.
Other simulators such as IRSim fall somewhere inbetween Verilog and Hspice simulators.
DRC Verification (ICFB)
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DRC Verification (ICFB)
DRC (Design Rule Check) verificationchecks for design rule violations. The
NCSU Cadence Design Kit comes with a
decent (but by no means perfect) DRC
checker.
The NCSU kit DRC checker will flag
certain metal constructs that should not be
flagged as errors. Refer to the next slide for
a more detailed explanation.
DRC V ifi ti (ICFB)
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DRC Verification (ICFB)
The NCSU kit DRC checker will flag these as errors
if the spacing is less than the minimum spacing forthat metal layer, even though it should not matter
because they all belong to the same net.
Metal1
shapes
DRC V ifi ti (ICFB)
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DRC Verification (ICFB)
Open the topchip_nopads layoutusing thelayout editor.
Click on Verify -> DRC
CheckFlat for checking method, and Fullfor checking limit.
ClickOK.
DRC will run (this will take a fewminutes), and subsequently return arounda thousand false metal spacing errors.
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Figure 31: DRC Form
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Checking for Short Circuits
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between VDD and GND
A simple way to perform this check is to open theextractedview of the layout. In the LibraryManager window, open with extracted view oftopchip_nopads.
Now, click on the VDD (or GND) ring. If youclicked on the VDD ring, you should see the VDDring, and the VDD rails highlighted. The samegoes for the GND ring.
If you see both rings highlighted when you clickon either ring, then a there is a short from VDD toGND in your layout that must be fixed.
Exporting to CIF
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Exporting to CIF
Most industrial foundries use a standarddesign transfer file format to send orreceive design files. CIF is one suchformat.
To export to CIF, click onFile -> Export-> CIF
Enter . for the run directory, tutorial
for the library name, topchip_nopadsfor the cell name, and layout for theview name.
Exporting to CIF
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p g
Enter cif_files/topchip_nopads.cif forthe output file.
Check the CIF DBbox.
Click on OK. This will generate a CIF file
called topchip_nopads.cifin thecadence/dfII/cif_files directory.
You will get some warnings (view the
PIPO.LOG file) because not all layers inICFB are translated into the CIF file. Thisis OK.
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Figure 32: CIF Out Form
Modelsim
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Modelsim
The final step in our design flow is tosimulate our ICFB-generated Verilog netlist
using Modelsim.
If the place-and-route procedures weresuccessful, we should get the same results
for this simulation as the simulation we ran
with our Synopsys-generated Verilog
netlist.
Modelsim
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Modelsim
There should be the following Verilogfiles in the cadence/dfII/gate directory:
topchip_nopads_se.v, which we just
created,
tb_topchip_nopads_se.v, the testbench file
for the file above.
Modelsim
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Modelsim
Change to the qhsim directory. Type swsetup modelsim.
3. Type qvlcom
../cadence/dfII/gate/libcells_icfb.v
4. Type qvlcom
../cadence/dfII/gate/topchip_nopads_se.v
5. Type qvlcom
../cadence/dfII/gate/tb_topchip_nopads_se.v
Modelsim
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Type qhsim tb_topchip_nopads&. This will
invoke Qhsim to simulate the testbench. There is a .do file in the qhsim directory that
displays the signals and wave windows, adds allthe top level signals into the wave window, and
runs the simulation for 150 us. Activate thescript by typing do tb_topchip_nopads.do inthe command window. If you open up that .dofile you will find that it contains the same
commands that you would type in the commandwindow to achieve the same results.
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Modelsim
Verify that the results for this simulation
match that of the first Verilog simulation
in this tutorial, by looking at the wavewindow.
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