03 Design Flow

8/12/2019 03 Design Flow

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CSE 467 3Verilog Digital System Design

Digital System DesignDigital System Design

Automation with VerilogAutomation with Verilog!! As the size and complexity of digital systems increase, more computerAs the size and complexity of digital systems increase, more computer

aided design (CAD) tools are introduced into the hardware designaided design (CAD) tools are introduced into the hardware designprocess.process.

!! Early simulation and primitive hardware generation tools have givenEarly simulation and primitive hardware generation tools have givenway to sophisticated design entry, verification, high-level synthesis,way to sophisticated design entry, verification, high-level synthesis,formal verification, and automatic hardware generation and deviceformal verification, and automatic hardware generation and device

programming tools.programming tools.

!! Growth of design automation tools is largely due to hardwareGrowth of design automation tools is largely due to hardwaredescription languages (description languages (HDLsHDLs) and design methodologies that are) and design methodologies that arebased on these languages.based on these languages.

!! Based onBased on HDLsHDLs, new digital system CAD tools have been developed, new digital system CAD tools have been developedand are now widely used by hardware designers.and are now widely used by hardware designers.

!! One of the most widely usedOne of the most widely used HDLsHDLsis the Verilog HDL.is the Verilog HDL.

!! Because of its wide acceptance in digital design industry, Verilog hasBecause of its wide acceptance in digital design industry, Verilog hasbecome a must-know for design engineers and students in computer-become a must-know for design engineers and students in computer-hardware-related fields.hardware-related fields.


Digital Design FlowDigital Design Flow

!! FPGA Design FlowFPGA Design Flow

Compilation and Synthesis

Analysis Synthesis Routingandplacement

Y = a & d & ww = a & b | c

Post-synthesis Simulation

Timing Analysis

1.6ns2 ns

C++ Classes,Language Representation

Behavioral Simulation Assertion Verification Formal Verification

Violation Report;Time of Violation;

Monitor Coverage

Pass / Fail ReportProperty Coverage

Counter Examples

Design Entry in Verilog

always (posedgeclk )begin . . . end

if () bus = w;

else. . .

Comp1 U1(. . .);Comp2U2(. . .);

. . .CompnUn(. . .);

moduledesign (. . .);

assign . . . always . . .

comp i (. . .)

endmodule

Testbench in Verilog

moduletestbench ();

generatedata ;

process data;endmodule

D ev ic e P ro gr am mi ng A SI C N et li st Custom IC Layout

EDIFor other netlists1010...


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Behavioral S imulat ion Assert ion Verif icat ion Formal Verif icat ion

Violation Report;Time of Violation;

Monitor Coverage

Pass / Fail ReportProperty Coverage

Counter Examples

Design Entry in Verilog

always (posedge clk )begin . . . end

if () bus = w;

else . . .

Comp1 U1 (. . .) ;Comp2 U2 (. . .) ;

. . .CompnUn (. . .);

module design (. . .) ;


compi (. . .)

endmodule


module testbench ();

generate data ;

process data ;endmodule

Design EntryDesign Entry

PhasePhase



!! Digital Design Flow begins with specification of the design at variousDigital Design Flow begins with specification of the design at variouslevels of abstraction.levels of abstraction.

!! Design entry phase:Design entry phase:Specification of design as a mixture of behavioralSpecification of design as a mixture of behavioral

VerilogVerilog code, instantiation ofcode, instantiation ofVerilogVerilog modules, and bus and wiremodules, and bus and wireassignmentsassignments


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Analysis Synthesis Routing and placement

Y = a & d & ww = a & b | c

Timing Analysis

1.6 ns2 ns


Behavioral Simulat ion Assertion Verif icat ion Formal Ver if icat ion

Violation Report;

Time of Violation;Monitor Coverage

Pass / Fail Report

Property CoverageCounter Examples



(Continued)(Continued)

PresynthesisPresynthesis

VerificationVerification



!! Presynthesis verification:Presynthesis verification:Generating testbenches for verification of theGenerating testbenches for verification of thedesign and later for verifying the synthesis outputdesign and later for verifying the synthesis output


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Analysis Synthesis Routing and placement

Y = a & d & ww = a & b | c

Timing Analysis

1.6 ns2 ns


Behavioral Simulat ion Assertion Verif icat ion Formal Ver if icat ion

Violation Report;

Time of Violation;Monitor Coverage

Pass / Fail Report

Property CoverageCounter Examples



(Continued)(Continued)

Synthesis ProcessSynthesis Process



!! Synthesis process:Synthesis process:Translating the design into actual hardware of aTranslating the design into actual hardware of atarget device (FPGA, ASIC or custom IC)target device (FPGA, ASIC or custom IC)


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!! FPGA Design Flow (Continued)FPGA Design Flow (Continued)


Timing Analysis

1.6 ns2 ns


module testbench (); generate data ;


Device Programming ASIC Netlist Custom IC Layout


PostsynthesisPostsynthesis

VerificationVerification



!! PostsynthesisPostsynthesissimulation:simulation:Testing the behavioral model of the designTesting the behavioral model of the designand its hardware model by usingand its hardware model by usingpresynthesispresynthesistest datatest data


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!! FPGA Design Flow (Continued)FPGA Design Flow (Continued)


Timing Analysis

1.6 ns2 ns


module testbench (); generate data ;


Device Programming ASIC Netlist Custom IC Layout




!! Digital Design Flow ends with generating netlist for an applicationDigital Design Flow ends with generating netlist for an applicationspecific integrated circuits (ASIC), layout for a custom IC, or a programspecific integrated circuits (ASIC), layout for a custom IC, or a programfor a programmable logic devices (PLD)for a programmable logic devices (PLD)


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Digital DesignDigital DesignFlowFlow

HardwareHardware

GenerationGeneration

Design EntryDesign Entry Testbench in VerilogTestbench in Verilog

Design ValidationDesign ValidationCompilationCompilation

and Synthesisand Synthesis


SimulationSimulation

TimingTiming

AnalysisAnalysis



Digital DesignDigital Design

FlowFlow

HardwareHardware







TimingTiming

AnalysisAnalysis




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!! The first step in the design of a digital systemThe first step in the design of a digital system

!! Describing the design in Verilog in a top-down hierarchical fashionDescribing the design in Verilog in a top-down hierarchical fashion

!! Register Transfer Level (RTL):Register Transfer Level (RTL):High-level Verilog designs usuallyHigh-level Verilog designs usuallydescribed at this leveldescribed at this level

!! Verilog constructs used in RT level design:Verilog constructs used in RT level design:

!! procedural statementsrocedural statementsfor high-level behavioral descriptionfor high-level behavioral description!! continuous assignmentsontinuous assignmentsfor representing logic blocks, bus assignments,for representing logic blocks, bus assignments,

and bus and input/output interconnect specificationsand bus and input/output interconnect specifications

!! instantiation statementsnstantiation statementsfor using lower-level components in an upper-for using lower-level components in an upper-level designlevel design



FlowFlow

HardwareHardware







TimingTiming

AnalysisAnalysis

Testbench in VerilogTestbench in Verilog



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!! Simulation and Test of a designed system functionality beforeSimulation and Test of a designed system functionality beforeHardware generationHardware generation

!! Detection of design errors and incompatibility of components usedDetection of design errors and incompatibility of components used

!! in the designin the design

!! By generation of a test data and observation of simulation resultsBy generation of a test data and observation of simulation results

!! Testbench:Testbench:A Verilog moduleA Verilog module

!! Use of high-level constructs of Verilog for:Use of high-level constructs of Verilog for:

!! Data GenerationData Generation

!! Response MonitoringResponse Monitoring

!! Handshaking with the designHandshaking with the design

!! Inside the Testbench: Instantiation of the design moduleInside the Testbench: Instantiation of the design module

!!

Forms a simulation model together with the design, used by aForms a simulation model together with the design, used by aVerilog simulation engineVerilog simulation engine



FlowFlow

HardwareHardware







TimingTiming

AnalysisAnalysis

Design ValidationDesign Validation



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!! An important task in any digital system designAn important task in any digital system design

!! The process to check the design for any design flawsThe process to check the design for any design flaws

!! A design flaw due to:A design flaw due to:

!! Ambiguous Problem SpecificationsAmbiguous Problem Specifications

!! Designer ErrorsDesigner Errors

!! Incorrect Use of Parts in the DesignIncorrect Use of Parts in the Design

!! Can be done by:Can be done by:

!! SimulationSimulation

!! Assertion VerificationAssertion Verification

!!

Formal VerificationFormal Verification



DesignDesign

ValidationValidation

SimulationSimulation AssertionAssertionVerificationVerification

FormalFormalVerificationVerification


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DesignDesign


SimulationSimulationAssertionAssertion

VerificationVerificationFormalFormal

VerificationVerificationSimulationSimulation



!! Simulation for design validation, done before a design is synthesizedSimulation for design validation, done before a design is synthesized

!! Also Referred to as RT level, or Pre-synthesis SimulationAlso Referred to as RT level, or Pre-synthesis Simulation

!! Simulation at RTL level is accurate to the clock levelSimulation at RTL level is accurate to the clock level

!! The advantage: its speed compared with simulations at the gate orThe advantage: its speed compared with simulations at the gate or

transistor levelstransistor levels

!! The Required Test data: generated graphically using waveform editors,The Required Test data: generated graphically using waveform editors,

or through a testbenchor through a testbench

!! Outputs of simulators:Outputs of simulators:

!! Waveforms (for visual inspection)Waveforms (for visual inspection)

!! Text for large designs for machine processingText for large designs for machine processing


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!! Using a Testbench or a Waveform Editor for SimulationUsing a Testbench or a Waveform Editor for Simulation

TwoTwo

alternativesalternatives

for definingfor defining

test inputtest input

data for adata for a

simulationsimulation

engineengine

Testbench

Text,

VCD...

Waveform

Other forms

Simulation Model

HierachicalDesign

Description

Simulator

Waveform

Simulator

...

Simulation Model

Hierachical

Design

Description

Text,

VCD...

Waveform

Other forms

...

Stimuli

InputsInputsOutputsOutputs



!! Verilog Simulation with a TestbenchVerilog Simulation with a Testbench

TestbenchTestbench

for thefor the

CounterCounterCircuitCircuit

Verilog CodeVerilog Code

of a Counterof a Counter

CircuitCircuit

`timescale1 ns / 100 ps

module Chap1CounterTester ();regClk=0, Reset=0;

wire [3:0] Count;initial begin

Reset = 0; #5 Reset = 1; #115 Reset = 0;

# 760 $stop;end

always #26.5 Clk = ~ Cl k;Chap1Counter U1 (Clk, Reset, Count);

endmodule

module Chap1Counter (Clk, Reset, Count);inputClk, Reset;output [3:0] Count;reg [3:0] Count;

always @(posedge Clk) beginif(Reset) Count = 0;else Count = Count + 1;

endendmodule

SimulatorTestbench

Design to Simulate

The simulationThe simulation

results in formresults in form

of a waveformof a waveform


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SimulationSimulationThe testbench instantiatesThe testbench instantiatesthe design under test, and asthe design under test, and as

part of the code of thepart of the code of thetestbench it applies test datatestbench it applies test data

to the instantiated circuit.to the instantiated circuit.

!! Verilog Simulation with a Testbench (Continued)Verilog Simulation with a Testbench (Continued)

`timescale 1 ns / 100 ps

module Chap1CounterTester ();regClk=0, Reset=0;

wire [3:0] Count;initial begin

Reset = 0; #5 Reset = 1; #115 Reset = 0;

# 760 $stop;end

always #26.5 Clk = ~ Clk;Chap1Counter U1 (Clk, Reset, Count);

endmodule

module Chap1Counter (Clk, Reset, Count);inputClk, Reset;

output [3:0] Count;reg [3:0] Count;

always @(posedge Clk) beginif(Reset) Count = 0;else Count = Count + 1;

endendmodule


Simulator


Validates theValidates the

functionality of thefunctionality of the

counter circuit beingcounter circuit being

tested,tested, Regardless ofRegardless of

clock frequencyclock frequency

!! Verilog Simulation with a Testbench (Continued)Verilog Simulation with a Testbench (Continued)


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!! Obviously, an actual hardware component behaves differently.Obviously, an actual hardware component behaves differently.

!! Based on the timing and delays of the parts used, there will be aBased on the timing and delays of the parts used, there will be anonzero delay between the active edge of the clock and the counternonzero delay between the active edge of the clock and the counteroutput.output.

!! Furthermore, if the clock frequency applied to an actual part is too fastFurthermore, if the clock frequency applied to an actual part is too fastfor propagation of values within the gates and transistors of a design,for propagation of values within the gates and transistors of a design,the output of the design becomes unpredictable.the output of the design becomes unpredictable.

!! The simulation shown here is not provided with the details of theThe simulation shown here is not provided with the details of thetiming of the hardware being simulated.timing of the hardware being simulated.

!! Therefore, potential timing problems of the hardware that are due toTherefore, potential timing problems of the hardware that are due togate delays cannot be detected.gate delays cannot be detected.

!! This is typical of aThis is typical of apresynthesispresynthesisor high-level behavioral simulation.or high-level behavioral simulation.


Assertion VerificationAssertion Verification

DesignDesign




AssertionAssertionVerificationVerification


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Assertion VerificationAssertion Verification

!! AAssertionssertionMonitorsMonitors::UsedUsedto continuously check for design propertiesto continuously check for design properties

during simulationduring simulation

!! Instead of having to inspect simulation results manually or byInstead of having to inspect simulation results manually or by

developing sophisticateddeveloping sophisticated testbenchestestbenches

!! DDesignesign Properties:Properties: CCertain conditions have to be metertain conditions have to be metfor thefor thedesigndesign toto

function correctlyfunction correctly

!! Assertion Monitors developed tAssertion Monitors developed to assert that theo assert that theDesignDesignPProperties areroperties are

notnotviolatedviolated

!! Firing of an assertion verification: aFiring of an assertion verification: alertslerts the malthe malfunctioningfunctioning of designof design

according toaccording tothe designerthe designers expectations expectation

!! Open verification library (OVL):Open verification library (OVL):provides a set of assertion monitors forprovides a set of assertion monitors for

monitoring common design propertiesmonitoring common design properties



DesignDesign






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!! Formal verification:Formal verification:The process of checking a design against certainThe process of checking a design against certain

propertiesproperties

!! Examining the design to make sure that the described properties by theExamining the design to make sure that the described properties by the

designer to reflect correct behavior of the design hold under alldesigner to reflect correct behavior of the design hold under all

conditionsconditions

!! PPropertyropertyssCCounterounterEExamplesxamples::InInputputconditionsconditionsmakingmaking aapropertypropertytoto

failfail

!! Property coverage indicates how muchProperty coverage indicates how muchof the complete design isof the complete design is

exercised by theexercised by thepropertyproperty



FlowFlow

HardwareHardware







TimingTiming

AnalysisAnalysis

Compilation and SynthesisCompilation and Synthesis

CompilationCompilation

And SynthesisAnd Synthesis


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!! Synthesis:Synthesis:The process of automatic hardware generation from a designThe process of automatic hardware generation from a design

description that has an unambiguous hardware correspondence.description that has an unambiguous hardware correspondence.

!! A Verilog description for synthesis:A Verilog description for synthesis:

!! Cannot include signal and gate levelCannot include signal and gate leveltiming specifications, filetiming specifications, file

handling, and other language constructs thathandling, and other language constructs thatdo not translate todo not translate to

sequential or combinational logic equationssequential or combinational logic equations

!! Must follow certain styles of coding for combinational andMust follow certain styles of coding for combinational and

sequential circuitssequential circuits

!! Compilation process has three phases:Compilation process has three phases:

!! Analysis PhaseAnalysis Phase

!! Synthesis PhaseSynthesis Phase

!! Routing and Placement PhaseRouting and Placement Phase



!! Compilation and Synthesis ProcessCompilation and Synthesis Process

Design Specification

Comp1 U1 (. . .);Comp2 U2 (. . .);

. . .Compn Un (. . .);

Analysis

GenericHardware

Generation

LogicOptimization

Binding

Routing

andPlacement

Timing

Analysis

Target HardwareSpecification

Pd S u

Intermediate Format

Synthesis

T = ; T = ...

Operating

Condition

ChipManufacturing

orDevice

Programming

always (posedge clk )

begin . . . end

if () bus = w;

else . . .

module design ( . . .);


comp i(. . .)endmodule

Input: HardwareInput: Hardware

descriptiondescriptionconsisting ofconsisting of

various levels ofvarious levels of

VerilogVerilog

Output:Output:

A detailedA detailedhardware forhardware for

programmingprogramming

an FPGA oran FPGA or

manufacturingmanufacturing

ananASICASIC

The compilationThe compilationprocess and aprocess and a

graphicalgraphical

representation forrepresentation for

each of theeach of the

compilation phasecompilation phase

outputsoutputs


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!! Compilation and Synthesis Process (Continued)Compilation and Synthesis Process (Continued)

Design Specification

Comp1 U1 (. . .) ;Comp2 U2 (. . .) ;

. . .CompnUn (. . .) ;

Analysis

Intermediate Format

always (posedge clk )

begin . . . end

if () bus = w;

else . . .

module design (. . .) ;


compi (. . .)endmodule

Analysis Phase: TranslatesAnalysis Phase: Translates

various parts of the design tovarious parts of the design to

an intermediatean intermediateformat.format.


GenericHardware

Generation

Logic

OptimizationBinding

Target Hardware

Specification

Synthesis



Synthesis Phase: Links allSynthesis Phase: Links allparts together and generatesparts together and generates

the correspondingthe correspondinglogic.logic.

Has three different phases.Has three different phases.


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Routing and Placement Phase:Routing and Placement Phase:Places and routes componentsPlaces and routes components

of the target hardware,of the target hardware,andandgenerates timing details.generates timing details.

Routing

andPlacement

TimingAnalysis

Pd SuT = ; T = ...

OperatingCondition

Chip

Manufacturing

orDevice

Programming


Compilation and SynthesisCompilation and SynthesisCompilationCompilation


Routing andRouting and

PlacementPlacement

AnalysisAnalysisGeneric HardwareGeneric Hardware


LogicLogic

OptimizationOptimization

BindingBinding


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AnalysisAnalysis

CompilationCompilationand Synthesisand Synthesis


PlacementPlacement



LogicLogic

OptimizationOptimizationBindingBinding

AnalysisAnalysis


AnalysisAnalysis

!! Before the complete design is turned into hardwareBefore the complete design is turned into hardware

!! Analyzing the design and generating a uniform format for allAnalyzing the design and generating a uniform format for allparts ofparts ofitit

!! Also checks the syntax and semantics of the input Verilog codeAlso checks the syntax and semantics of the input Verilog code


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Generic Hardware GenerationGeneric Hardware Generation



PlacementPlacement



LogicLogic


Generic HardwareGeneric Hardware



Generic Hardware GenerationGeneric Hardware Generation

!! Generic Hardware Generation:Generic Hardware Generation:Turning the design into a genericTurning the design into a generic

hardware format such as a set of Boolean expressions or a netlist ofhardware format such as a set of Boolean expressions or a netlist of

basic gatesbasic gates


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Logic OptimizationLogic Optimization



PlacementPlacement



LogicLogic


LogicLogic

OptimizationOptimization


Logic OptimizationLogic Optimization

!! Logic Optimization:Logic Optimization:

!! Reducing expressions with constant inputReducing expressions with constant input

!! Removing redundant logic expressionsRemoving redundant logic expressions

!! Two-level minimizationTwo-level minimization

!! Multilevel minimization that include logic sharingMultilevel minimization that include logic sharing

!! Output:Output:

!! Boolean expressionsBoolean expressions

!! Tabular logic representationsTabular logic representations

!! Primitive gate netlistsPrimitive gate netlists


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BindingBinding



PlacementPlacement



LogicLogic

OptimizationOptimizationBindingBindingBindingBinding


BindingBinding

!! Binding:Binding:

!! Decide exactly what logic elementsDecide exactly what logic elementsand cells are needed for theand cells are needed for the

realization of the circuit using information from target hardwarerealization of the circuit using information from target hardware

!! OOutput is specific to theutput is specific to theFPGA, ASIC, or custom IC being usedFPGA, ASIC, or custom IC being used


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Routing and PlacementRouting and Placement



PlacementPlacement



LogicLogic



PlacementPlacement



!! DDecides on the placement of cells of the targetecides on the placement of cells of the target hardwarehardware

!! DeterminesDetermineswiring ofwiring of inputs and outputs of the cells through wiringinputs and outputs of the cells through wiring

channels and switching areas of the targetchannels and switching areas of the target hardwarehardware

!! The output is specific to the hardware being used and can be used forThe output is specific to the hardware being used and can be used for

programming an FPGA or manufacturing an ASIC.programming an FPGA or manufacturing an ASIC.


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!! An Example Synthesis RunAn Example Synthesis Run

moduleChap1Counter (Clk, Reset, Count);

inputClk, Reset;

output [3:0] Count;reg [3:0] Count;

always @(posedge Clk) begin

if(Reset) Count = 0;

else Count = Count + 1;

end

endmodule

Synthesis Tool

Target hardware specification

List of primitive components

- Flip-flops

- Logic elements

Timing specifications

- Pin-to-pin timing

Design to Synthesize

An example ofAn example of

a synthesis run:a synthesis run:The counterThe counter

circuit is beingcircuit is being

synthesizedsynthesized



!! An Example Synthesis Run (Continued)An Example Synthesis Run (Continued)

moduleChap1Counter (Clk, Reset, Count);

inputC lk, Reset;

output [3:0] Count;

reg [3:0] Count;

always @(posedge Clk) begin

if(Reset) Count = 0;

else Count = Count + 1;

end

endmodule

Synthesis Tool

Target hardware specification

List of primitive components- Flip-flops

- Logic elements Timing specifications

- Pin-to-pin timing

Design to Synthesize

VerilogVerilog DescriptionDescription

of the Designof the Design

SpecificationSpecification

of the Targetof the Target

HardwareHardware


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Synthesis Tool


!! An Example Synthesis Run (Continued)An Example Synthesis Run (Continued)

The output ofThe output of

synthesis toolsynthesis tool

A list of gates and flip-A list of gates and flip-

flops available in theflops available in thetarget hardware andtarget hardware and

their interconnectionstheir interconnections



FlowFlow

HardwareHardware







TimingTiming

AnalysisAnalysisPostsynthesisPostsynthesisSimulationSimulation

PostsynthesisPostsynthesisSimulationSimulation


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Timing AnalysisTiming Analysis

!! AApart of the compilation process, or in some tools after the compilationpart of the compilation process, or in some tools after the compilation

processprocess

!! Timing Analysis Phase generates:Timing Analysis Phase generates:

!! WorstWorst-case delays-case delays

!! ClockingClockingspeedspeed

!! DelaysDelaysfrom one gate to anotherfrom one gate to another

!! RequiredRequiredsetup and holdsetup and hold timestimes

!! Results of timing analysis appear inResults of timing analysis appear inTablesTablesand/orand/or GraphsGraphs

!! The results is used by designersThe results is used by designers to decide on speed of their circuits.to decide on speed of their circuits.



FlowFlow

HardwareHardware







TimingTiming

AnalysisAnalysis

Hardware GenerationHardware Generation

HardwareHardware



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Hardware GenerationHardware Generation

!! LastLaststage in an automated Verilog-based designstage in an automated Verilog-based design

!! Generates aGenerates a netlistnetlist for ASIC manufacturing, a program for programmingfor ASIC manufacturing, a program for programming

FPGAsFPGAs, or layout of custom IC cells, or layout of custom IC cells


Verilog HDLVerilog HDL

VerilogVerilog

HDLHDL

VerilogVerilogEvolutionEvolution

VerilogVerilogAttributesAttributes

The VerilogThe VerilogLanguageLanguage


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Verilog HDLVerilog HDL

!! A language that can be understood by:A language that can be understood by:

!! System DesignersSystem Designers

!! RT Level Designers,RT Level Designers,

!! Test EngineersTest Engineers

!! SimulatorsSimulators

!! Synthesis ToolsSynthesis Tools

!! MachinesMachines

!! Has become an IEEE standardHas become an IEEE standard


Verilog EvolutionVerilog Evolution

VerilogVerilog

HDLHDL






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!! Designed in earlyDesigned in early 19841984byby Gateway Design AutomationGateway Design Automation

!! Originally used as a simulation and verification toolOriginally used as a simulation and verification tool

!! After the initial acceptance of this language by electronic industry, aAfter the initial acceptance of this language by electronic industry, afault simulator, a timing analyzer, and later in 1987, a synthesis tool wasfault simulator, a timing analyzer, and later in 1987, a synthesis tool wasdeveloped based on this language.developed based on this language.

!! Since acquiring Gateway Design Automation and its Verilog-basedSince acquiring Gateway Design Automation and its Verilog-basedtools by Cadence Design System,tools by Cadence Design System, CadenceCadencehas been a strong forcehas been a strong forcebehind popularizing the Verilog hardware description language.behind popularizing the Verilog hardware description language.

!! In 1987 VHDL became an IEEE standard hardware descriptionIn 1987 VHDL became an IEEE standard hardware descriptionlanguage.language.

!! VHDL was adapted by the U.S. government for related projects andVHDL was adapted by the U.S. government for related projects andcontracts.contracts.

!! In an effort for popularizing Verilog, in 1990,In an effort for popularizing Verilog, in 1990, OVI (Open VerilogOVI (Open VerilogInternational)International)was formed and Verilog was placed in public domain.was formed and Verilog was placed in public domain.

!! In 1993, efforts for standardization of this language started. VerilogIn 1993, efforts for standardization of this language started. Verilogbecame the IEEE standard,became the IEEE standard, IEEE Std. 1364-1995IEEE Std. 1364-1995, in 1995., in 1995.



!! Verilog-2001:Verilog-2001:A new version of Verilog approved by IEEE in 2001A new version of Verilog approved by IEEE in 2001

!! Additional Features of Verilog-2001:Additional Features of Verilog-2001:

!! New features for external file access for read and writeNew features for external file access for read and write

!! Library managementLibrary management

!! Constructs for design ConfigurationConstructs for design Configuration

!! Higher abstraction level constructsHigher abstraction level constructs

!! Constructs for specification of iterative structuresConstructs for specification of iterative structures


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Verilog AttributesVerilog Attributes

VerilogVerilog

HDLHDL

VerilogVerilog

EvolutionEvolution

VerilogVerilog

AttributesAttributes

The VerilogThe Verilog

LanguageLanguage

VerilogVerilog

AttributesAttributes



!! Verilog is a hardware description language for describing hardwareVerilog is a hardware description language for describing hardware

from transistor level to behavioral.from transistor level to behavioral.

!! Supports timing constructs for switch level timing simulation and at theSupports timing constructs for switch level timing simulation and at the

same time, has features for describing hardware at the abstractsame time, has features for describing hardware at the abstract

algorithmic level.algorithmic level.

!! A Verilog description may consist of a mix of modules at variousA Verilog description may consist of a mix of modules at various

abstraction levels with different degrees of detail.abstraction levels with different degrees of detail.


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PLIPLI

Switch LevelSwitch Level Gate LevelGate Level

Pin-To-Pin DelayPin-To-Pin DelayBussingBussing

SpecificationsSpecifications

BehavioralBehavioral

LevelLevelSystem UtilitiesSystem Utilities




PLIPLI





LevelLevel System UtilitiesSystem Utilities

Switch LevelSwitch Level



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!! Features of the language for switch level modeling and simulation:Features of the language for switch level modeling and simulation:

!! Primitive unidirectional and bidirectional switches with parametersPrimitive unidirectional and bidirectional switches with parameters

for delay and charge storagefor delay and charge storage

!! Circuit delays may be modeled as propagation delay, rise and fall delay,Circuit delays may be modeled as propagation delay, rise and fall delay,

and line delays.and line delays.

!! The charge storage feature for describing dynamic complimentaryThe charge storage feature for describing dynamic complimentary

metal oxidemetal oxide semicondutorsemicondutor(CMOS) and metal oxide semiconductor(CMOS) and metal oxide semiconductor

(MOS) circuits.(MOS) circuits.



PLIPLI






Gate LevelGate Level



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!! Gate level primitives with predefined parameters provide a convenientGate level primitives with predefined parameters provide a convenient

platform for:platform for:

!! netlist representationnetlist representation

!! gate level simulation.gate level simulation.

!! For more detailed and special purpose gate simulations:For more detailed and special purpose gate simulations:

!! Gate components defined at the behavioral level.Gate components defined at the behavioral level.

!! Verilog provides utilities for defining primitives with specialVerilog provides utilities for defining primitives with special

functionalities:functionalities:

!! A simple 4-value logic system used for signal valuesA simple 4-value logic system used for signal values

!!

16 levels of strength in addition to the four values for more accurate16 levels of strength in addition to the four values for more accuratelogic modelinglogic modeling



PLIPLI






Pin-To-Pin DelayPin-To-Pin Delay



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!! Verilog provides a utility for timing specification of components at theVerilog provides a utility for timing specification of components at the

input/output level:input/output level:

!! Can be used for back annotation of timing information in originalCan be used for back annotation of timing information in original

predesignedpredesigneddescriptionsdescriptions

!! Enables modelers toEnables modelers to finetunefinetunetiming behavior of their models basedtiming behavior of their models based

on physical implementationson physical implementations



PLIPLI






Bussing SpecificationsBussing Specifications

BussingBussing



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Bussing SpecificationsBussing Specifications

!! Verilog provides:Verilog provides:

!! Bus and register modeling utilitiesBus and register modeling utilities

!! For various bus structures, predefined wire and bus resolutionFor various bus structures, predefined wire and bus resolution

functions using the 4-value logic value system.functions using the 4-value logic value system.

!! Combination of bus logic and resolution-functions enable modeling ofCombination of bus logic and resolution-functions enable modeling of

most physical bus types.most physical bus types.

!! For register modeling, high-level clock representation and timing-For register modeling, high-level clock representation and timing-

control constructs can be used for representation of registers withcontrol constructs can be used for representation of registers with

various clocking and resetting schemes.various clocking and resetting schemes.



PLIPLI






Behavioral LevelBehavioral Level

BehavioralBehavioralLevelLevel


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Behavioral LevelBehavioral Level

!! Procedural blocks inProcedural blocks inVerilogVerilog enable algorithmic representations ofenable algorithmic representations of

hardware structures.hardware structures.

!! Constructs similar to those in software programming languages areConstructs similar to those in software programming languages are

provided for describing hardware at this level.provided for describing hardware at this level.



PLIPLI






System UtilitiesSystem Utilities



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!! System tasks inSystem tasks inVerilogVerilogprovide designers with tools for :provide designers with tools for :

!! TestbenchTestbench generationgeneration

!! File access for read and writeFile access for read and write

!! Data handlingData handling

!! Data generationData generation

!! Special hardware modeling.Special hardware modeling.

!! System utilities for reading memory and programmable logic arraySystem utilities for reading memory and programmable logic array

(PLA) images provide convenient ways of modeling these components.(PLA) images provide convenient ways of modeling these components.

!! VerilogVerilog display and I/O tasks can be used to handle all inputs anddisplay and I/O tasks can be used to handle all inputs and

outputs for data application and simulation.outputs for data application and simulation.!! VerilogVerilog allows random access to files for read and write operations.allows random access to files for read and write operations.



PLIPLI






Program Language InterfaceProgram Language Interface

PLIPLI


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Program Language InterfaceProgram Language Interface

!! The Programming Language Interface (PLI) forThe Programming Language Interface (PLI) forVerilogVerilog is ais a

mechanism to interfacemechanism to interfaceVerilogVerilogprograms with programs written in theprograms with programs written in the

C language. It also provides mechanisms to access internal databasesC language. It also provides mechanisms to access internal databases

of the simulator from C programs.of the simulator from C programs.

!! PLI is used for implementing system calls which would be hard to doPLI is used for implementing system calls which would be hard to do

otherwise (or impossible) usingotherwise (or impossible) usingVerilogVerilog syntax. Or, in other words, yousyntax. Or, in other words, you

can take advantage of both paradigms - the parallel and hardwarecan take advantage of both paradigms - the parallel and hardware

related features ofrelated features ofVerilogVerilog and the sequential flow of C - using the PLI.and the sequential flow of C - using the PLI.

!! Some of the most common applications of PLI are delay backSome of the most common applications of PLI are delay back

annotation, writing delay calculators and developing user interface.annotation, writing delay calculators and developing user interface.


TheTheVerilogVerilog LanguageLanguage

VerilogVerilog

HDLHDL






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TheTheVerilogVerilog LanguageLanguage

!! The Verilog HDL satisfies all requirements for design and synthesis ofThe Verilog HDL satisfies all requirements for design and synthesis ofdigital systems:digital systems:

!! Supports hierarchical description of hardware from system to gateSupports hierarchical description of hardware from system to gateor even switch level.or even switch level.

!! Has strong support at all levels for timing specification andHas strong support at all levels for timing specification andviolation detection.violation detection.

!! Timing and concurrency required for hardware modeling areTiming and concurrency required for hardware modeling arespecially emphasized in it.specially emphasized in it.

!! A hardware component is described by theA hardware component is described by the module declarationodule declarationlanguage construct in it.language construct in it.


TheTheVerilogVerilog LanguageLanguage!! The Verilog HDL satisfies all requirements for design and synthesis ofThe Verilog HDL satisfies all requirements for design and synthesis of

digital systems (Continued):digital systems (Continued):

!! Description of a module specifies a componentDescription of a module specifies a components input and outputs input and outputlist as well as internal component busses and registers within alist as well as internal component busses and registers within amodulemodule, concurrent assignments, component instantiations, and, concurrent assignments, component instantiations, and

procedural blocks can be used to describe a hardware component.procedural blocks can be used to describe a hardware component.

!! Several modules can hierarchically be instantiated to form otherSeveral modules can hierarchically be instantiated to form otherhardware structures.hardware structures.

!! Many Verilog tools and environments exist that provide simulation,Many Verilog tools and environments exist that provide simulation,fault simulation, formal verification, and synthesis.fault simulation, formal verification, and synthesis.

!!

Simulation environments provide graphical front-end programs andSimulation environments provide graphical front-end programs andwaveform editing and display tools.waveform editing and display tools.

!! Synthesis tools are based on a subset of Verilog.Synthesis tools are based on a subset of Verilog.

03 Design Flow

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