Defining Platform-Based Design

Defining Platform-Based DesignDefining Platform-Based Design

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OutlineOutline

A brief history of GSRC Platform-based DesignA brief history of GSRC Platform-based Design

Principles: Latest viewPrinciples: Latest view

MetropolisMetropolis

Two examplesTwo examplesPico-radio networkPico-radio network

Unmanned Helicopter controllerUnmanned Helicopter controller

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Platform Based DesignPlatform Based DesignWhat is it?What is it?

Question:Question: How many definitions of Platform Based Design are there?How many definitions of Platform Based Design are there?

Answer:Answer: How many people to you ask?How many people to you ask?

What does the confusion mean?What does the confusion mean? It is a definition in transition. It is a definition in transition.

OrOr Marketing has gotten involved….Marketing has gotten involved….

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Platform-Based Design Definitions:Platform-Based Design Definitions:Three PerspectivesThree Perspectives

Systems DesignersSystems Designers

SemiconductorSemiconductor

Academic (ASV)Academic (ASV)

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System DefinitionSystem Definition

Ericsson's Internet Services Platform is a new tool for Ericsson's Internet Services Platform is a new tool for

helping CDMA operators and service providers deploy helping CDMA operators and service providers deploy

Mobile Internet applications rapidly, efficiently and cost-Mobile Internet applications rapidly, efficiently and cost-

effectivelyeffectively Source: Ericsson press release

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Semiconductor DefinitionSemiconductor Definition

We define platform-based design as the creation of a stable We define platform-based design as the creation of a stable

microprocessor-based architecture that can be rapidly extended, microprocessor-based architecture that can be rapidly extended,

customized for a range of applications, and delivered to customized for a range of applications, and delivered to

customers for quick deployment.customers for quick deployment.

Source: Jean-Marc Chateau (ST Micro)

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PlatformsPlatforms

Platforms Examples

TI: OMAPPhilips: NexperiaARM: PrimeXSys

System

HW

SW

Xilinx: Virtex IIeASIC: eUnit

Implementation

Fabrics

Manufacturing

Cisco: ONS 15800 DWDM PlatformEricsson: Internet Services platformService

Nokia: Mobile Internet ArchitectureIntel: Personal Internet Client ArchitectureSony: Playstation 2

Application

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Platform Architectures: Philips Platform Architectures: Philips NexperiaNexperia

HardwareHardware Software Software

MiddlewareJavaTV, TVPAK, OpenTV, MHP/Java, proprietary ...

Applications

Nexperia Hardware

Streaming and Platform Software

Streaming and Platform Software K

ern

el:

pSO

S,

VxW

orks

, W

in-

CE

TM-xxxxD$

I$

TriMedia CPU

DEVICE IP BLOCK

DEVICE IP BLOCK

DEVICE IP BLOCK

. . .

DVP SYSTEM SILICON

PI

BU

S

SDRAM

MMI

DV

P M

EM

OR

Y

BU

S

DEVICE IP BLOCK

PRxxxxD$

I$

MIPS CPU

DEVICE IP BLOCK. . .

DEVICE IP BLOCK

PI

BU

S

TriMedia™MIPS™

Source: Philips

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Platform TypesPlatform Types

“Communication Centric Platform” SONIC, PalmchipSONIC, Palmchip

Concentrates on communicationConcentrates on communication Delivers communication framework plus peripheralsDelivers communication framework plus peripherals Limits the modeling effortsLimits the modeling efforts

SiliconBackplaneAgent™

Open Core Protocol™

SiliconBackplane™

(patented)

MultiChipBackplane™{

DSP MPEGCPUDMA

C MEM I O

SONICs Architecture

Source: G. Martin

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“Highly Programmable Platform” Triscend A7. Altera Excalibur, Xilinx Platform FPGA, ChameleonTriscend A7. Altera Excalibur, Xilinx Platform FPGA, Chameleon Concentrates on reconfigurabilityConcentrates on reconfigurability

Delivers reconfigurable processor plus programmable logicDelivers reconfigurable processor plus programmable logic Modeling efforts undetermined because of programmable partsModeling efforts undetermined because of programmable parts

Triscend A7

Xilinx Vertex II

Platform FPGA

Platform TypesPlatform Types

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ASV: The Next Level of Abstraction in the ASV: The Next Level of Abstraction in the Architecture SpaceArchitecture Space

abst

ract

Transistor ModelCapacity Load

1970’s

cluster

abst

ract

Gate Level ModelCapacity Load

1980’s

RTL

cluster

abst

ract

SDFWire Load

1990’s

IP Blocks

cluster

abst

ract

IP Block PerformanceInter IP Communication Performance Models

RTLClusters

SWModels

Year 2000 +

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Hardware Platforms (1998)Hardware Platforms (1998)

A Hardware Platform is a family of architectures that satisfy a set of architectural A Hardware Platform is a family of architectures that satisfy a set of architectural constraints imposed to allow the re-use of hardware and software components.constraints imposed to allow the re-use of hardware and software components.

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Hardware Platforms Not Enough!Hardware Platforms Not Enough!

Hardware platform has to be “extended” upwards to be Hardware platform has to be “extended” upwards to be

really effective in time-to-marketreally effective in time-to-market

Interface to the application software is an “API”Interface to the application software is an “API”

Software layer performs abstraction:Software layer performs abstraction:Programmable cores and memory subsystem with (RT)OSProgrammable cores and memory subsystem with (RT)OS

I/O subsystem via Device DriversI/O subsystem via Device Drivers

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Software PlatformsSoftware Platforms

Output DevicesInput devices

Hardware Platform

I O

Hardware

Software

Network

Software Platform

Application Software

Platform API

Software Platform

RT

OS

BIOS

Device Drivers

N

etw

ork

Com

mun

icat

ion

Co

mp

il er s

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ASV Triangles (1998)ASV Triangles (1998)

PlatformDesign-Space

Export

PlatformMapping

Architectural Space

Application SpaceApplication Instance

Platform Instance

SystemPlatform

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A Discipline of Platform-Based DesignA Discipline of Platform-Based Design

Silicon Implementation PlatformSilicon Implementation Platform

Architectural PlatformArchitectural Platform

Manfacturing InterfaceManfacturing Interface

Silicon ImplementationSilicon Implementation

Basic device & interconnectstructures

Delay, variation,SPICE models

Microarchitecture(s)Microarchitecture(s)

Circuit Fabric(s)Circuit Fabric(s)

Functional Blocks,InterconnectCycle-speed, power, area

S SV V SG

SG

SSV

V

SS SSVV VV SSGG

ApplicationApplication

Architecture(s)Architecture(s)

Kernels/BenchmarksProgramming Model:Models/Estimators

Source: R. Newton

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OutlineOutline


Principles: Latest versionPrinciples: Latest version

Meta-model and MetropolisMeta-model and Metropolis

Two examplesTwo examplesPico-radio networkPico-radio network


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ASV PlatformsASV Platforms

Platform

Mapping Tools

Platform

Platform stack {

In general, a platform is an abstraction layer that covers a number of possible refinements into a lower level.

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The design process is meet-in-the-middle:•Top-down: map an instance of the top platform into an instance of the lower platform and propagate constraints•Bottom-up: build a platform by defining the “library” that characterizes it and a performance abstraction (e.g., number of literals for tech. Independent optimization, area and propagation delay for a cell in a standard cell library)

The library has elements and interconnects

ASV PlatformsASV Platforms

For every platform, there is a view that is used to map the upper layers of abstraction into the platform and a view that is used to define the class of lower level abstractions implied by the platform.

For every platform, there is a view that is used to map the upper layers of abstraction into the platform and a view that is used to define the class of lower level abstractions implied by the platform.

Upper layer of abstraction

Lower layer of abstraction

Constraints Performance Annotation

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Platform-Based ImplementationPlatform-Based Implementation

Platforms eliminate Platforms eliminate large loop iterationslarge loop iterations for affordable design for affordable design

Restrict design space via new forms of regularity and structure that Restrict design space via new forms of regularity and structure that

surrender surrender somesome design potential for lower cost and first-pass success design potential for lower cost and first-pass success

The number and location of intermediate platforms is the essence of The number and location of intermediate platforms is the essence of

platform-based designplatform-based design

Silicon Implementation

Application

Silicon Implementation

Application

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Platform-Based Design ProcessPlatform-Based Design Process

Different situations will employ different intermediate platforms, Different situations will employ different intermediate platforms,

hence different layers of hence different layers of regularity and design-space constraintsregularity and design-space constraints

Critical step is defining intermediate platforms to support: Critical step is defining intermediate platforms to support: PredictabilityPredictability: abstraction to facilitate higher-level optimization: abstraction to facilitate higher-level optimization

VerifiabilityVerifiability: ability to ensure correctness: ability to ensure correctness

Architecture

Logic Regularity

Component Regularity and Reuse

Regular Fabrics

Geometrical Regularity Silicon Implementation

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Implementation ProcessImplementation Process

Skipping platforms can Skipping platforms can potentiallypotentially produce a superior design by produce a superior design by

enlarging design space – if design-time and product volume ($) enlarging design space – if design-time and product volume ($)

permitspermits

However, even for a large-step-across-platform flow there is a benefit However, even for a large-step-across-platform flow there is a benefit

to having to having a lower-bound on what is achievable a lower-bound on what is achievable from predictable flowfrom predictable flow

Geometrical Regularity Silicon Implementation

Architecture

Logic Regularity

Component Regularity and Reuse

Regular Fabrics

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Tight Lower BoundsTight Lower Bounds

The larger the step across platforms, the more difficult to: predict The larger the step across platforms, the more difficult to: predict

performance, optimize at system level, and provide a performance, optimize at system level, and provide a tighttight lower lower

bound bound

Design space may actually be Design space may actually be smallersmaller than with smaller steps since it than with smaller steps since it

is more difficult to explore and restriction on search impedes is more difficult to explore and restriction on search impedes

complete design space explorationcomplete design space exploration

The predictions/abstractions may be so wrong that design The predictions/abstractions may be so wrong that design

optimizations are misguided and the lower bounds are incorrect!optimizations are misguided and the lower bounds are incorrect!

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Design FlowDesign Flow

Theory:Theory:Initial intent captured with declarative notationInitial intent captured with declarative notation

Map into a set of interconnected component:Map into a set of interconnected component: Each component can be declarative or operationalEach component can be declarative or operational Interconnect is operational: describes how components interactInterconnect is operational: describes how components interact Repeat on each component until implementation is reachedRepeat on each component until implementation is reached

Choice of model of computations for component and interaction is Choice of model of computations for component and interaction is already a design step!already a design step!

Meta-model in Metropolis (operational) and Trace Algebras Meta-model in Metropolis (operational) and Trace Algebras (denotational) are used to capture this process and make it (denotational) are used to capture this process and make it rigorousrigorous

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ConsequencesConsequences There is no difference between HW and SW. Decision comes later.There is no difference between HW and SW. Decision comes later. HW/SW implementation depend on choice of component at the HW/SW implementation depend on choice of component at the

architecture platform level.architecture platform level. Function/Architecture co-design happens at all levels of abstractions Function/Architecture co-design happens at all levels of abstractions

Each platform is an “architecture” since it is a library of usable components and Each platform is an “architecture” since it is a library of usable components and interconnects. It can be designed independently of a particular behavior.interconnects. It can be designed independently of a particular behavior.

Usable components can be considered as “containers”, i.e., they can support a set Usable components can be considered as “containers”, i.e., they can support a set of behaviors.of behaviors.

Mapping choses one such behavior. A Platform Instance is a mapped behavior Mapping choses one such behavior. A Platform Instance is a mapped behavior onto a platform.onto a platform.

A fixed architecture with a programmable processor is a platform in this sense. A A fixed architecture with a programmable processor is a platform in this sense. A processor is indeed a collection of possible bahaviors.processor is indeed a collection of possible bahaviors.

A SW implementation on a fixed architecture is a platform instance.A SW implementation on a fixed architecture is a platform instance.

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OutlineOutline




Three examplesThree examplesPico-radio networkPico-radio network


High-performance micro-processorsHigh-performance micro-processors

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Metropolis FrameworkMetropolis FrameworkDesign

Constraints

Function

Specification

Architecture (Platform)

Specification

Metropolis Infrastructure

• Design methodology• Meta model of computation• Base tools - Design imports - Meta model compiler - Simulation

Synthesis/Refinement• Compile-time scheduling of concurrency

• Communication-driven hardware synthesis• Protocol interface generation

Analysis/Verification• Static timing analysis of reactive systems

• Invariant analysis of sequential programs• Refinement verification• Formal verification of embedded software

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Models of Computation: And There are More...Models of Computation: And There are More...

Continuous time (ODEs)Continuous time (ODEs)

Spatial/temporal (PDEs)Spatial/temporal (PDEs)

Discrete timeDiscrete time

RendezvousRendezvous

Synchronous/ReactiveSynchronous/Reactive

DataflowDataflow

......

Tower of Babel, Bruegel, 1563

Each of these provides a formal framework for reasoning about certain aspects of embedded systems. Source: Ed Lee

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Metropolis Meta ModelMetropolis Meta Model

Do not commit to the semantics of a particular Model of Computation (MoC)Do not commit to the semantics of a particular Model of Computation (MoC)

Define a set of “Define a set of “building blocksbuilding blocks”:”: specifications with many useful MoCs can be described using the building blocks.specifications with many useful MoCs can be described using the building blocks.

unambiguous semantics for each building block.unambiguous semantics for each building block.

syntax for each building block syntax for each building block a language of the meta modela language of the meta model..

Represent objects at Represent objects at allall design phases (mapped or unmapped)design phases (mapped or unmapped)

Question: What is a good set of building blocks?

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OutlineOutline



Embedded SoftwareEmbedded Software


Two examplesTwo examplesPico-radio network (BWRC and Nokia)Pico-radio network (BWRC and Nokia)

Unmanned Helicopter controller (Honeywell)Unmanned Helicopter controller (Honeywell)

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A Hierarchical Application of the Paradigm:A Hierarchical Application of the Paradigm:The Fractal Nature of Design!The Fractal Nature of Design!

Functional & Performance Requirements

Network Architecture

Performance analysis

NetworkLevel

Radio NodeLevel


Node Architecture



Network Architecture


ModuleLevel

Constraints

Constraints

Source: Jan Rabaey

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Network Platforms Network Platforms

• Network Platform Instance: set of resources (links and protocols) that provide Communication Services

• Network Platform API: set of Communication Services

• Communication Service: transfer of messages between ports

• Event trace defines order of send/receive methods• Quality of service

node

link

port

NPI I/O port

NP components:

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Network PlatformsNetwork Platforms

node

link

port

NPI I/O port

NP components:

Network Platform Instance

CommunicationServices:- CS1: Lossy Broadcast Error rate: 33% Max Delay: 30 ms- CS2: …

Network Platform API

PerformanceEstimates

ConstraintsBudgeting

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Network Platforms APINetwork Platforms API

es1, es2, es3 er11, er12

er21, er22, er23

event trace:

• NP API: set of Communication Services (CS)

• CS: message transfer defined by ports, messages, events (modeling send/receive methods), event trace

• Example• CS: lossy broadcast transfer of messages m1, m2, m3• Quality of Service (platform parameters):

• Losses: 1 ( m3)• Error rate: 33%• In-order delivery

• D(m3) = t(er23) – t (es3) = 30 ms

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Picoradio Network PlatformsPicoradio Network Platforms

CS S

CS S

Pull Push

Application Layer

Power < 100 uW, BER ~ 0

SS C

C SS

Multi-hop message delivery

Network Layer

=C S

SC

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OutlineOutline



Embedded SoftwareEmbedded Software


Three examplesThree examplesPico-radio network (BWRC and Nokia)Pico-radio network (BWRC and Nokia)

Unmanned Helicopter controller (Honeywell)Unmanned Helicopter controller (Honeywell)

Micro-processor and Chip Design (Intel and Cypress)Micro-processor and Chip Design (Intel and Cypress)

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Synchronous Platform Based UAV Design

Platform-Based Design

I

UAV System

II

Synchronous Embedded Control

III

Platform-Based Design of Unmanned Aerial Platform-Based Design of Unmanned Aerial VehiclesVehicles

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INS

R-50 Hovering

• Goal: basic autonomous flight• Need: UAV with allowable payload• Need: combination of GPS and

Inertial Navigation System (INS)• GPS (senses using triangulation)

• Outputs accurate position data• Available at low rate & has jamming

• INS (senses using accelerometer and rotation sensor)• Outputs estimated position with

unbounded drift over time• Available at high rate

• Fusion of GPS & INS provides needed high rate and accuracy

GPS Card

GPS Antenna

II. UAV System: II. UAV System: Sensor OverviewSensor Overview

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d dGPSINS

Software Request Software

GPSINS

Pull Configuration

Sharedmemory

Push Configuration

• Sensors may differ in:• Data formats, initialization schemes (usually requiring

some bit level coding), rates, accuracies, data communication schemes, and even data types

• Differing Communication schemes requires the most custom written code per sensor

II. UAV System: II. UAV System: Sensor ConfigurationsSensor Configurations

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III. Synchronous ControlIII. Synchronous Control Advantages of Advantages of time-triggered frameworktime-triggered framework: :

Allows for Allows for composabilitycomposability and and validationvalidation These are important properties for safety critical systems like the UAV These are important properties for safety critical systems like the UAV

controllercontroller Timing guarantees ensure Timing guarantees ensure no jitterno jitter

Disadvantages:Disadvantages: Bounded delayBounded delay is introduced is introduced

Stale data will be used by the controllerStale data will be used by the controller Implementation and system integration become more difficultImplementation and system integration become more difficult

Platform design allows for time-triggered framework for the UAV Platform design allows for time-triggered framework for the UAV controllercontroller Use Giotto as a middleware to ease implementation:Use Giotto as a middleware to ease implementation:

provides real-time guarantees for control blocksprovides real-time guarantees for control blocks handles all processing resources handles all processing resources Handles all I/O proceduresHandles all I/O procedures

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Platform Based Design for UAVsPlatform Based Design for UAVs

Sensors: INS, GPSActuators: Servo InterfaceVehicles: Yamaha R-50/R-

Max

Control Applications (Matlab)

GoalGoal Abstract details of sensors, Abstract details of sensors,

actuators, and vehicle actuators, and vehicle hardware from control hardware from control applicationsapplications

How?How? Synchronous Embedded Synchronous Embedded

Programming Language Programming Language (i.e. Giotto)(i.e. Giotto)

PlatformPlatform

Synchronous Embedded

Programming(Giotto)

Application Space

Architectural Space

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Platform Based Design for UAVsPlatform Based Design for UAVs Device PlatformDevice Platform

IsolatesIsolates details of sensor/actuators details of sensor/actuators from embedded control programsfrom embedded control programs

CommunicatesCommunicates with each with each sensor/actuator according to its own sensor/actuator according to its own data format, context, and timing data format, context, and timing requirementsrequirements

PresentsPresents an API to embedded control an API to embedded control programs for accessing programs for accessing sensors/actuatorssensors/actuators

Language PlatformLanguage Platform ProvidesProvides an environment in which an environment in which

synchronous control programs can be synchronous control programs can be scheduled and runscheduled and run

AssumesAssumes the use of generic data the use of generic data formats for sensors/actuators made formats for sensors/actuators made possible by the Device Platformpossible by the Device Platform

Sensors: INS, GPSActuators: Servo InterfaceVehicles: Yamaha R-50/R-

Max

Synchronous Embedded

Programming(Giotto)

Control Applications (Matlab)

Application Space

Architectural Space

Virtual Avionics Platform

Device Platform

Language Platform

Defining Platform-Based Design

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