D Flip-Flop Design

Design Practice - MyCAD

D Flip-Flop Design Practice - MyCAD 2

• Preface• Inverter Gate Design

– Inverter gate schematic and symbol– Inverter gate simulation– Inverter gate layout and results of verification

• NAND2 Gate Design– NAND2 gate schematic and symbol– NAND2 simulation– NAND2 gate layout and results of verification

• NAND3 Gate Design– NAND3 gate schematic and symbol– NAND3 simulation– NAND3 gate layout and results of verification

• D Flip-Flop Design– D Flip-Flop schematic and symbol– D Flip-Flop simulation– D Flip-Flop layout and results of verification

• D Flip-Flop P/C Design– D Flip-Flop P/C schematic and symbol– D Flip-Flop P/C simulation– D Flip-Flop P/C layout and results of verification

Table of Contents

D Flip-Flop Design Practice - MyCAD 3

Preface

• This document provides the information on how to design D Filp-Flop schematic and layout.

• D Flip-Flop is designed based on MOSIS SCMOS layout rules.

• If you want to get more information, please refer to the related documents as below.– MyCAD Tutorial :

Learn how to use schematic and layout editor.– MySpice Tutorial :

Learn about simulating a circuit.– MyChip Pro Verification Reference Manual :

Look up specific verification commands.

Copyright © 1992 – 2006, SELOCO Incorporated.

D Flip-Flop Design Practice - MyCAD 4

Inverter schematic and symbol

10

01

OUTIN

OutputInput

Logic Symbol

Truth TableSchematic

L = 0.2umW = 1.6um

L = 0.2umW = 0.6um

D Flip-Flop Design Practice - MyCAD 5

Inverter Simulation

IN OUT

D Flip-Flop Design Practice - MyCAD 6

Inverter layout and results of verification

Layout

DRC result

LVS result

D Flip-Flop Design Practice - MyCAD 7

NAND2 schematic and symbol

Logic Symbol

Truth Table Schematic011

101

110

100

OUTIN1IN0

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NAND2 Simulation

OUT

IN0

IN1

D Flip-Flop Design Practice - MyCAD 9

NAND2 layout and results of verification

Layout

DRC result

LVS result

D Flip-Flop Design Practice - MyCAD 10

NAND3 schematic and symbol

Logic Symbol

Truth Table Schematic

0111

1011

1101

1001

1110

1010

1100

1000

OUTCBA

OutputInput

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NAND3 Simulation

IN0 IN1

OUTIN2

D Flip-Flop Design Practice - MyCAD 12

NAND3 layout and results of verification

Layout

DRC result

LVS result

D Flip-Flop Design Practice - MyCAD 13

D Flip-Flop schematic and symbol

Logic Symbol

Truth Table Schematic

011↑

100↑

Q_barQDCLK

OutputInput

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D Flip-Flop Simulation

Clock D (input)

Q (output)

D Flip-Flop Design Practice - MyCAD 15

D Flip-Flop layout and results of verification

Layout

DRC result

LVS result

D Flip-Flop Design Practice - MyCAD 16

D Flip-Flop with Preset and Clearschematic and symbol

Logic Symbol

Truth Table

101

Q_bar(t)Q_bar(t)

10

011

Q(t)Q(t)

01

XXXXX01

1001111

0101111

XXX10

Q_bar(t+1)Q(t+1)DPRECLRCLK

OUTPUTINPUT

Schematic

D Flip-Flop Design Practice - MyCAD 17

D Flip-Flop with Preset and ClearSimulation (1/2)

Clock D (input)

Preset Clear

D Flip-Flop Design Practice - MyCAD 18

D Flip-Flop with Preset and ClearSimulation (2/2)

Q (output) Q_bar (output)

D Flip-Flop Design Practice - MyCAD 19

D Flip-Flop with Preset and Clearlayout and results of verification

Layout

DRC result LVS result

The End