Cyclone V GT Development Kit Board

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8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 E E D D C C B B A A DESCRIPTION REV DATE PAGES PAGE DESCRIPTION 2 NOTES: Title, Notes, Block Diagram, Rev. History 1 3 4 7 8 9 10 11 12 13 14 15 16 17 JTAG 18 19 20 21 22 23 24 25 5 6 1129 Parts, 106 Library Parts, 1085 Nets, 5532 Pins A 1/04/2013 All Released Rev A FPGA Package Top Cyclone V GT Development Kit Board 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework PCI Express Edge Connector Cyclone V GT Banks 3 and 4 Cyclone V GT Transceiver Banks 2. 100-0321004-B1 110-0321004-B1 120-0321004-B1 130-0321004-B1 140-0321004-B1 150-0321004-B1 160-0321004-B1 170-0321004-B1 180-0321004-B1 210-0321004-B1 220-0321004-B1 320-0321004-B1 On-Board USB Blaster II 26 27 28 29 PAGE DESCRIPTION 30 Flash 5M2210 System Controller User I/O Power 2 - 1.1V (C5_VCC) Power 1 - DC Input, 12V, 3.3V Cyclone V GT Clocks DDR3A x40 Hard Memory Controller Ethernet PHY & RJ-45 Power 3 - 1.2V (C5_GXB) HSMC Port A & Port B Power 7 - Power Monitor Power 4 - 2.5V (C5_2.5V) Decoupling Cyclone V GT Power Cyclone V GT Configuration Clocks SDI Port A TX/RX Cable Driver & SMB Cyclone V GT Banks 5 and 6 Cyclone V GT Banks 7 and 8 DDR3A x64 Soft Memory Controller ASSP CPLD Power 5 - 1.5V Power 6 - LTC3605 VAR B 3/15/2013 All Released Rev B - Swap HSMA/B Dip switch position, Changed ASSP MAX II device to M100, Changed EPCQ, Rerouted JTAG signals and added filter to TCK, Changed LCD to include SPI option, Changed Flash connections and translator device, Moved C170 to top of board. Title Size Document Number Rev Date: Sheet of B Cyclone V GT FPGA Development Kit Board B 1 30 Thursday, May 02, 2013 150-0321004-B1 (6XX-44179R) Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Copyright (c) 2013, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of B Cyclone V GT FPGA Development Kit Board B 1 30 Thursday, May 02, 2013 150-0321004-B1 (6XX-44179R) Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Copyright (c) 2013, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of B Cyclone V GT FPGA Development Kit Board B 1 30 Thursday, May 02, 2013 150-0321004-B1 (6XX-44179R) Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Transcript of Cyclone V GT Development Kit Board

Page 1: Cyclone V GT Development Kit Board

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DESCRIPTIONREV DATE PAGES

PAGE DESCRIPTION

2

NOTES:

Title, Notes, Block Diagram, Rev. History1

34

7891011121314151617

JTAG

1819202122232425

56

1129 Parts, 106 Library Parts, 1085 Nets, 5532 Pins

A 1/04/2013 All Released Rev A

FPGA Package Top

Cyclone V GT Development Kit Board

1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework

PCI Express Edge ConnectorCyclone V GT Banks 3 and 4

Cyclone V GT Transceiver Banks

2.

100-0321004-B1110-0321004-B1120-0321004-B1130-0321004-B1140-0321004-B1150-0321004-B1160-0321004-B1170-0321004-B1180-0321004-B1210-0321004-B1220-0321004-B1320-0321004-B1

On-Board USB Blaster II

26272829

PAGE DESCRIPTION30

Flash5M2210 System Controller

User I/O

Power 2 - 1.1V (C5_VCC)Power 1 - DC Input, 12V, 3.3V

Cyclone V GT Clocks

DDR3A x40 Hard Memory Controller

Ethernet PHY & RJ-45

Power 3 - 1.2V (C5_GXB)

HSMC Port A & Port B

Power 7 - Power Monitor

Power 4 - 2.5V (C5_2.5V)

Decoupling

Cyclone V GT Power

Cyclone V GT Configuration

Clocks

SDI Port A TX/RX Cable Driver & SMB

Cyclone V GT Banks 5 and 6Cyclone V GT Banks 7 and 8

DDR3A x64 Soft Memory Controller

ASSP CPLD

Power 5 - 1.5VPower 6 - LTC3605 VAR

B 3/15/2013 All Released Rev B - Swap HSMA/B Dip switch position, Changed ASSP MAX II device to M100,Changed EPCQ, Rerouted JTAG signals and added filter to TCK, Changed LCD to include SPIoption, Changed Flash connections and translator device, Moved C170 to top of board.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B1 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B1 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B1 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Page 2: Cyclone V GT Development Kit Board

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D D

C C

B B

A A

BANK 8A

HSMC Port A - LVDS

XCVR BANKS QL0, QL1PCIe x4HSMC Port A x2

Package Top View

VCCIO = 2.5VBANK 7A

HSMC Port B - x32 DQ/DQSVCCIO = Variable (Default = 2.5V)

Ethernet, PCIe,User I/O

Flash

BANK 5A

BANK 3AVCCIO = 2.5V

DDR3B X64 (SMC)

BANK 5B / 6AVCCIO = 1.5V

USB Blaster IIDDR3 x32 (HMC)

BANK 3BVCCIO = 1.5V

DDR3 x32 (HMC)

VCCIO = 1.5VBANK 4A

VCCIO = 1.8V

XCVR BANKS QL2, QL3HSMC Port A x2HSMC Port B x4

Hardware Option SDI x1

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B2 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B2 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B2 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Page 3: Cyclone V GT Development Kit Board

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A A

PCI Express Edge Connector

Link Width DIP Switch

JTAG Chain ControlON = not-in-chainOFF = in-chain

PCIE_TX_CP2PCIE_TX_CN2

PCIE_TX_CP3PCIE_TX_CN3

PCIE_TX_CN1PCIE_TX_CP1

PCIE_TX_CP0PCIE_TX_CN0

PCIE_WAKEn_R3.3V_PCIE_AUX

PCIE_PRSNT2n_x4PCIE_PRSNT2n_x1

PCIE_PRSNT2n_x4

PCIE_PRSNT2n_x1

PCIE_PRSNT1n

HSMB_JTAG_ENHSMA_JTAG_EN

12V_PCIE 3.3V_PCIE12V_PCIE

12V_PCIE 3.3V_PCIE

3.3V_PCIE

2.5V

PCIE_RX_N07PCIE_RX_P07

PCIE_RX_N17PCIE_RX_P17

PCIE_RX_N27PCIE_RX_P27

PCIE_RX_N37PCIE_RX_P37

PCIE_SMBDAT4

PCIE_TX_N0 7

PCIE_TX_P07

PCIE_TX_N1 7

PCIE_TX_P1 7

PCIE_TX_N2 7

PCIE_TX_P27

PCIE_TX_N3 7

PCIE_TX_P37

PCIE_WAKEn4 PCIE_PERSTn 10

PCIE_REFCLK_P 7PCIE_REFCLK_N 7

PCIE_SMBCLK4

HSMB_JTAG_EN 11HSMA_JTAG_EN 11

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B3 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B3 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B3 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C5560.1uF

R107 DNI

C5490.1uF

R72 1.00k

C5590.1uF

C1230.1uF

C1270.1uF

R106 DNI

C5520.1uF

C5570.1uF

KEY

X4

X1

J16

PCIE_Slot

+12VB1

+12VB2

+12VB3

GNDB4

SMCLKB5

SMDATB6

GNDB7

+3_3VB8

JTAG_TRSTNB9

+3_3VAUXB10

WAKE_NB11

RSVD1B12

GNDB13

PET0PB14

PET0NB15

GNDB16

PRSNT2_N_X1B17

GNDB18

PET1PB19

PET1NB20

GNDB21

GNDB22

PET2PB23

PET2NB24

GNDB25

GNDB26

PET3PB27

PET3NB28

GNDB29

RSVD3B30

PRSNT2_N_X4B31

GNDB32

PRSNT1_NA1

+12VA2

+12VA3

GNDA4

JTAG_TCKA5

JTAG_TDIA6

JTAG_TDOA7

JTAG_TMSA8

+3_3VA9

+3_3VA10

PERST_NA11

GNDA12

REFCLK+A13

REFCLK-A14

GNDA15

PER0PA16

PER0NA17

GNDA18

RSVD2A19

GNDA20

PER1PA21

PER1NA22

GNDA23

GNDA24

PER2PA25

PER2NA26

GNDA27

GNDA28

PER3PA29

PER3NA30

GNDA31

RSVD4A32

C5550.1uF

B1

PCI BRACKET

C5540.1uF

C5500.1uF

R73 1.00k

C1240.1uF

C1250.1uF

C1260.1uF

OPEN

SW3

TDA04H0SB1

1234 5

678

C5530.1uF

C5510.1uF

C5580.1uF

Page 4: Cyclone V GT Development Kit Board

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USB INTERFACE

DDR3A x40 HMC INTERFACE

VCCIO = 1.5V

VCCIO = 1.5V

Cyclone V GT Banks 3 and 4

ETHERNET INTERFACE

PCIE INTERFACE

VCCIO = 2.5V

USER INTERFACE

SDI INTERFACE

MVE ASSP Core InterfaceFLASH INTERFACE

DISPLAY INTERFACE

RZQIN_1_5V

DDR3A_CKE

DDR3A_WEn

USB_OEn

USB_WRn

USB_SDAUSB_SCL

USB_DATA3

DDR3A_CASn

DDR3A_RESETn

DDR3A_A13

DDR3A_ODT

DDR3A_A4

DDR3A_A0

DDR3A_A7

DDR3A_A1

DDR3A_A9DDR3A_BA1

DDR3A_RASn

DDR3A_A12

DDR3A_A6

DDR3A_CSn

DDR3A_A8

USB_DATA7USB_DATA4

DDR3A_A5

USB_ADDR0USB_DATA2

USB_DATA5

USB_DATA0

USB_DATA1

USB_DATA6

DDR3A_DQ22DDR3A_DQ21

DDR3A_DQ23

DDR3A_DQ17

DDR3A_DQ20

DDR3A_DQ18

DDR3A_DQ16

DDR3A_DQ19

DDR3A_DM2

DDR3A_DQ27

DDR3A_DQ29

DDR3A_DM3

DDR3A_DQ24

DDR3A_DQ28

DDR3A_DQ31

DDR3A_DQ26DDR3A_DQ25

DDR3A_DQ30

DDR3A_DQS_N3DDR3A_DQS_P3

DDR3A_BA2

USB_FULLUSB_EMPTY

DDR3A_DQ38

DDR3A_DQ36

DDR3A_DM4

DDR3A_DQ34DDR3A_DQ35

DDR3A_DQ37

DDR3A_DQ39

DDR3A_DQ32DDR3A_DQ33

DDR3A_DQ10

DDR3A_DM1

DDR3A_DQ9

DDR3A_DQ12DDR3A_DQ13DDR3A_DQ14DDR3A_DQ15

DDR3A_DQ11

DDR3A_DQ8

DDR3A_DQS_N1DDR3A_DQS_P1

DDR3A_DQ1

DDR3A_DQ6DDR3A_DQ7

DDR3A_DQ5

DDR3A_DQ3

DDR3A_DM0

DDR3A_DQ4

DDR3A_A10

DDR3A_BA0

DDR3A_DQS_N0DDR3A_DQS_P0

DDR3A_A11

DDR3A_DQS_N4DDR3A_DQS_P4

DDR3A_DQS_N2DDR3A_DQS_P2

USB_ADDR1

DISP_I2C_SDA

PCIE_WAKEnPCIE_SMBCLK

PCIE_SMBDAT

ENET_RX_D3ENET_GTX_CLK

ENET_RESETnENET_INTn

ENET_RX_D2

ENET_TX_D1ENET_TX_D3ENET_TX_D0

ENET_TX_D2

ENET_RX_DV

ENET_TX_EN

ENET_RX_D1

ENET_MDCDISP_I2C_SCL

ENET_RX_D0

ENET_MDIO

ENET_RX_CLK

DDR3A_DQ0

DDR3A_DQ2

FLASH_RESETn

SDI_A_TX_EN

SDI_A_RX_BYPASS

SDI_A_TX_SD_HDn

SDI_A_RX_EN

USER_PB1

USER_PB0

USER_PB2

FLASH_WEn

FLASH_OEn

DDR3A_CLK_PDDR3A_CLK_N

ASSP_RUN_IN

ASSP_DATAOUTASSP_RANDOM_INASSP_CLK

ASSP_SYS_RESETASSP_SHIFT_ENASSP_TEST1ASSP_TEST2

USER_LED0

USER_LED1USER_LED4USER_LED2USER_LED3

USER_LED5USER_LED7

USER_LED6

PCIE_LED_X1

PCIE_LED_X4

DISP_SPISS

USB_DATA[7:0]19

USB_SDA 19

USB_RESETn 9,19USB_OEn 19

USB_WRn 19

USB_RDn 9,19

DDR3A_DQ[39:0]12

DDR3A_CSn 12

DDR3A_CKE 12DDR3A_CASn 12

DDR3A_RASn 12DDR3A_WEn 12

DDR3A_ODT 12

DDR3A_DQS_P[4:0]12

DDR3A_DQS_N[4:0]12

DDR3A_DM[4:0]12

DDR3A_BA[2:0]12

DDR3A_A[13:0]9,12

DDR3A_RESETn 12

USB_ADDR[1:0]19

USB_SCL 19

USB_FULL 19USB_EMPTY 19

PCIE_SMBDAT 3

PCIE_WAKEn 3PCIE_SMBCLK 3

ENET_MDIO 17ENET_RESETn 17ENET_INTn 17

ENET_MDC 17

PCIE_LED_X4 20PCIE_LED_X1 20

ENET_RX_D[3:0]17

ENET_TX_D[3:0]17

ENET_GTX_CLK 17

ENET_RX_DV 17ENET_TX_EN 17

ENET_RX_CLK 17

FLASH_RESETn 14,15 USER_LED[7:0]20

SDI_A_TX_EN 15,16SDI_A_RX_BYPASS 15,16SDI_A_RX_EN 15,16SDI_A_TX_SD_HDn 16

USER_PB[2:0]20

FLASH_WEn 14,15

DDR3A_CLK_P 12DDR3A_CLK_N 12

ASSP_DATAOUT 21

ASSP_TEST1 21ASSP_TEST2 21

ASSP_CLK 21ASSP_RANDOM_IN 21

ASSP_SYS_RESET 21ASSP_RUN_IN 21

FLASH_OEn 14,15

DISP_I2C_SCL 20

DISP_I2C_SDA 20

DISP_SPISS 20

ASSP_SHIFT_EN 21

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B4 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B4 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B4 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Bank 3ACyclone V GT Bank 3

Bank 3B (HMC)

HMC_B_A_2, 3 at Clocksection

5CGTFD9E5F35

U13A

Version = 0.2 Preliminary

DQ2B/DIFFIO_TX_B16nAP7

DQ2B/DIFFIO_RX_B14pAH13

DQ2B/DIFFIO_RX_B10nAK10

DQ2B/DIFFIO_TX_B12nAN4

DQ2B/DIFFIO_RX_B10pAJ10 DQ2B/DIFFIO_TX_B9pAL6

DQ2B/DIFFIO_TX_B16pAN7

DQ3B/DIFFIO_RX_B18pAG14DQ3B/DIFFIO_TX_B17pAM8

DQ3B/DIFFIO_TX_B21nAM10

DQ3B/DIFFIO_TX_B20nAN9

DQ3B/DIFFIO_TX_B24nAK12

DQ3B/DIFFIO_RX_B22pAJ14

DQ3B/DIFFIO_TX_B21pAL10

DQ3B/DIFFIO_RX_B22nAK14

DIFFIO_RX_B23nAB15

DIFFIO_TX_B12pAN5DIFFIO_RX_B15p

AD14

DIFFIO_RX_B15nAE14

DIFFIO_TX_B17nAN8

DIFFIO_RX_B23pAA15

DIFFIO_TX_B20pAM9

DQ2B/DIFFIO_TX_B13nAP5 DQ2B/DIFFIO_TX_B13pAP6

DQ3B/DIFFIO_RX_B18nAH14

DQS3B/DIFFIO_RX_B19pAD15

DQ2B/DIFFIO_RX_B14nAJ12

DQ3B/DIFFIO_TX_B24pAK13

DQS2B/DIFFIO_RX_B11pAB14

DQSn2B/DIFFIO_RX_B11nAB13

DIFFIO_TX_B9nAM6

DQSn3B/DIFFIO_RX_B19nAC14

HMC_B_A_1/DQ6B/DIFFIO_TX_B48nAL18 HMC_B_A_0/DQ6B/DIFFIO_TX_B48pAK18

HMC_B_A_11/DQ5B/DIFFIO_TX_B37nAM16HMC_B_A_10/DQ5B/DIFFIO_TX_B37pAL16

HMC_B_A_14/DQ5B/DIFFIO_RX_B34pAM14HMC_B_A_13/DQ5B/DIFFIO_TX_B36nAN13HMC_B_A_12/DIFFIO_TX_B36pAM13

DQ4B/DIFFIO_TX_B32nAL13 DQ4B/DIFFIO_TX_B32pAL12

DQ4B/DIFFIO_TX_B29pAN11

DQ4B/DIFFIO_RX_B30pAJ15

DQ4B/DIFFIO_RX_B26pAL15

DQ4B/DIFFIO_TX_B28nAP9

DQ4B/DIFFIO_TX_B29nAP11

DQ4B/DIFFIO_RX_B30nAK15

HMC_B_A_15/DQ5B/DIFFIO_RX_B34nAN14

HMC_B_A_5/DQ6B/DIFFIO_RX_B46nAJ17

DQ4B/DIFFIO_TX_B25pAL11

HMC_B_A_7/DQ6B/DIFFIO_TX_B44nAL17

HMC_B_A_4/DQ6B/DIFFIO_RX_B46pAH17

HMC_B_A_6/DIFFIO_TX_B44pAK17

DQ4B/DIFFIO_RX_B26nAM15

HMC_B_A_8/DQ5B/DIFFIO_RX_B38pAH16

DIFFIO_RX_B31nAD16

HMC_B_WEn/DQ5B/DIFFIO_TX_B33pAN12

DIFFIO_TX_B28pAP10

HMC_GND/DIFFIO_TX_B33nAP12

HMC_GND/DIFFIO_TX_B41nAP16

DIFFIO_TX_B25nAM11

DIFFIO_RX_B31pAC16

HMC_B_RASn/DQ5B/DIFFIO_TX_B40nAP14

HMC_B_CKn/DQSn6B/DIFFIO_RX_B43nAA17 HMC_B_CSn_0/DQS5B/DIFFIO_RX_B35p

AA16

HMC_B_BA_2/DQ6B/DIFFIO_RX_B42nAP17

HMC_B_BA_0/DQ6B/DIFFIO_TX_B41pAN16

HMC_B_BA_1/DQ6B/DIFFIO_RX_B42pAN17

HMC_B_CK/DQS6B/DIFFIO_RX_B43pAA18

HMC_B_CASn/DQ5B/DIFFIO_TX_B40pAP15

HMC_B_A_9/DQ5B/DIFFIO_RX_B38nAJ16

HMC_B_CSn_1/DQSn5B/DIFFIO_RX_B35nAB16

DQS4B/DIFFIO_RX_B27pAG16

DQSn4B/DIFFIO_RX_B27nAG15

R272100, 1%Bank 4ACyclone V GT Bank 4

5CGTFD9E5F35

U13B

Version = 0.2 Preliminary

DQ12B/DIFFIO_RX_B94nAG26DQ12B/DIFFIO_RX_B90pAG24

DQ12B/DIFFIO_TX_B89pAJ29DQ12B/DIFFIO_RX_B94pAG25

HMC_B_DQ_1/DQ7B/DIFFIO_RX_B50pAM19 HMC_B_DQ_0/DQ7B/DIFFIO_RX_B50nAN19

HMC_B_DQ_3/DQ7B/DIFFIO_TX_B52nAP21 HMC_B_DQ_2/DQ7B/DIFFIO_TX_B49pAP20

HMC_B_DQ_5/DQ7B/DIFFIO_RX_B54pAG19 HMC_B_DQ_4/DQ7B/DIFFIO_RX_B54nAH19

HMC_B_DQ_7/DQ7B/DIFFIO_TX_B56nAM21 HMC_B_DQ_6/DQ7B/DIFFIO_TX_B53pAJ19

HMC_B_DQ_9/DQ8B/DIFFIO_RX_B58pAL20 HMC_B_DQ_8/DQ8B/DIFFIO_RX_B58nAM20

HMC_B_DQ_11/DQ8B/DIFFIO_TX_B60nAN23 HMC_B_DQ_10/DQ8B/DIFFIO_TX_B57pAN22

HMC_B_DQ_13/DQ8B/DIFFIO_RX_B62pAP25 HMC_B_DQ_12/DQ8B/DIFFIO_RX_B62nAP24

HMC_B_DQ_15/DQ8B/DIFFIO_TX_B64nAN24 HMC_B_DQ_14/DQ8B/DIFFIO_TX_B61pAN26

HMC_B_DQ_36/DQ11B/DIFFIO_RX_B86nAK25HMC_B_DQ_35/DQ11B/DIFFIO_TX_B84nAN29

HMC_B_DQ_38/DQ11B/DIFFIO_TX_B85pAK28HMC_B_DQ_37/DQ11B/DIFFIO_RX_B86pAJ25

HMC_B_DM_4/DQ11B/DIFFIO_TX_B88pAL30HMC_B_DQ_39/DQ11B/DIFFIO_TX_B88nAM30

HMC_B_DQSn_4/DQSn11B/DIFFIO_RX_B83nAD21HMC_B_DQS_4/DQS11B/DIFFIO_RX_B83pAC21

HMC_B_ODT_1/DQ7B/DIFFIO_TX_B53nAK19

HMC_B_DQS_0/DQS7B/DIFFIO_RX_B51pAB19

HMC_B_CKE_0/DQ8B/DIFFIO_TX_B61nAP26

HMC_B_DQS_1/DQS8B/DIFFIO_RX_B59pAD19

HMC_B_ODT_0/DIFFIO_TX_B52pAN21

HMC_B_RESETn/DIFFIO_TX_B68pAJ22

HMC_B_DM_0/DQ7B/DIFFIO_TX_B56pAL21

HMC_B_DQSn_0/DQSn7B/DIFFIO_RX_B51nAC19

HMC_B_DM_1/DQ8B/DIFFIO_TX_B64pAM24

HMC_B_DQSn_1/DQSn8B/DIFFIO_RX_B59nAE19

HMC_B_CKE_1/DIFFIO_TX_B60pAM23

DQ12B/DIFFIO_RX_B90nAH24

HMC_GND/DIFFIO_TX_B57nAP22

HMC_GND/DIFFIO_RX_B87pAE23

HMC_GND/DIFFIO_TX_B73nAM25HMC_GND/DIFFIO_TX_B65nAL22

HMC_B_DQ_17/DQ9B/DIFFIO_RX_B66pAN27 HMC_B_DQ_16/DQ9B/DIFFIO_RX_B66nAP27

HMC_B_DQ_19/DQ9B/DIFFIO_TX_B68nAJ21 HMC_B_DQ_18/DQ9B/DIFFIO_TX_B65pAK22

HMC_B_DQ_21/DQ9B/DIFFIO_RX_B70pAH22 HMC_B_DQ_20/DQ9B/DIFFIO_RX_B70nAH21

HMC_B_DQ_23/DQ9B/DIFFIO_TX_B72nAN28 HMC_B_DQ_22/DQ9B/DIFFIO_TX_B69pAP30

HMC_GND/DIFFIO_RX_B87nAF23

HMC_GND/DIFFIO_RX_B71nAB20

DQSn12B/DIFFIO_RX_B91nAD22DQS12B/DIFFIO_RX_B91pAC22

HMC_GND/DIFFIO_RX_B79pAF22

HMC_B_DM_2/DQ9B/DIFFIO_TX_B72pAM28

HMC_B_DQSn_2/DQSn9B/DIFFIO_RX_B67nAK20

HMC_GND/DIFFIO_RX_B71pAB21

HMC_GND/DIFFIO_TX_B76pAL26

HMC_B_DQS_2/DQS9B/DIFFIO_RX_B67pAJ20

HMC_B_DQ_24/DQ10B/DIFFIO_RX_B74nAL23

HMC_GND/DIFFIO_RX_B79nAG21

HMC_GND/DIFFIO_TX_B84pAM29HMC_GND/DIFFIO_TX_B81nAP32

DIFFIO_RX_B95pAF25

HMC_GND/DQ10B/DIFFIO_TX_B77nAP31

HMC_B_DQ_26/DQ10B/DIFFIO_TX_B73pAL25 HMC_B_DQ_25/DQ10B/DIFFIO_RX_B74pAK23

HMC_B_DQ_28/DQ10B/DIFFIO_RX_B78nAK24 HMC_B_DQ_27/DQ10B/DIFFIO_TX_B76nAM26

HMC_B_DQ_30/DQ10B/DIFFIO_TX_B77pAN31 HMC_B_DQ_29/DQ10B/DIFFIO_RX_B78pAJ24

HMC_B_DM_3/DQ10B/DIFFIO_TX_B80pAL27 HMC_B_DQ_31/DQ10B/DIFFIO_TX_B80nAL28

HMC_GND/DQ9B/DIFFIO_TX_B69nAP29

HMC_GND/DQ11B/DIFFIO_TX_B85nAK27

DIFFIO_RX_B95nAE25

RZQ_0/DIFFIO_TX_B49nAP19

HMC_B_DQS_3/DQS10B/DIFFIO_RX_B75pY20

HMC_B_DQ_32/DQ11B/DIFFIO_RX_B82nAH23

DIFFIO_TX_B89nAK29

HMC_B_DQSn_3/DQSn10B/DIFFIO_RX_B75nAA20

HMC_B_DQ_33/DQ11B/DIFFIO_RX_B82pAG23

DIFFIO_TX_B92pAL31

HMC_B_DQ_34/DQ11B/DIFFIO_TX_B81pAN32

DQ12B/DIFFIO_TX_B93nAJ26

DQ12B/DIFFIO_TX_B93pAH26

DQ12B/DIFFIO_TX_B92nAM31

DQ12B/DIFFIO_TX_B96nAJ27

DQ12B/DIFFIO_TX_B96pAH27

Page 5: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Cyclone V GT Banks 5 and 6

VCCIO =1.8V

VCCIO = 1.5V

FLASH INTERFACE

MAX V CONTROL

DDR3B x64 SMC INTERFACE

VCCIO = 1.5V

FM_A1

FM_A17

FM_A9

FM_A21FM_A23FM_A24

FM_A22

FM_A18FM_A19FM_A20

DDR3B_DQ30

DDR3B_WEn

FM_D4FM_D3FM_D2

FM_D11FM_D12

FM_D1

FM_D10

FM_D5

FM_D7FM_D6

FM_D15

MAX_CSnFM_A14FM_A15

FM_A12

FM_A13

FM_A16

FM_A3

FM_A8

FM_A10

FM_A11

FM_A7

FM_A25

FM_A4FM_A5

FM_D9FM_D8FM_A6

FM_D0

DDR3B_DQ21

DDR3B_DQ29

DDR3B_A7

DDR3B_A0

DDR3B_A11

DDR3B_A6

DDR3B_A1

DDR3B_A5

DDR3B_CLK_N

DDR3B_A3

DDR3B_CLK_P

DDR3B_A2

DDR3B_A10

DDR3B_A4

DDR3B_RESETn

DDR3B_DQS_P2DDR3B_BA2DDR3B_DQS_N2

DDR3B_RASn

DDR3B_CASn

DDR3B_ODT

DDR3B_DQ18

DDR3B_BA0DDR3B_BA1

DDR3B_DQ23DDR3B_DQ16

DDR3B_DQ24

DDR3B_DQ22

DDR3B_DQ19

DDR3B_DQ17

DDR3B_DQ25

DDR3B_DQS_P3

DDR3B_DQ28

DDR3B_DQ27

DDR3B_DM2

DDR3B_DQ26

DDR3B_DQ31

DDR3B_DQS_N3

DDR3B_DQ0

DDR3B_DQS_P0

DDR3B_DQ15

DDR3B_DQ11

DDR3B_DQ5DDR3B_DQ1

DDR3B_DQ3

DDR3B_DQS_P1

DDR3B_DQ8

DDR3B_DQ4

DDR3B_DQ6

DDR3B_DQS_N0

DDR3B_DM1

DDR3B_DQ13

DDR3B_DQ14

DDR3B_DQ10

DDR3B_DQS_N1

DDR3B_DQ7

DDR3B_DQ12

DDR3B_DQ9

DDR3B_DM0

DDR3B_DQ2

DDR3B_DQ62

DDR3B_DQ59DDR3B_DQ61DDR3B_DQ56

DDR3B_DQ60

DDR3B_DQS_P7

DDR3B_DM7

DDR3B_DQ50

DDR3B_DQ63

DDR3B_DQ58

DDR3B_DQS_N7

DDR3B_DQ55

DDR3B_DQ52DDR3B_DQ51DDR3B_DQ49

DDR3B_DQ53

DDR3B_DQ48

DDR3B_DQ54DDR3B_DM6

DDR3B_DQS_P6DDR3B_DQS_N6

DDR3B_DQS_P4DDR3B_DQS_N4

DDR3B_DQS_P5DDR3B_DQS_N5

DDR3B_DQ37

DDR3B_DQ39DDR3B_DQ36DDR3B_DQ38

DDR3B_DM4

DDR3B_DQ33

DDR3B_DQ34DDR3B_DQ32

DDR3B_DQ41

DDR3B_DQ46DDR3B_DQ43DDR3B_DQ47

DDR3B_DQ44

DDR3B_DQ45

DDR3B_DQ40DDR3B_DM5

DDR3B_DQ35

DDR3B_DQ42

DDR3B_DQ57

SDI_CLK148_DN

SDI_CLK148_UP

DDR3B_CKE

MAX_OEn

DDR3B_A9

MAX_WEn

FM_A26

FLASH_ADVnDDR3B_A8

FM_D[15:0]10,14,15

FM_A[26:1]10,14,15

MAX_CSn 15MAX_WEn 15

MAX_OEn 15

FLASH_ADVn 14,15

DDR3B_CASn 13DDR3B_CKE 13

DDR3B_CSn 9,13

DDR3B_DQ[63:0]9,13

DDR3B_ODT 13

DDR3B_WEn 13DDR3B_RASn 13

DDR3B_DM[7:0]9,13

DDR3B_DQS_N[7:0]13

DDR3B_DQS_P[7:0]13

DDR3B_BA[2:0]13

DDR3B_RESETn 13

DDR3B_A[13:0]9,13

SDI_CLK148_UP 8SDI_CLK148_DN 8

DDR3B_CLK_P 13DDR3B_CLK_N 13

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B5 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B5 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B5 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Bank 5A

Bank 5B

Cyclone V GT Bank 5

DQ6R pins at Clocksection

5CGTFD9E5F35

U13C

Version = 0.2 Preliminary

DIFFIO_RX_R17nAA28DIFFIO_RX_R17pAA27

DIFFIO_TX_R22pAL32

DQ1R/DIFFIO_RX_R4pAB24

DQ1R/RZQ_1/DIFFIO_TX_R1pAD24

DQ1R/DIFFIO_TX_R7pAC28 DQ1R/DIFFIO_RX_R4nAB23

DQ1R/DIFFIO_RX_R8nY25 DQ1R/DIFFIO_RX_R8pY24

DQ2R/DIFFIO_TX_R10nAF26 DQ2R/DIFFIO_TX_R10pAF27

DQ2R/DIFFIO_RX_R15pAB30 DQ2R/DIFFIO_TX_R14nAH28

DQ2R/DIFFIO_RX_R15nAA30

DQ2R/DIFFIO_TX_R16pAG29

DQSn2R/DIFFIO_RX_R13nY22 DQS2R/DIFFIO_RX_R13p

AA23

DQ3R/DIFFIO_TX_R18nAJ30DQ3R/DIFFIO_TX_R18pAK30

DQ3R/DIFFIO_RX_R23pAH31DQ3R/DIFFIO_TX_R22nAK32

DQ3R/DIFFIO_RX_R23nAJ31

DQ3R/DIFFIO_TX_R24pAL33

DQSn3R/DIFFIO_RX_R21nW24DQS3R/DIFFIO_RX_R21pY23

DIFFIO_TX_R7nAC29

DIFFIO_TX_R24nAK33

DQ2R/DIFFIO_RX_R11pAB28

DQ2R/DIFFIO_RX_R11nAB29 DQ3R/DIFFIO_RX_R19p

AG30

DQ3R/DIFFIO_RX_R19nAF30

DIFFIO_RX_R9pAB25

DIFFIO_TX_R14pAG28

DQ2R/DIFFIO_TX_R12pAE28

DQ2R/DIFFIO_TX_R12nAF28 DQ3R/DIFFIO_TX_R20p

AN33

DQ3R/DIFFIO_TX_R20nAM33

DIFFIO_RX_R9nAA25

DIFFIO_TX_R16nAH29

DQ4R/DIFFIO_TX_R26nAD30 DQ4R/DIFFIO_TX_R26pAE30

DQ4R/DIFFIO_TX_R28pAH32

DQ4R/DIFFIO_RX_R27pY28

DQ4R/DIFFIO_RX_R31pAC31 DQ4R/DIFFIO_TX_R30nAF31 DQ4R/DIFFIO_TX_R28nAJ32

DQ4R/DIFFIO_RX_R27nY27

DQ6R/DIFFIO_TX_R42nAH34DQ6R/DIFFIO_TX_R42pAG34

DQ6R/DIFFIO_RX_R43nAC34DQ6R/DIFFIO_RX_R43pAC33

DQ6R/DIFFIO_RX_R47pW32DQ6R/DIFFIO_TX_R46nAD34

DQ6R/DIFFIO_RX_R47nV32

DQ6R/DIFFIO_TX_R48pAB33

DQ4R/DIFFIO_TX_R32pAN34

DQS4R/DIFFIO_RX_R29pY29

DIFFIO_TX_R40nAF32

DQ4R/DIFFIO_RX_R31nAC32

DQSn4R/DIFFIO_RX_R29nY30

DIFFIO_RX_R25pAA32

DQ5R/DIFFIO_TX_R34nAB31

DQ5R/DIFFIO_TX_R40pAE32 DQ5R/DIFFIO_RX_R39n

V31

DQ5R/DIFFIO_RX_R35pAK34

DQ5R/DIFFIO_TX_R36pAH33 DQ5R/DIFFIO_RX_R35nAJ34

DQ5R/DIFFIO_TX_R36nAG33

DQ5R/DIFFIO_TX_R34pAA31

DIFFIO_TX_R30pAG31DIFFIO_RX_R25nY32

DIFFIO_TX_R38pAD31DIFFIO_TX_R32nAM34

DIFFIO_TX_R48nAB34DIFFIO_TX_R46pAE34

DQ5R/DIFFIO_TX_R38nAD32

DQSn5R/DIFFIO_RX_R37nW30

DQ5R/DIFFIO_RX_R39pW31

DQS5R/DIFFIO_RX_R37pW29

DQS6R/DIFFIO_RX_R45pV24

DQSn6R/DIFFIO_RX_R45nV23

Bank 6ACyclone V GT Bank 6

DQ7R pins at Clocksection

5CGTFD9E5F35

U13D

Version = 0.2 Preliminary

DQS8R/DIFFIO_RX_R61pU23

DQ8R/DIFFIO_RX_R63nN34

DQ8R/DIFFIO_TX_R62nJ34

DQSn8R/DIFFIO_RX_R61nT23

DQ7R/DIFFIO_TX_R50nAA33 DQ7R/DIFFIO_TX_R50p

Y33

DQ7R/DIFFIO_RX_R51nU29 DQ7R/DIFFIO_RX_R51pU28

DQ7R/DIFFIO_RX_R55nP34

DQS7R/DIFFIO_RX_R53pU24

DQSn7R/DIFFIO_RX_R53nU25

DQ7R/DIFFIO_TX_R54nV34

DQ8R/DIFFIO_RX_R59pT27

DQ8R/DIFFIO_RX_R63pN33

DQ8R/DIFFIO_TX_R58pT33

DQ8R/DIFFIO_TX_R58nT32

DQ10R/DIFFIO_TX_R76nH32

DQ10R/DIFFIO_RX_R75nK30

DQ10R/DIFFIO_TX_R76pJ32

DQ10R/DIFFIO_RX_R75pL30

DQ10R/DIFFIO_RX_R79pN28DQ10R/DIFFIO_TX_R78nH31

DQ10R/DIFFIO_RX_R79nM28

DQ10R/DIFFIO_TX_R80pP30

DQ11R/DIFFIO_RX_R83nM30

DQ11R/DIFFIO_TX_R84pJ30

DQ11R/DIFFIO_RX_R83pM29

DQS10R/DIFFIO_RX_R77pR23

DQ11R/DIFFIO_TX_R86nH28DQ11R/DIFFIO_TX_R84nJ29

DQ11R/DIFFIO_TX_R88pK29

DQ11R/DIFFIO_RX_R87pL28

DQ7R/DIFFIO_RX_R55pR34

DQ8R/DIFFIO_RX_R59nT28

DQ8R/DIFFIO_TX_R64pL33 DQ11R/DIFFIO_RX_R87n

L27

DQ11R/DIFFIO_TX_R82pG31

DQS11R/DIFFIO_RX_R85pP24

DIFFIO_TX_R88nK28

DQ7R/DIFFIO_TX_R56pU34

DQ8R/DIFFIO_TX_R60nM33 DQ8R/DIFFIO_TX_R60pM34

DQSn10R/DIFFIO_RX_R77nR24

DQ11R/DIFFIO_TX_R82nG30

DQSn11R/DIFFIO_RX_R85nP25

DIFFIO_TX_R86pH29

DQ9R/DIFFIO_TX_R66pK33

DQ9R/DIFFIO_TX_R66nK32

DQ9R/DIFFIO_TX_R70nN31 DQ9R/DIFFIO_TX_R68nH33

DQ9R/DIFFIO_RX_R67nR28

DQ9R/DIFFIO_TX_R68pH34

DQ9R/DIFFIO_TX_R72pG34

DQ9R/DIFFIO_RX_R71pP32

DQS9R/DIFFIO_RX_R69pT25

DQ9R/DIFFIO_RX_R71nP31

DQSn9R/DIFFIO_RX_R69nR25

DIFFIO_RX_R65pR32DIFFIO_TX_R64nL32DIFFIO_TX_R62pK34DIFFIO_TX_R56nU33

DIFFIO_TX_R70pN32DIFFIO_RX_R65nR33

DIFFIO_RX_R73pR30DIFFIO_TX_R72nG33

DQ9R/DIFFIO_RX_R67pR27

DQ10R/DIFFIO_TX_R74nL31

DIFFIO_RX_R73nR29

DIFFIO_TX_R80nN29

DQ10R/DIFFIO_TX_R74pM31

DIFFIO_TX_R78pJ31

DIFFIO_TX_R54pV33

DIFFIO_RX_R81pP27

DIFFIO_RX_R81nN27

Page 6: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

VCCIO = Varies (Default = 2.5V)

Cyclone V GT Banks 7 and 8

HSMC PORT A INTERFACEVCCIO = 2.5V

USER I/O INTERFACES

HSMC PORT B INTERFACE

HSMA_RX_D_N10HSMA_RX_D_P10

HSMA_TX_D_P6

HSMA_TX_D_P11

HSMA_RX_D_P5HSMA_RX_D_N5

HSMA_SDA

HSMA_PRSNTn

HSMA_D2

HSMA_D3

HSMA_D1

HSMA_D0

HSMB_A13HSMB_A14HSMB_A15HSMB_A8

HSMB_ADDR_CMD0

HSMB_PRSNTnHSMB_BA3

HSMB_DQS_P0HSMB_DQS_N0

HSMB_DQS_P1HSMB_DQS_N1

HSMB_DQS_P2HSMB_DQS_N2

HSMB_DQS_P3HSMB_DQS_N3

HSMB_A9HSMB_CASnHSMB_RASnHSMB_WEn

HSMB_A11

HSMB_BA2HSMB_A10HSMB_A3HSMB_A4HSMB_A5HSMB_A7HSMB_BA0HSMB_BA1HSMB_A1HSMB_A2

HSMB_DQ1HSMB_DQ2HSMB_DQ3HSMB_DQ4HSMB_DQ5HSMB_DQ6HSMB_DQ7HSMB_A0HSMB_DQ0

HSMB_DQ11HSMB_DQ12HSMB_DQ13HSMB_DQ14HSMB_DQ15HSMB_DQ8HSMB_DQ9

HSMB_DQ10

RZQIN_HSMB_VAR

HSMB_DQ17HSMB_DQ18HSMB_DQ19HSMB_DQ20HSMB_DQ21HSMB_DQ22HSMB_DQ23

HSMB_DQ16

HSMB_DM3HSMB_DQ24HSMB_DQ25HSMB_DQ27HSMB_DQ26HSMB_DQ28HSMB_CLK_OUT_N2HSMB_DQ30

HSMB_DQ31

HSMB_CSnHSMB_A12HSMB_A6HSMB_RX_LEDHSMB_CLK_OUT_P1HSMB_CLK_OUT_N1HSMB_SCL

HSMB_SDA

HSMB_DM2HSMB_DM1HSMB_DM0

HSMB_C_NHSMB_CKE

HSMA_TX_D_N11HSMA_TX_D_N1HSMA_RX_D_P8HSMA_RX_D_N8HSMA_TX_D_P5

HSMA_TX_D_P9

HSMA_RX_D_P15HSMA_RX_D_N15

HSMA_RX_D_P3HSMA_RX_D_N3

HSMA_TX_D_P2HSMA_TX_D_N2HSMA_RX_D_P12HSMA_RX_D_N12HSMA_TX_D_P4HSMA_TX_D_N4HSMA_TX_D_N13HSMA_RX_D_P7HSMA_RX_D_N7

HSMA_RX_D_P0HSMA_RX_D_N0

HSMA_TX_D_P15HSMA_RX_D_P13HSMA_RX_D_N13

HSMA_TX_D_P8HSMA_TX_D_N8HSMA_RX_D_P11HSMA_RX_D_N11HSMA_TX_D_P7HSMA_TX_D_N7HSMA_TX_LEDHSMA_SCLHSMA_RX_LEDHSMA_CLK_OUT_P1

HSMA_RX_D_P16HSMA_RX_D_N16HSMA_TX_D_P10HSMA_TX_D_N10HSMA_TX_D_P12HSMA_TX_D_N12HSMA_RX_D_P14HSMA_RX_D_N14HSMA_TX_D_P3HSMA_TX_D_N3

HSMA_RX_D_N4HSMA_RX_D_P4

HSMA_RX_D_P9HSMA_RX_D_N9HSMA_TX_D_P1HSMA_RX_D_P6HSMA_RX_D_N6HSMA_RX_D_P2HSMA_RX_D_N2HSMA_CLK_OUT_N1

HSMA_TX_D_N15HSMA_TX_D_N9

HSMA_RX_D_P1HSMA_RX_D_N1

HSMA_TX_D_N5HSMA_TX_D_P13

USER_DIPSW1

HSMA_CLK_OUT0USER_DIPSW2

USER_DIPSW4USER_DIPSW3USER_DIPSW5USER_DIPSW0HSMA_CLK_IN0

HSMA_TX_D_P14HSMA_TX_D_N14

HSMA_TX_D_N6

HSMB_TX_LEDUSER_DIPSW7USER_DIPSW6

HSMB_CLK_OUT_P2

HSMB_CLK_IN_P1HSMB_CLK_IN_N1

HSMB_CLK_OUT0

HSMB_C_P

HSMB_CLK_IN0

HSMA_TX_D_N0

HSMA_TX_D_P0

HSMA_TX_D_P16HSMA_TX_D_N16

HSMB_DQ29

HSMA_CLK_OUT0 18

HSMA_RX_LED 20HSMA_PRSNTn 6,15,18,20

HSMA_TX_LED 20

HSMA_CLK_OUT_N[2:1]9,18

HSMA_CLK_OUT_P[2:1]9,18

HSMA_TX_D_P[16:0]18

HSMA_TX_D_N[16:0]18

HSMA_RX_D_P[16:0] 18HSMA_RX_D_N[16:0]

18

HSMA_SDA 18HSMA_SCL 18

HSMA_D[3:0] 18

USER_DIPSW[7:0]20

HSMB_SDA 18HSMB_SCL 18

HSMB_C_P 18

HSMB_ADDR_CMD0 18HSMB_C_N 18

HSMB_DQ[31:0]18

HSMB_A[15:0]18

HSMB_BA[3:0]18

HSMB_DM[3:0]18

HSMB_CASn 18

HSMB_CLK_OUT0 18

HSMB_CLK_OUT_N[2:1]18

HSMB_CLK_OUT_P[2:1]18

HSMB_RASn 18

HSMB_WEn 18

HSMB_CLK_IN_N[2:1]9,18

HSMB_CLK_IN_P[2:1]9,18

HSMB_CLK_IN0 18

HSMB_DQS_P[3:0]18

HSMB_DQS_N[3:0]18

HSMB_CKE 18HSMB_CSn 18

HSMB_RX_LED 20HSMB_TX_LED 20

HSMA_PRSNTn 6,15,18,20

HSMB_PRSNTn 15,18,20

HSMA_CLK_IN0 18

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B6 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B6 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B6 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Bank 7ACyclone V GT Bank 7

5CGTFD9E5F35

U13E

Version = 0.2 Preliminary

DQ1T/DIFFIO_RX_T3pG25DQ1T/DIFFIO_TX_T2nH26

DQ1T/DIFFIO_RX_T3nF25

DQ1T/DIFFIO_TX_T4pG28

HMC_T_DQ_1/DQ6T/DIFFIO_RX_T47pB20 HMC_T_DQ_0/DQ6T/DIFFIO_RX_T47nB19

HMC_T_DQ_3/DQ6T/DIFFIO_TX_T46nD19 HMC_T_DQ_2/DQ6T/DIFFIO_TX_T48pA21

HMC_T_DQ_5/DQ6T/DIFFIO_RX_T43pC21 HMC_T_DQ_4/DQ6T/DIFFIO_RX_T43nB21

HMC_T_DQ_7/DQ6T/DIFFIO_TX_T42nB24 HMC_T_DQ_6/DQ6T/DIFFIO_TX_T44pA23

HMC_T_DQ_9/DQ5T/DIFFIO_RX_T39pE20 HMC_T_DQ_8/DQ5T/DIFFIO_RX_T39nD20

HMC_T_DQ_11/DQ5T/DIFFIO_TX_T38nD21 HMC_T_DQ_10/DQ5T/DIFFIO_TX_T40pA26

HMC_T_DQ_13/DQ5T/DIFFIO_RX_T35pD22 HMC_T_DQ_12/DQ5T/DIFFIO_RX_T35nC23

HMC_T_DQ_15/DQ5T/DIFFIO_TX_T34nA27 HMC_T_DQ_14/DQ5T/DIFFIO_TX_T36pB26

HMC_T_DQ_36/DQ2T/DIFFIO_RX_T11nD29HMC_T_DQ_35/DQ2T/DIFFIO_TX_T14nE28

HMC_T_DQ_38/DQ2T/DIFFIO_TX_T12pC32HMC_T_DQ_37/DQ2T/DIFFIO_RX_T11pD30

HMC_T_DM_4/DQ2T/DIFFIO_TX_T10pF27HMC_T_DQ_39/DQ2T/DIFFIO_TX_T10nF28

HMC_T_DQSn_4/DQSn2T/DIFFIO_RX_T13nK23HMC_T_DQS_4/DQS2T/DIFFIO_RX_T13pL23

HMC_T_ODT_1/DQ6T/DIFFIO_TX_T44nA22

HMC_T_DQS_0/DQS6T/DIFFIO_RX_T45pM18

HMC_T_CKE_0/DQ5T/DIFFIO_TX_T36nB25

HMC_T_DQS_1/DQS5T/DIFFIO_RX_T37pM20

HMC_T_ODT_0/DIFFIO_TX_T46pE19

HMC_T_RESETn/DIFFIO_TX_T30pD25

HMC_T_DM_0/DQ6T/DIFFIO_TX_T42pB23

HMC_T_DQSn_0/DQSn6T/DIFFIO_RX_T45nL18

HMC_T_DM_1/DQ5T/DIFFIO_TX_T34pA28

HMC_T_DQSn_1/DQSn5T/DIFFIO_RX_T37nM19

HMC_T_CKE_1/DIFFIO_TX_T38pC22

DQ1T/DIFFIO_TX_T2pH27

HMC_GND/DIFFIO_RX_T17nK22

HMC_GND/DIFFIO_RX_T9pM25

HMC_GND/DIFFIO_RX_T25nL20

HMC_GND/DIFFIO_TX_T22pE27

HMC_T_DQ_17/DQ4T/DIFFIO_RX_T31pF20 HMC_T_DQ_16/DQ4T/DIFFIO_RX_T31nG20

HMC_T_DQ_19/DQ4T/DIFFIO_TX_T30nC26 HMC_T_DQ_18/DQ4T/DIFFIO_TX_T32pD24

HMC_T_DQ_21/DQ4T/DIFFIO_RX_T27pF21 HMC_T_DQ_20/DQ4T/DIFFIO_RX_T27nG21

HMC_T_DQ_23/DQ4T/DIFFIO_TX_T26nE23 HMC_T_DQ_22/DQ4T/DIFFIO_TX_T28pD27

HMC_GND/DIFFIO_RX_T25pL21

HMC_GND/DIFFIO_RX_T9nL25

DQSn1T/DIFFIO_RX_T5nN24DQS1T/DIFFIO_RX_T5pM24

HMC_GND/DIFFIO_TX_T16nB30

HMC_T_DM_2/DQ4T/DIFFIO_TX_T26pE22

HMC_T_DQSn_2/DQSn4T/DIFFIO_RX_T29nM21

HMC_GND/DIFFIO_TX_T14pE29

HMC_GND/DIFFIO_TX_T32nC24

HMC_T_DQS_2/DQS4T/DIFFIO_RX_T29pN22

HMC_T_DQ_24/DQ3T/DIFFIO_RX_T23nH21

HMC_GND/DIFFIO_RX_T17pL22

HMC_GND/DIFFIO_TX_T40nA25

HMC_GND/DIFFIO_TX_T24nB29

DIFFIO_RX_T1nJ25

HMC_GND/DQ3T/DIFFIO_TX_T20nC28

HMC_T_DQ_26/DQ3T/DIFFIO_TX_T24pB28 HMC_T_DQ_25/DQ3T/DIFFIO_RX_T23pH22

HMC_T_DQ_28/DQ3T/DIFFIO_RX_T19nF22 HMC_T_DQ_27/DQ3T/DIFFIO_TX_T22nD26

HMC_T_DQ_30/DQ3T/DIFFIO_TX_T20pC29 HMC_T_DQ_29/DQ3T/DIFFIO_RX_T19pF23

HMC_T_DM_3/DQ3T/DIFFIO_TX_T18pE24 HMC_T_DQ_31/DQ3T/DIFFIO_TX_T18nE25

HMC_GND/DQ2T/DIFFIO_TX_T12nC31

HMC_GND/DQ4T/DIFFIO_TX_T28nC27

DIFFIO_TX_T6pF26

RZQ_2/DIFFIO_TX_T48nA20

HMC_T_DQS_3/DQS3T/DIFFIO_RX_T21pM23

HMC_T_DQ_32/DQ2T/DIFFIO_RX_T15nG23

DIFFIO_RX_T1pK25

HMC_T_DQSn_3/DQSn3T/DIFFIO_RX_T21nN23

HMC_T_DQ_33/DQ2T/DIFFIO_RX_T15pH23

DIFFIO_TX_T8nE30

HMC_T_DQ_34/DQ2T/DIFFIO_TX_T16pB31

DQ1T/DIFFIO_TX_T6nG26

DQ1T/DIFFIO_RX_T7pG24

DQ1T/DIFFIO_TX_T4nG29

DQ1T/DIFFIO_TX_T8pF30DQ1T/DIFFIO_RX_T7nH24

Bank 8ACyclone V GT Bank 8

HMC

HMC_T_A_2, 3 at Clocksection

5CGTFD9E5F35

U13F

Version = 0.2 Preliminary

DQ9T/DIFFIO_TX_T72pC13

DQ9T/DIFFIO_TX_T68pC11

DQ9T/DIFFIO_RX_T71pE15

DQ9T/DIFFIO_RX_T71nD15

DQ9T/DIFFIO_RX_T67nA8 DQ9T/DIFFIO_RX_T67pB8

DQ9T/DIFFIO_TX_T70nB9

DQ11T/DIFFIO_RX_T83pG13

DQ11T/DIFFIO_TX_T88pC1

DQ11T/DIFFIO_TX_T82pD11

DQ11T/DIFFIO_RX_T87nD12

DQ11T/DIFFIO_TX_T86nB3

DQ11T/DIFFIO_TX_T82nD10

DQ11T/DIFFIO_RX_T87pE12

DQ11T/DIFFIO_TX_T84pC8

DQ10T/DIFFIO_RX_T79nG14

DQ12T/DIFFIO_RX_T91nF11DQ10T/DIFFIO_RX_T75p

E14

DQ10T/DIFFIO_RX_T75nD14 DQ12T/DIFFIO_RX_T91p

F12

DQ10T/DIFFIO_RX_T79pH14

DQ12T/DIFFIO_RX_T95nG11

DQ9T/DIFFIO_TX_T66nA6 DQ9T/DIFFIO_TX_T66pA7

DQ11T/DIFFIO_RX_T83nH13

DQS11T/DIFFIO_RX_T85pN13

DQ9T/DIFFIO_TX_T68nB11

DQ11T/DIFFIO_TX_T84nC7

DQS9T/DIFFIO_RX_T69pL16

DQSn9T/DIFFIO_RX_T69nL15

DQ12T/DIFFIO_TX_T90pF10

DQSn11T/DIFFIO_RX_T85nN12

HMC_T_A_1/DQ7T/DIFFIO_TX_T50nC17 HMC_T_A_0/DQ7T/DIFFIO_TX_T50pC18

HMC_T_A_11/DQ8T/DIFFIO_TX_T60nA13HMC_T_A_10/DQ8T/DIFFIO_TX_T60pB13

HMC_T_A_14/DQ8T/DIFFIO_RX_T63pD17HMC_T_A_13/DQ8T/DIFFIO_TX_T62nB14HMC_T_A_12/DIFFIO_TX_T62pC14

DIFFIO_TX_T70pC9

DIFFIO_RX_T89nK13

DIFFIO_RX_T73pJ15

DIFFIO_RX_T81pM13

DIFFIO_RX_T89pL12

DIFFIO_RX_T65nG15

DIFFIO_RX_T73nK14

DIFFIO_RX_T81nL13

HMC_T_A_15/DQ8T/DIFFIO_RX_T63nD16

HMC_T_A_5/DQ7T/DIFFIO_RX_T51nE17

DIFFIO_TX_T88nB1

HMC_T_A_7/DQ7T/DIFFIO_TX_T54nA16

HMC_T_A_4/DQ7T/DIFFIO_RX_T51pE18

HMC_T_A_6/DIFFIO_TX_T54pA17

DIFFIO_RX_T65pF15

HMC_T_A_8/DQ8T/DIFFIO_RX_T59pF17

DIFFIO_TX_T96nE8

HMC_T_WEn/DQ8T/DIFFIO_TX_T64pB10

DIFFIO_TX_T86pA2

HMC_GND/DIFFIO_TX_T56nA15

HMC_GND/DIFFIO_TX_T64nA10

DIFFIO_TX_T80nA3

DIFFIO_TX_T94pE7

HMC_T_RASn/DQ8T/DIFFIO_TX_T58nA11

HMC_T_CKn/DQSn7T/DIFFIO_RX_T53nL17 HMC_T_CSn_0/DQS8T/DIFFIO_RX_T61p

M15

HMC_T_BA_2/DQ7T/DIFFIO_RX_T55nB16

HMC_T_BA_0/DQ7T/DIFFIO_TX_T56pB15

HMC_T_BA_1/DQ7T/DIFFIO_RX_T55pC16

HMC_T_CK/DQS7T/DIFFIO_RX_T53pM16

HMC_T_CASn/DQ8T/DIFFIO_TX_T58pA12

HMC_T_A_9/DQ8T/DIFFIO_RX_T59nF16

HMC_T_CSn_1/DQSn8T/DIFFIO_RX_T61nM14

DIFFIO_TX_T78pF13DIFFIO_TX_T72nC12

DQ10T/DIFFIO_TX_T74nA5

DQ10T/DIFFIO_TX_T76pC6

DQ10T/DIFFIO_TX_T76nB6

DQ10T/DIFFIO_TX_T74pB5

DQS10T/DIFFIO_RX_T77pP14

DQSn10T/DIFFIO_RX_T77nN14

DQ12T/DIFFIO_TX_T92nD9DQ12T/DIFFIO_TX_T92pE9

DQ12T/DIFFIO_RX_T95pH12

DQ12T/DIFFIO_TX_T90nE10

DQS12T/DIFFIO_RX_T93pL11

DQSn12T/DIFFIO_RX_T93nK12

DQ12T/DIFFIO_TX_T94nD7

DQ12T/DIFFIO_TX_T96pF8

DQ10T/DIFFIO_TX_T80pB4

DQ10T/DIFFIO_TX_T78nE13

R195100, 1%

Page 7: Cyclone V GT Development Kit Board

8

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1

1

E E

D D

C C

B B

A A

Cyclone V GT Transceivers and Power

RREF_TL

XCVR_TX_N3XCVR_TX_P3XCVR_RX_P3

XCVR_RX_N3

C5_VCCE_GXBLC5_VCCL_GXBL

C5_2.5V

PCIE_TX_N0 3

PCIE_TX_N1 3PCIE_TX_P1 3

PCIE_TX_N2 3PCIE_TX_P2 3

PCIE_TX_N3 3PCIE_TX_P3 3

PCIE_TX_P0 3PCIE_RX_N03

PCIE_RX_N13PCIE_RX_P13

PCIE_RX_N23PCIE_RX_P23

PCIE_RX_N33PCIE_RX_P33

PCIE_RX_P03

HSMB_TX_P0 18HSMB_TX_N0 18

HSMB_TX_P3 18HSMB_TX_N3 18

HSMB_TX_P1 18HSMB_TX_N1 18

HSMB_TX_N2 18HSMB_TX_P2 18

HSMB_RX_P318HSMB_RX_N318

HSMB_RX_N218HSMB_RX_P218

HSMB_RX_P018HSMB_RX_N018

HSMB_RX_P118HSMB_RX_N118

REFCLK_QL3_P8REFCLK_QL3_N8

REFCLK_QL2_P8REFCLK_QL2_N8

HSMA_RX_P318HSMA_RX_N318

HSMA_RX_N218HSMA_RX_P218

HSMA_TX_P3 18HSMA_TX_N3 18

HSMA_TX_N2 18HSMA_TX_P2 18

SDI_A_TX_P 16SDI_A_TX_N 16

SDI_A_RX_P16SDI_A_RX_N16

HSMA_RX_P018HSMA_RX_N018HSMA_RX_P118HSMA_RX_N118

HSMA_TX_P0 18HSMA_TX_N0 18HSMA_TX_P1 18HSMA_TX_N1 18

PCIE_REFCLK_P3PCIE_REFCLK_N3

REFCLK_QL1_P8REFCLK_QL1_N8

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B7 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B7 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B7 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R205 2.00K

R51 DNIR410R46DNI

R47 0R48 0

Cyclone V GT Transceivers

Bank QL2

Bank QL1

Bank QL0

Bank QL3

U13M

5CGTFD9E5F35Version = 0.2 Preliminary

GXB_TX_L0pAH4

GXB_TX_L1pAF4

GXB_TX_L3pAB4

GXB_TX_L4pY4

GXB_RX_L8p,GXB_REFCLK_L8pN2

GXB_TX_L6pT4

GXB_TX_L0nAH3

GXB_TX_L1nAF3

GXB_TX_L3nAB3

GXB_TX_L4nY3

GXB_RX_L8n,GXB_REFCLK_L8nN1

GXB_TX_L6nT3

GXB_RX_L0p,GXB_REFCLK_L0pAJ2

GXB_RX_L1p,GXB_REFCLK_L1pAG2

GXB_RX_L2p,GXB_REFCLK_L2pAE2

REFCLK0LpAA11

GXB_TX_L2nAD3

GXB_RX_L3n,GXB_REFCLK_L3nAC1

GXB_RX_L4n,GXB_REFCLK_L4nAA1

GXB_RX_L5n,GXB_REFCLK_L5nW1

GXB_RX_L0n,GXB_REFCLK_L0nAJ1

GXB_RX_L1n,GXB_REFCLK_L1nAG1

GXB_RX_L2n,GXB_REFCLK_L2nAE1

REFCLK0LnAB10

GXB_TX_L2pAD4

GXB_RX_L3p,GXB_REFCLK_L3pAC2

GXB_RX_L4p,GXB_REFCLK_L4pAA2

GXB_RX_L5p,GXB_REFCLK_L5pW2

GXB_RX_L7p,GXB_REFCLK_L7pR2

REFCLK1LnV10

GXB_TX_L5pV4

GXB_RX_L6n,GXB_REFCLK_L6nU1

REFCLK1LpW11

GXB_RX_L7n,GXB_REFCLK_L7nR1

GXB_RX_L6p,GXB_REFCLK_L6pU2

GXB_TX_L5nV3

GXB_TX_L7nP3

GXB_TX_L8nM3

REFCLK2LnT10

GXB_RX_L10n,GXB_REFCLK_L10nJ1

GXB_TX_L10nH3

GXB_TX_L11nF3

GXB_TX_L9nK3

REFCLK3LnP10

GXB_TX_L7pP4

GXB_TX_L8pM4

REFCLK2LpU11

GXB_RX_L10p,GXB_REFCLK_L10pJ2

GXB_TX_L10pH4

GXB_TX_L11pF4

GXB_TX_L9pK4

REFCLK3LpR11

GXB_RX_L11n,GXB_REFCLK_L11nG1 GXB_RX_L11p,GXB_REFCLK_L11pG2

GXB_RX_L9p,GXB_REFCLK_L9pL2

GXB_RX_L9n,GXB_REFCLK_L9nL1

RREF_TLE1

R50 DNI R45DNI

Cyclone V GT Transceiver Power

1.2V

Transceiver Power

Transceiver High Voltage Power

2.5V

Transceiver Clock Power

1.2V

U13N

5CGTFD9E5F35Version = 0.2 Preliminary

VCCE_GXBLAD8

VCCH_GXBLW9 VCCH_GXBL

AB8

VCCE_GXBLP8

VCCE_GXBLAA9 VCCE_GXBLAC9

VCCH_GXBLN9

VCCE_GXBLU9

VCCE_GXBLM8 VCCE_GXBLR9

VCCE_GXBLV8 VCCE_GXBLY8

VCCL_GXBLR7VCCL_GXBLU7VCCL_GXBLW7

VCCL_GXBLN7

VCCH_GXBLT8

VCCL_GXBLAA7VCCL_GXBLAC7

R420

Page 8: Cyclone V GT Development Kit Board

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4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Si570 Programmable OscillatorUse Clock Control GUI(Default 100MHz)I2C Address 00 HEX

Clocks/Oscillators

CLK_SEL = HIGH selects (CLK1p/n) Si570 inputCLK_SEL = LOW selects (CLK2p/n) SMA input

Si571 Programmable OscillatorUse Clock Control GUI(Default 148.5MHz)I2C Address 55 HEX

From FPGA

100M_OSC_N

CLKIN_SMA_CN

100M_OSC_P

CLKIN_SMA_N

CLKIN_SMA_CPCLKIN_SMA_CN

CLKIN_SMA_P

CLOCK_SDACLOCK_SCL

REFCLK_QL1_CP

REFCLK_QL3_CNREFCLK_QL3_CP

REFCLK_QL1_CNPDn

GLBUFFER_EN

CLKIN_SMA_CP

Si570_EN

REFCLK_QL2_CP

REFCLK_QL2_CN

SI571_VCONTROL

CLOCK_SCL

CLOCK_SDA

SMA_CLKOUT_PSMA_CLKOUT_N

2.5V

3.3V

2.5V 2.5V

2.5V

2.5V

1.8V

2.5V

2.5V

1.8V

1.8V

1.8V

2.5V

2.5V

CLOCK_SCL15

CLOCK_SDA15

SI570_EN15

REFCLK_QL1_P 7REFCLK_QL1_N 7

REFCLK_QL3_P 7REFCLK_QL3_N 7

CLKINTOP_P 9CLKINTOP_N 9

CLKINBOT_P 9CLKINBOT_N 9

CLK_SEL15,20

CLKIN_R_P 9CLKIN_R_N 9

CLKIN_50 9

SDI_CLK148_DN5SDI_CLK148_UP5

SI571_EN15

REFCLK_QL2_N 7

REFCLK_QL2_P 7

CLK50_EN15

CLKIN_MAX_50 15

CLK125_EN15 CLK_125M_P 9

CLK_125M_N 9

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B8 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B8 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B8 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C18 0.1uF

C491

0.1uF

C147

0.1uF

C139

1.0nF

C492

10uF

C109

0.1uF

C154 0.1uF

R159 4.99K

C161

0.1uF

X4

SI570

OE2

NC1

GND3

CLK+4

CLK-5

VCC6

SDA7

SCL8

R158 4.99K

C15 0.1uF

R12 100, 1%

R180 4.7K

C160 0.1uF

C19 0.1uF

U52

SL18860DC

CLKIN3 CLKOUT1

8

CLKOUT29

GND1

CLKOUT310

VDD2

OE16

OE_OSC4

OE27

OE35

R242 10.0K

R183 4.70K, 1%

C145

10uF

R24124

R2084.5

R13 4.7K

C265

0.1uF

X5

125.0MHz

EN1

NC2

GND3

OUT4

OUTn5

VCC6

R19124 J3LTI-SASF546-P26-X1

1

2345

C148

10uF

J6

LTI-SASF546-P26-X11

2345

X6

50MHz

VCC4

GND2

OUT3

EN1

R157 4.70K, 1%

C8

2.2uF

C155 0.1uF

C140

0.1uF

X3

SI571

OE2

VC1

GND3

CLK+4

CLK-5

VDD6

SDA7

SCL8

R160

180K

C9

0.1uF

R2584.5

J71

2 3 4 5

C146

0.1uFU3

IDT5T9306

GN

D29

GL8

PDn21

CLK1p6

CLK1n7

CLK2p16

CLK2n15

Gn1

Q4n18Q4p19

Q3n13Q3p12

Q2n11Q2p10

VD

D17

Q1n4Q1p3

Q6p26

Q6n25

Q5n23Q5p24

CLK_SEL28

VD

D14

VDD5 VDD9

VD

D20

VDD2 V

DD

27N

C22

R182 4.70K, 1%

C20 0.1uF

R175 4.70K, 1%

R166 4.7K

J41

2 3 4 5

R324 10K

R22100, 1%R23100, 1%

C159 0.1uF

C319

10uF

C103

2.2uF

Page 9: Cyclone V GT Development Kit Board

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6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

USB INTERFACE

HSMC PORT B INTERFACE

CLOCKS

Cyclone V GT Clocks

DDR3B X64 SMC INTERFACE

VCCIO = 1.5V

VCCIO = 1.5V

VCCIO = VARIES

VCCIO = 1.5V

VCCIO = 1.5V

VCCIO = 2.5V

DDR3A x40 HMC INTERFACE

HSMC PORT A INTERFACE

FLASH INTERFACE

DOES NOT NEED TO BE A CLOCK OUT,CAN BE USED AS I/O.

HSMA_CLK_IN_N2HSMA_CLK_IN_P2

CLKIN_R_NCLKIN_R_PCLKINBOT_P CLKINBOT_N

HSMA_CLK_IN_P1 HSMA_CLK_IN_N1

CLKINTOP_NCLKINTOP_P

HSMA_CLK_IN_P2HSMA_CLK_IN_N2

HSMA_CLK_IN_N1HSMA_CLK_IN_P1

CLKINBOT_PCLKINBOT_N

CLKINTOP_PCLKINTOP_N

CLKIN_R_PCLKIN_R_N

HSMB_CLK_IN_N2HSMB_CLK_IN_P2

CLK_125M_PCLK_125M_N

CLKIN_50

USB_CLK

SMA_CLKOUT

HSMA_CLK_OUT_N2HSMA_CLK_OUT_P2

USB_RDn

USB_RESETnDDR3A_A2DDR3A_A3

FLASH_RDYBSYn

CLK_125M_NCLK_125M_P

DDR3B_A12

DDR3B_CSn

DDR3B_A13

DDR3B_DQ20

DDR3B_DM3MAX_CLK

SMA_CLKOUT

HSMB_CLK_IN_P2 HSMB_CLK_IN_N2

HSMB_CLK_IN_P[2:1]6,18

HSMB_CLK_IN_N[2:1] 6,18

CLKIN_50 8CLKINBOT_P 8CLKINBOT_N 8

USB_CLK 15,19

HSMA_CLK_OUT_N[2:1]6,18

HSMA_CLK_OUT_P[2:1]6,18

CLKINTOP_N 8

CLKIN_R_N 8CLKINTOP_P 8

CLKIN_R_P 8

DDR3A_A[13:0]4,12

USB_RESETn 19USB_RDn 19

FLASH_RDYBSYn 14,15

HSMA_CLK_IN_P[2:1]18

HSMA_CLK_IN_N[2:1]18

DDR3B_CSn 13

DDR3B_DQ[31:0]5,13

DDR3B_A[13:0]5,13

CLK_125M_N 8

CLK_125M_P 8

MAX_CLK 15

DDR3B_DM[7:0]5,13

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B9 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B9 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B9 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

J141

2 3 4 5R223 100, 1%

R251 100, 1%R266 100, 1%

Bank 3BCyclone V GT Clocks

Bank 4A

Bank 5B

Bank 6A

Bank 7A

Bank 8A

5CGTFD9E5F35

U13G

Version = 0.2 Preliminary

CLK1p/DIFFIO_RX_B47pAC18

CLK1n/DIFFIO_RX_B47nAB18

CLK0p/FPLL_BL_FBp/DIFFIO_RX_B39pAD17

CLK0n/FPLL_BL_FBn/DIFFIO_RX_B39nAC17

CLK2p/DIFFIO_RX_B55pAF18

CLK2n/DIFFIO_RX_B55nAG18

CLK3n/DIFFIO_RX_B63nAE20 CLK3p/DIFFIO_RX_B63pAD20

CLK6n/DIFFIO_RX_R41nV27 CLK6p/DIFFIO_RX_R41pV28

DQ6R/FPLL_BR_CLKOUT0/FPLL_BR_CLKOUTp/FPLL_BR_FB/DIFFIO_TX_R44pAF33

DQ6R/FPLL_BR_CLKOUT1/FPLL_BR_CLKOUTn/DIFFIO_TX_R44nAE33

CLK7p/FPLL_BR_FBp/DIFFIO_RX_R33pW26

CLK7n/FPLL_BR_FBn/DIFFIO_RX_R33nW27

CLK4n/FPLL_TR_FBn/DIFFIO_RX_R57nT30 CLK4p/FPLL_TR_FBp/DIFFIO_RX_R57pT31

CLK5n/DIFFIO_RX_R49nU30 CLK5p/DIFFIO_RX_R49pU31

CLK10n/DIFFIO_RX_T41nH18 CLK10p/DIFFIO_RX_T41pH19

CLK11n/DIFFIO_RX_T33nK19 CLK11p/DIFFIO_RX_T33pJ20

CLK8n/FPLL_TL_FBn/DIFFIO_RX_T57nH16 CLK8p/FPLL_TL_FBp/DIFFIO_RX_T57pH17

CLK9n/DIFFIO_RX_T49nF18 CLK9p/DIFFIO_RX_T49pG18 DQ7T/HMC_T_A_3/FPLL_TL_CLKOUT1/FPLL_TL_CLKOUTn/DIFFIO_TX_T52n

A18DQ7T/HMC_T_A_2/FPLL_TL_CLKOUT0/FPLL_TL_CLKOUTp/FPLL_TL_FB/DIFFIO_TX_T52pB18

DQ6B/HMC_B_A_3/FPLL_BL_CLKOUT1/FPLL_BL_CLKOUTn/DIFFIO_TX_B45nAN18DQ6B/HMC_B_A_2/FPLL_BL_CLKOUT0/FPLL_BL_CLKOUTp/FPLL_BL_FB/DIFFIO_TX_B45pAM18

DQ7R/FPLL_TR_CLKOUT1/FPLL_TR_CLKOUTn/DIFFIO_TX_R52nW34DQ7R/FPLL_TR_CLKOUT0/FPLL_TR_CLKOUTp/FPLL_TR_FB/DIFFIO_TX_R52pY34

R217 DNI

R181 100, 1%

R218 DNI

R245 100, 1%

Page 10: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Cyclone V GT Configuration

INSTALL THIS RESISTOR ONLY WHEN FPGA IS NOT POPULATED.

FLASH INTERFACE

FPGA_MSEL1FPGA_MSEL2

FPGA_MSEL3FPGA_MSEL4

FPGA_MSEL0FPGA_MSEL1FPGA_MSEL2

FPGA_MSEL0

FPGA_MSEL3

JTAG_FPGA_TDO JTAG_BLASTER_TDO

FPGA_CONFIG_D8FPGA_CONFIG_D9FPGA_CONFIG_D10FPGA_CONFIG_D11FPGA_CONFIG_D12FPGA_CONFIG_D13

FPGA_DCLK

FPGA_CONFIG_D14FPGA_CONFIG_D15

FPGA_CONFIG_D7

FPGA_CONFIG_D0FPGA_CONFIG_D1FPGA_CONFIG_D2FPGA_CONFIG_D3FPGA_CONFIG_D4FPGA_CONFIG_D5FPGA_CONFIG_D6

FPGA_CEn

FM_A2

FM_D13

FM_D14

FPGA_MSEL4FORCE_FAN

FLASH_CEn

FLASH_CLK

C5_VCCIO_2.5V

2.5V

2.5V

2.5V

2.5V

2.5V

FPGA_PR_READY 15FPGA_PR_ERROR 15

FPGA_PR_REQUEST 15FPGA_CvP_CONFDONE 15

JTAG_BLASTER_TDO11,19JTAG_TCK11,15,18,19JTAG_TMS11,15,19

FPGA_MSEL4 15

FPGA_MSEL2 15FPGA_MSEL3 15

FPGA_MSEL0 15FPGA_MSEL1 15

FPGA_CEn 15FPGA_CONFIG_D[15:0]14,15FPGA_DCLK14,15

FPGA_nCONFIG15 FPGA_CONF_DONE15

FPGA_nSTATUS15

FLASH_CEn 14,15

FM_D[15:0]5,14,15

FM_A[26:1]5,14,15

JTAG_FPGA_TDO11,18

CPU_RESETn15,20

FPGA_PR_DONE 15

FORCE_FAN 15

PCIE_PERSTn 3

FLASH_CLK 14,15

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B10 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B10 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B10 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R97 DNI C97 DNI

R120 1.00kR121 1.00k

R190 DNI

R185 1.00k

R25

4

10K

OPEN

SW5

TDA04H0SB1

1234 5

678

R189 1.00k

R98DNI

R122 10K

R25

6

10K

R355 10K

R186 DNI

R119 1.00k

R25

5

10K

R26

9

10K

R332 10KR331 10K

R187 1.00kR188 DNI

R258 DNI

Cyclone V GT ConfigurationBank 3A

Bank 5A

Bank 9A

5CGTFD9E5F35

U13H

Version = 0.2 Preliminary

DATA15/DQ1B/DIFFIO_TX_B6pAK8

PR_READY/DQ1B/DIFFIO_TX_B8nAK9

PR_DONE/DIFFIO_RX_B7nAC12

MSEL3K10

nPERSTL0/DQS1R/DIFFIO_RX_R6pAA21

nCONFIGG8

PR_REQUEST/DQ1R/DIFFIO_TX_R1nAD25

CvP_CONFDONE/DQ1R/DIFFIO_TX_R3nAC26

nSTATUSG9

PR_ERROR/DIFFIO_RX_B7pAC13

MSEL4H7

DATA10/DQSn1B/DIFFIO_RX_B3nAJ11 DATA9/DQ1B/DIFFIO_TX_B4nAL7

DATA14/DQ1B/DIFFIO_RX_B5nAG13 DATA13/DQ1B/DIFFIO_TX_B6n

AL8

DATA8/DQ1B/DIFFIO_RX_B1pAD12

DATA11/DIFFIO_TX_B4pAK7

AS_DATA2AH8

AS_DATA3AJ6

DATA6/DQ1B/DIFFIO_RX_B1nAD11

DATA7/DQ1B/DIFFIO_TX_B2pAM5

DEV_OE/DIFFIO_TX_R5pAE29

CLKUSR/DQ1B/DIFFIO_RX_B5pAF13

INIT_DONE/DIFFIO_RX_R2pAC23

AS_DATA0/ASDOAH9

AS_DATA1AJ7

DATA4/nCSOAG10

DATA5/DIFFIO_TX_B2nAM4

CRC_ERROR/DIFFIO_RX_R2nAC24DEV_CLRn/DQ1R/DIFFIO_TX_R5n

AD29

DATA12/DQS1B/DIFFIO_RX_B3pAH12

CONF_DONEG10

DCLKAF10

nCEO/DQ1R/DIFFIO_TX_R3pAC27

MSEL2F6MSEL1J11

TMSAG11

TDOAF11

nCEF7

TDIAE10

MSEL0J12

TCKAK5

IO/DQ1B/DIFFIO_TX_B8pAJ9

nPERSTL1/DQSn1R/DIFFIO_RX_R6nAA22

Page 11: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

JTAG

(uses JTAG mode only)USB Blaster Programming Header

TS5A23157 Switch FunctionsWhen Pins 1 & 5 are:LOW --> NC to/from COM = ON and NO to/from COM = OFFHIGH --> NC to/from COM = OFF and NO to/from COM = ON

Logic 0 = pin 10 <--> pin 9 (HSMB Bypass)Logic 1 = pin 10 <--> pin 2 (HSMB Enable)

Logic 0 = pin 6 <--> pin 7 (HSMBBypass)Logic 1 = pin 6 <--> pin 4 (HSMB Enable)

Logic 0 = pin 10 <--> pin 9 (HSMA Bypass)Logic 1 = pin 10 <--> pin 2 (HSMA Enable)

Logic 0 = pin 6 <--> pin 7 (HSMA Bypass)Logic 1 = pin 6 <--> pin 4 (HSMA Enable)

Populate R285 if you would like toMaster the JTAG chain throughHSMC Port A or HSMC Port B

JTAG_BLASTER_TDI

JTAG_TCK

HSMB_JTAG_TDI

JTAG_TMS

JTAG_TMS

HSMA_JTAG_EN

HSMB_JTAG_EN

JTAG_BLASTER_TDO

2.5V2.5V

2.5V

2.5V

2.5V

2.5V

2.5V

JTAG_TCK 10,15,18,19

JTAG_TMS 10,15,19

JTAG_BLASTER_TDO 10,19

HSMB_JTAG_TDO18

HSMB_JTAG_TMS 18

HSMA_JTAG_TMS 18

HSMB_JTAG_TDI 18

HSMA_JTAG_TDO18

USB_DISABLEn19

JTAG_FPGA_TDO 10,18

JTAG_BLASTER_TDI 15,19

JTAG_EPM2210_TDI 15HSMB_JTAG_EN3

HSMA_JTAG_EN3

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B11 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B11 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B11 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R319 1.00kR281 1.00k

U37

TS5A23157

IN11

NO12

GND3

NO24

IN25

COM26

NC27

V+8

NC19

COM110

R117 1.00k

C134 0.1uF

R118 1.00k

R308 DNI

J13

70246-1004

2468

10

13579

U36

TS5A23157

IN11

NO12

GND3

NO24

IN25

COM26

NC27

V+8

NC19

COM110

R293 1.00k

C460 DNI

R285 DNI

R3091.00k

C135 0.1uF

Page 12: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

DDR3A (x40 HMC)Uses Hard Memory Controller

Place These Caps Near DDR3(U26, U27, and U28)

Place one termination resistor atthe end of each branch.

DDR3A_BA1

DDR3A_CLK_P DDR3A_CLK_N

DDR3A_A11DDR3A_A8

DDR3A_A5

DDR3A_A1

DDR3A_A6

DDR3A_A11

DDR3A_A0

DDR3A_A7

DDR3A_A12

DDR3A_A2

DDR3A_A8

DDR3A_A3

DDR3A_A9

DDR3A_A4

DDR3A_A10

DDR3A_A5

DDR3A_A1

DDR3A_A6

DDR3A_A11

DDR3A_A0

DDR3A_A7

DDR3A_A12

DDR3A_A2

DDR3A_A8

DDR3A_A3

DDR3A_A9

DDR3A_A4

DDR3A_A10

DDR3A_CSn

DDR3A_A5

DDR3A_A1

DDR3A_A6

DDR3A_A11

DDR3A_A0

DDR3A_A7

DDR3A_A12

DDR3A_A2

DDR3A_A8

DDR3A_A3

DDR3A_A9

DDR3A_A4

DDR3A_A10

DDR3A_A3DDR3A_A7 DDR3A_A5 DDR3A_A0DDR3A_A9

DDR3A_WEn

DDR3A_ODTDDR3A_BA0

DDR3A_A1

DDR3A_CASnDDR3A_A10

DDR3A_RASn DDR3A_A12DDR3A_A6

DDR3A_A2DDR3A_A13

DDR3A_A4

DDR3A_BA2

DDR3A_DQS_P0

DDR3A_DQ5

DDR3A_DQ11

DDR3A_DQ6

DDR3A_DQ12

DDR3A_DQ0DDR3A_DQ1

DDR3A_DQS_N0

DDR3A_DQ7

DDR3A_DQ13

DDR3A_DQS_P1

DDR3A_DQ2

DDR3A_DQS_N1

DDR3A_DQ8

DDR3A_DQ14

DDR3A_DQ3

DDR3A_DQ9

DDR3A_DQ15

DDR3A_DQ4

DDR3A_DQ10

DDR3A_DQ37

DDR3A_DQS_P4DDR3A_DQS_N4

DDR3A_DQ38

DDR3A_DQ33DDR3A_DQ32

DDR3A_DQ39

DDR3A_DQ34DDR3A_DQ35DDR3A_DQ36 DDR3A_DQ20

DDR3A_DQ26

DDR3A_DQ21

DDR3A_DQ27

DDR3A_DQ22

DDR3A_DQ28

DDR3A_DQ17

DDR3A_DQ23

DDR3A_DQ16

DDR3A_DQ29

DDR3A_DQS_P2DDR3A_DQS_N2

DDR3A_DQ18

DDR3A_DQ24

DDR3A_DQ30

DDR3A_DQS_P3DDR3A_DQS_N3

DDR3A_DQ19

DDR3A_DQ25

DDR3A_DQ31

DDR3A_DM2DDR3A_DM3

DDR3A_ZQ02

DDR3A_BA2DDR3A_BA1DDR3A_BA0

DDR3A_A13

DDR3A_DM4

DDR3A_ZQ03

DDR3A_BA2DDR3A_BA1DDR3A_BA0

DDR3A_A13

DDR3A_DM0DDR3A_DM1

DDR3A_ZQ01

DDR3A_BA2DDR3A_BA1DDR3A_BA0

DDR3A_A13

DDR3A_CLK_P

DDR3A_CSnDDR3A_WEnDDR3A_RASnDDR3A_CASn

DDR3A_RESETnDDR3A_ODT

DDR3A_CKE

DDR3A_CLK_NDDR3A_CLK_P

DDR3A_CSnDDR3A_WEnDDR3A_RASnDDR3A_CASn

DDR3A_RESETnDDR3A_ODT

DDR3A_CKE

DDR3A_CLK_N

DDR3A_CKE

DDR3A_RESETn

DDR3A_CLK_NDDR3A_CLK_P

1.5V_DDR3

VTT_DDR3A

VTT_DDR3A

VTT_DDR3A

VTT_DDR3AVTT_DDR3A

VTT_DDR3A

1.5V_DDR3

VREF_DDR3A

1.5V_DDR3

VREF_DDR3A

1.5V_DDR3

VREF_DDR3A

1.5V_DDR3

1.5V_DDR3

1.5V_DDR3

1.5V_DDR3

DDR3A_DM[4:0]4

DDR3A_BA[2:0]4

DDR3A_DQ[39:0]4

DDR3A_DQS_P[4:0]4

DDR3A_DQS_N[4:0]4

DDR3A_CLK_P4

DDR3A_CSn4DDR3A_WEn4DDR3A_RASn4DDR3A_CASn4

DDR3A_RESETn4DDR3A_ODT4

DDR3A_CKE4

DDR3A_CLK_N4

DDR3A_A[13:0]4,9

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B12 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B12 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B12 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

DDR3 DeviceU28

MT41K128M16JT

A5P2 A4P8 A3N2 A2P3 A1P7 A0N3

NC4L9

A10/APL7

A11R7

A12/BCnN7

RESETnT2

VSSQB1

VSSQB9

VSSQD1

A9R3 A8T8 A7R2 A6R8

NC5M7

NC1J1

NC3L1

ZQL8

CK_NK7

WEL3

CKEK9

A13T3

ODTK1

NC2J9

RASJ3

CK_PJ7

CSL2

BA0M2

BA1N8

BA2M3

CASK3

DM1D3

NC6T7

DM0E7

VDDB2

VDDD9

VDDG7

VDDK2

VSSA9

VSSB3

VSSE1

VSSG8

DQ0E3

DQS_P0F3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

DQS_P1C7DQS_N0G3

DQS_N1B7

VSSQD8

VSSQE2

VSSQE8

VSSQF9

VDDQH9

VDDK8

VDDN1

VDDN9

VDDR1

VDDR9

VREFDQH1

VREFCAM8

VSSQG1

VSSQG9

VDDQA1

VDDQA8

VDDQC1

VDDQC9

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VSSJ2

VSSJ8

VSSM1

VSSM9

VSSP1

VSSP9

VSST1

VSST9

C483

0.01uF

R318200

RN7E 515 12

C453

0.47uF

C513

0.1uF

C484

3.3nF

C454

0.01uF

C473

2.2nF

RN6G 517 10

C458

0.47uF

CN6

0.1uF

1234 5

678

C530

0.47uF

C531

2.2nF

RN5B 512 15

R326

240

RN6D 514 13

R288240

RN5G 517 10

C499

0.1uF

RN4F 516 11

R287240

C457

0.47uF

C481

0.1uF

C451

0.47uF

C470

2.2nF

C498

4.7nF

RN4D 514 13

C497

3.3nF

RN4G 517 10

RN5D 514 13

C510

0.1uF

CN4

0.1uF

1234 5

678

RN7F 516 11

RN5E 515 12

C509

0.01uF

RN7D 514 13

R286240

RN4C 513 14

C512

0.1uF

RN5F 516 11

RN6B 512 15

C452

0.1uF

RN7C 513 14

C494

2.2nF

C456

0.1uF

RN5A 511 16

C436

2.2nF

C493

0.1uF

C482

2.2nF

RN6F 516 11RN6E 515 12CN5

0.1uF

1234 5

678

C486

0.1uF

RN7B 512 15

RN5H 518 9

RN6H 518 9

C495

4.7nF

C472

2.2nF

C496

0.1uF

R330 4.70K, 1%

C485

0.01uF

C532

0.47uF

R339 51

C511

0.01uF

RN7H 518 9

R325

240

RN4E 515 12

RN6C 513 14

C487

2.2nF

R327

240

RN4B 512 15

RN7A 511 16

C450

0.01uF

C500

2.2nF

RN4H 518 9

DDR3 DeviceU27

MT41K128M16JT

A5P2 A4P8 A3N2 A2P3 A1P7 A0N3

NC4L9

A10/APL7

A11R7

A12/BCnN7

RESETnT2

VSSQB1

VSSQB9

VSSQD1

A9R3 A8T8 A7R2 A6R8

NC5M7

NC1J1

NC3L1

ZQL8

CK_NK7

WEL3

CKEK9

A13T3

ODTK1

NC2J9

RASJ3

CK_PJ7

CSL2

BA0M2

BA1N8

BA2M3

CASK3

DM1D3

NC6T7

DM0E7

VDDB2

VDDD9

VDDG7

VDDK2

VSSA9

VSSB3

VSSE1

VSSG8

DQ0E3

DQS_P0F3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

DQS_P1C7DQS_N0G3

DQS_N1B7

VSSQD8

VSSQE2

VSSQE8

VSSQF9

VDDQH9

VDDK8

VDDN1

VDDN9

VDDR1

VDDR9

VREFDQH1

VREFCAM8

VSSQG1

VSSQG9

VDDQA1

VDDQA8

VDDQC1

VDDQC9

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VSSJ2

VSSJ8

VSSM1

VSSM9

VSSP1

VSSP9

VSST1

VSST9

C455

0.01uF

RN6A 511 16

C437

2.2nF

C471

2.2nF

RN4A 511 16

C501

4.7nF

RN7G 517 10

DDR3 DeviceU26

MT41K128M16JT

A5P2 A4P8 A3N2 A2P3 A1P7 A0N3

NC4L9

A10/APL7

A11R7

A12/BCnN7

RESETnT2

VSSQB1

VSSQB9

VSSQD1

A9R3 A8T8 A7R2 A6R8

NC5M7

NC1J1

NC3L1

ZQL8

CK_NK7

WEL3

CKEK9

A13T3

ODTK1

NC2J9

RASJ3

CK_PJ7

CSL2

BA0M2

BA1N8

BA2M3

CASK3

DM1D3

NC6T7

DM0E7

VDDB2

VDDD9

VDDG7

VDDK2

VSSA9

VSSB3

VSSE1

VSSG8

DQ0E3

DQS_P0F3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

DQS_P1C7DQS_N0G3

DQS_N1B7

VSSQD8

VSSQE2

VSSQE8

VSSQF9

VDDQH9

VDDK8

VDDN1

VDDN9

VDDR1

VDDR9

VREFDQH1

VREFCAM8

VSSQG1

VSSQG9

VDDQA1

VDDQA8

VDDQC1

VDDQC9

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VSSJ2

VSSJ8

VSSM1

VSSM9

VSSP1

VSSP9

VSST1

VSST9

R317200

RN5C 513 14

Page 13: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

DDR3B (x64 Soft Memory Controller)DDR3B INTERFACE

Place These Caps Near DDR3 (U8, U15, U22 and U30)

Place one terminationresistor at the end of eachbranch.

DDR3B_CASn

DDR3B_A5

DDR3B_CLK_P DDR3B_CLK_N

DDR3B_A4DDR3B_A8

DDR3B_A1

DDR3B_A6

DDR3B_A11

DDR3B_A0

DDR3B_BA0

DDR3B_A7

DDR3B_A5

DDR3B_A1

DDR3B_A6

DDR3B_A11

DDR3B_A0

DDR3B_A7

DDR3B_A12

DDR3B_A2

DDR3B_A8

DDR3B_A3

DDR3B_A9

DDR3B_A4

DDR3B_A10

DDR3B_A12

DDR3B_BA2DDR3B_A0

DDR3B_A2

DDR3B_A8

DDR3B_A5 DDR3B_A2DDR3B_A7

DDR3B_A12

DDR3B_CSnDDR3B_A3

DDR3B_A6

DDR3B_ODTDDR3B_RASn

DDR3B_A3

DDR3B_A9

DDR3B_A1 DDR3B_BA1DDR3B_WEn

DDR3B_A4

DDR3B_A10

DDR3B_A13DDR3B_A9

DDR3B_A10

DDR3B_A11

DDR3B_ZQ2

DDR3B_CLK_P

DDR3B_CSnDDR3B_WEnDDR3B_RASnDDR3B_CASn

DDR3B_RESETnDDR3B_ODT

DDR3B_BA2

DDR3B_CKE

DDR3B_BA1

DDR3B_CLK_N

DDR3B_BA0

DDR3B_A13

DDR3B_ZQ1

DDR3B_BA2DDR3B_BA1DDR3B_BA0

DDR3B_A13

DDR3B_DM2DDR3B_DM3

DDR3B_DQ20

DDR3B_DQ26

DDR3B_DQ21

DDR3B_DQ27

DDR3B_DQ22

DDR3B_DQ28

DDR3B_DQ17

DDR3B_DQ23

DDR3B_DQ16

DDR3B_DQ29

DDR3B_DQS_P2DDR3B_DQS_N2

DDR3B_DQ18

DDR3B_DQ24

DDR3B_DQ30

DDR3B_DQS_P3DDR3B_DQS_N3

DDR3B_DQ19

DDR3B_DQ25

DDR3B_DQ31

DDR3B_DQS_P0

DDR3B_DQ5

DDR3B_DQ11

DDR3B_DQ6

DDR3B_DQ12

DDR3B_DQ0DDR3B_DQ1

DDR3B_DQS_N0

DDR3B_DQ7

DDR3B_DQ13

DDR3B_DQS_P1

DDR3B_DQ2

DDR3B_DQS_N1

DDR3B_DQ8

DDR3B_DQ14

DDR3B_DQ3

DDR3B_DQ9

DDR3B_DQ15

DDR3B_DQ4

DDR3B_DQ10

DDR3B_DM0DDR3B_DM1

DDR3B_CKE

DDR3B_RESETn

DDR3B_CLK_PDDR3B_CKE

DDR3B_CLK_N

DDR3B_CSnDDR3B_WEnDDR3B_RASnDDR3B_CASn

DDR3B_RESETnDDR3B_ODT

DDR3B_DM4DDR3B_DM5

DDR3B_DQ36

DDR3B_DQ42

DDR3B_DQ37

DDR3B_DQ43

DDR3B_DQ38

DDR3B_DQ44

DDR3B_DQ33

DDR3B_DQ39

DDR3B_DQ32

DDR3B_DQ45

DDR3B_DQS_P4DDR3B_DQS_N4

DDR3B_DQ34

DDR3B_DQ40

DDR3B_DQ46

DDR3B_DQS_P5DDR3B_DQS_N5

DDR3B_DQ35

DDR3B_DQ41

DDR3B_DQ47

DDR3B_DQS_P6DDR3B_DQS_N6DDR3B_DQS_P7DDR3B_DQS_N7

DDR3B_DM6DDR3B_DM7

DDR3B_A5

DDR3B_A1

DDR3B_A6

DDR3B_A11

DDR3B_A0

DDR3B_A7

DDR3B_A5

DDR3B_A1

DDR3B_A6

DDR3B_A11

DDR3B_A0

DDR3B_A7

DDR3B_A12

DDR3B_A2

DDR3B_A8

DDR3B_A3

DDR3B_A9

DDR3B_A4

DDR3B_A10

DDR3B_A12

DDR3B_A2

DDR3B_A8

DDR3B_A3

DDR3B_A9

DDR3B_A4

DDR3B_A10

DDR3B_ZQ3

DDR3B_CLK_P

DDR3B_CSnDDR3B_WEnDDR3B_RASnDDR3B_CASn

DDR3B_RESETnDDR3B_ODT

DDR3B_BA2

DDR3B_CKE

DDR3B_BA1

DDR3B_CLK_N

DDR3B_BA0

DDR3B_A13

DDR3B_ZQ4

DDR3B_BA2DDR3B_BA1DDR3B_BA0

DDR3B_A13

DDR3B_DQ52

DDR3B_DQ58

DDR3B_DQ53

DDR3B_DQ59

DDR3B_DQ54

DDR3B_DQ60

DDR3B_DQ49

DDR3B_DQ55

DDR3B_DQ48

DDR3B_DQ61

DDR3B_DQ50

DDR3B_DQ56

DDR3B_DQ62

DDR3B_DQ51

DDR3B_DQ57

DDR3B_DQ63

DDR3B_CLK_P DDR3B_CLK_N

VTT_DDR3B

VTT_DDR3B

VTT_DDR3B

VTT_DDR3BVTT_DDR3B

VTT_DDR3B

VREF_DDR3B

1.5V_DDR3

VREF_DDR3B

1.5V_DDR3

1.5V_DDR3

1.5V_DDR3

1.5V_DDR3

VREF_DDR3B

1.5V_DDR3

VREF_DDR3B

1.5V_DDR3

1.5V_DDR3

1.5V_DDR3

DDR3B_CLK_P5DDR3B_CKE5

DDR3B_CLK_N5

DDR3B_CSn9DDR3B_WEn5DDR3B_RASn5DDR3B_CASn5

DDR3B_RESETn5DDR3B_ODT5

DDR3B_DM[7:0]5,9

DDR3B_BA[2:0]5

DDR3B_DQ[63:0]5,9

DDR3B_DQS_P[7:0]5

DDR3B_DQS_N[7:0]5

DDR3B_A[13:0]5,9

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B13 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B13 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B13 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

RN2E 515 12

C221

0.47uF

RN3E 515 12

RN1H 518 9

V29

C268

0.01uF

DDR3 DeviceU30

MT41K128M16JT

A5P2 A4P8 A3N2 A2P3 A1P7 A0N3

NC4L9

A10/APL7

A11R7

A12/BCnN7

RESETnT2

VSSQB1

VSSQB9

VSSQD1

A9R3 A8T8 A7R2 A6R8

NC5M7

NC1J1

NC3L1

ZQL8

CK_NK7

WEL3

CKEK9

A13T3

ODTK1

NC2J9

RASJ3

CK_PJ7

CSL2

BA0M2

BA1N8

BA2M3

CASK3

DM1D3

NC6T7

DM0E7

VDDB2

VDDD9

VDDG7

VDDK2

VSSA9

VSSB3

VSSE1

VSSG8

DQ0E3

DQS_P0F3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

DQS_P1C7DQS_N0G3

DQS_N1B7

VSSQD8

VSSQE2

VSSQE8

VSSQF9

VDDQH9

VDDK8

VDDN1

VDDN9

VDDR1

VDDR9

VREFDQH1

VREFCAM8

VSSQG1

VSSQG9

VDDQA1

VDDQA8

VDDQC1

VDDQC9

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VSSJ2

VSSJ8

VSSM1

VSSM9

VSSP1

VSSP9

VSST1

VSST9

RN1E 515 12

C525

4.7nF

C465

0.1uF

C391

0.01uF

C393

0.47uF

V11

C523

0.47uF

R244

240

CN3

0.1uF

1234 5

678

V21

C426

0.01uF

C271

0.47uF

RN3A 511 16V13CN1

0.1uF

1234 5

678

C269

4.7nF

C218

0.1uF

C389

2.2nF

DDR3 DeviceU15

MT41K128M16JT

A5P2 A4P8 A3N2 A2P3 A1P7 A0N3

NC4L9

A10/APL7

A11R7

A12/BCnN7

RESETnT2

VSSQB1

VSSQB9

VSSQD1

A9R3 A8T8 A7R2 A6R8

NC5M7

NC1J1

NC3L1

ZQL8

CK_NK7

WEL3

CKEK9

A13T3

ODTK1

NC2J9

RASJ3

CK_PJ7

CSL2

BA0M2

BA1N8

BA2M3

CASK3

DM1D3

NC6T7

DM0E7

VDDB2

VDDD9

VDDG7

VDDK2

VSSA9

VSSB3

VSSE1

VSSG8

DQ0E3

DQS_P0F3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

DQS_P1C7DQS_N0G3

DQS_N1B7

VSSQD8

VSSQE2

VSSQE8

VSSQF9

VDDQH9

VDDK8

VDDN1

VDDN9

VDDR1

VDDR9

VREFDQH1

VREFCAM8

VSSQG1

VSSQG9

VDDQA1

VDDQA8

VDDQC1

VDDQC9

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VSSJ2

VSSJ8

VSSM1

VSSM9

VSSP1

VSSP9

VSST1

VSST9

V26RN3C 513 14

C446

4.7nF

V25V23

C390

0.1uF

C300

0.47uF

RN3G 517 10

V7

V16

C444

3.3nF

C467

0.1uF

RN2B 512 15

R323200

C272

2.2nF

V14

C527

2.2nF

RN2A 511 16

C365

0.1uF

C222

2.2nF

CN2

0.1uF

1234 5

678

R276

240

C219

0.01uF

V20

RN3D 514 13

C363

0.01uF

RN3B 512 15

C364

4.7nF

C490

0.1uF

C443

2.2nF

RN1D 514 13RN1C 513 14

C270

0.1uF

V31

RN2H 518 9

C524

0.01uF

RN3H 518 9

RN2G 517 10

DDR3 DeviceU22

MT41K128M16JT

A5P2 A4P8 A3N2 A2P3 A1P7 A0N3

NC4L9

A10/APL7

A11R7

A12/BCnN7

RESETnT2

VSSQB1

VSSQB9

VSSQD1

A9R3 A8T8 A7R2 A6R8

NC5M7

NC1J1

NC3L1

ZQL8

CK_NK7

WEL3

CKEK9

A13T3

ODTK1

NC2J9

RASJ3

CK_PJ7

CSL2

BA0M2

BA1N8

BA2M3

CASK3

DM1D3

NC6T7

DM0E7

VDDB2

VDDD9

VDDG7

VDDK2

VSSA9

VSSB3

VSSE1

VSSG8

DQ0E3

DQS_P0F3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

DQS_P1C7DQS_N0G3

DQS_N1B7

VSSQD8

VSSQE2

VSSQE8

VSSQF9

VDDQH9

VDDK8

VDDN1

VDDN9

VDDR1

VDDR9

VREFDQH1

VREFCAM8

VSSQG1

VSSQG9

VDDQA1

VDDQA8

VDDQC1

VDDQC9

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VSSJ2

VSSJ8

VSSM1

VSSM9

VSSP1

VSSP9

VSST1

VSST9

V27

C522

2.2nF

RN3F 516 11

C299

0.1uF

C301

2.2nF

R275 51

C220

0.1uF

R265 4.70K, 1%

C394

2.2nF

C361

2.2nF

C466

0.01uF

RN1B 512 15

C250

0.1uF

C526

0.1uF

DDR3 DeviceU8

MT41K128M16JT

A5P2 A4P8 A3N2 A2P3 A1P7 A0N3

NC4L9

A10/APL7

A11R7

A12/BCnN7

RESETnT2

VSSQB1

VSSQB9

VSSQD1

A9R3 A8T8 A7R2 A6R8

NC5M7

NC1J1

NC3L1

ZQL8

CK_NK7

WEL3

CKEK9

A13T3

ODTK1

NC2J9

RASJ3

CK_PJ7

CSL2

BA0M2

BA1N8

BA2M3

CASK3

DM1D3

NC6T7

DM0E7

VDDB2

VDDD9

VDDG7

VDDK2

VSSA9

VSSB3

VSSE1

VSSG8

DQ0E3

DQS_P0F3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

DQS_P1C7DQS_N0G3

DQS_N1B7

VSSQD8

VSSQE2

VSSQE8

VSSQF9

VDDQH9

VDDK8

VDDN1

VDDN9

VDDR1

VDDR9

VREFDQH1

VREFCAM8

VSSQG1

VSSQG9

VDDQA1

VDDQA8

VDDQC1

VDDQC9

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VSSJ2

VSSJ8

VSSM1

VSSM9

VSSP1

VSSP9

VSST1

VSST9

R204

240

V12V30

R306

240

C445

0.01uF

V34RN1G 517 10

C336

0.01uF

C297

0.1uF

RN1A 511 16

V17

C298

0.01uF

V24

C366

2.2nF

RN2C 513 14

C468

0.47uF

V33V22

C267

3.3nF

V28

C528

2.2nF

RN1F 516 11

C447

0.1uF

C362

0.47uF

R222200V9

RN2F 516 11

C234

2.2nF

V32RN2D 514 13

C464

2.2nF

C296

2.2nF

C266

2.2nF

V10

C217

2.2nF

C448

0.47uF

V15

V8

C449

2.2nF

C469

2.2nF

C392

0.1uF

Page 14: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

FM BUS INTERFACE

FLASH

FLASH 1Gb

FPGA CONFIG BUS INTERFACE

F_RSTn

F_WEnF_RDYBSYn

FLASH_WPn

FM_D3

FM_D15

FM_D9

FM_D4

FM_D10

FM_D5

FM_D11

FM_D6

FM_D0

FM_D12

FM_D7

FM_D1

FM_D13

FM_D8

FM_D2

FM_D14

FPGA_nCSO

FM_A17

FM_A2

FM_A21

FM_A6

FM_A1

FM_A25

FM_A10

FM_A14

FM_A18

FM_A3

FM_A22

FM_A7

FM_A11

FM_A15

FM_A19

FM_A4

FM_A23

FM_A8

FM_A12

FM_A16

FM_A20

FM_A5

FM_A24

FM_A9

FM_A13

FM_A26

FPGA_AS_DATA0FPGA_AS_DATA1FPGA_AS_DATA2FPGA_AS_DATA3FPGA_DCLKFPGA_nCSO

FLASH_WPn

FLASH_CEnF_OEnF_WEnF_ADVn

FPGA_AS_DATA0FPGA_AS_DATA1FPGA_AS_DATA2FPGA_AS_DATA3FPGA_nCSO

FPGA_CONFIG_D0FPGA_CONFIG_D1FPGA_CONFIG_D2FPGA_CONFIG_D3FPGA_CONFIG_D4

F_RSTn

FLASH_CLKF_RDYBSYnFPGA_AS_DATA0

FPGA_AS_DATA1FPGA_AS_DATA2FPGA_AS_DATA3

FLASH_CEnF_OEn

F_ADVn

F_ADVn

F_OEnF_RSTnF_WEn

1.8V

1.8V1.8V

1.8V

1.8V

3.3V

3.3V

3.3V

3.3V

1.5V_DDR31.8V

3.3V1.8V 1.5V_DDR3

FM_A[26:1]5,10,15

FM_D[15:0]5,10,15

FPGA_DCLK10,15

FPGA_CONFIG_D[15:0] 10,15

MAX_AS_CONF15

FLASH_CEn 10,15FLASH_CLK 10,15

FLASH_RDYBSYn 9,15

FLASH_ADVn 5,15

FLASH_RESETn 4,15FLASH_OEn 4,15

FLASH_WEn 4,15

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B14 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B14 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B14 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R349 10K

U33

EPCQ256SI16N

DATA31

DATA18

DATA29

GND10

DATA015

DCLK16

CSn7

VCC2

NC35

NC13

NC24 NC4

6

NC511

NC612

NC713

NC814

R316 DNI

R320 DNI

C90

0.1uF

C463

0.1uF

C544

0.1uF

U29

IDTQS3861

NC1

A02

A13

A24

A35

A46

A57

A68

A79

A810

A911

GND12

BE23

VCC24

B022

B121

B220

B319

B418

B517

B616

B715

B814

B913

C548

0.1uF

R312 DNI

C462

0.1uF

R353 DNI

C72

0.1uF

R314 DNI

R352 10K

R315 DNIC521

0.1uF

U35

MAX3023

VL3

IO VL11

IO VL22

IO VL35

IO VL46

NC14

EN7

VCC12

IO VCC114

IO VCC213

IO VCC310

IO VCC49

GND11

EN8

C89

0.1uF

R359 10K

R301 10K

C545

1uF

C73

0.1uF

R3450

R344 10K

R59 10K

R354 10K

PC28FxxxP30B85FLASH

U20

PC28F00AP30BF

A1A1

A2B1

A3C1

A4D1

A5D2

A6A2

A7C2

A8A3

A9B3

A10C3

A11D3

A12C4

A13A5

A14B5

A15C5

A16D7

A17D8

A18A7

A19B7

A20C7

A21C8

A22A8

NC(64M)/A23G1

CE#B4

OE#F8

WE#G8

WP#C6

VCCA6

RESET#D4

VCCH3

D0F2

D1E2

D2G3

D3E4

D4E5

D5G5

D6G6

D7H7

D8E1

D9E3

D10F3

D11F4

D12F5

D13H5

D14G7

D15E7

WAITF7

GNDB2

GNDH4GNDH2

CLKE6

ADV#F6

NC/A26(1G)B8

RFU3E8RFU2F1RFU1G2RFU0H1

NC(64M,128M)/A24H8

NC/A25(512M)B6

VPPA4

VCCQD6VCCQD5

VCCQG4

GNDH6

C71

0.1uF

R313 DNI

R351 10K

C91

0.1uF

C535

0.1uF

Page 15: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

5M2210 System Controller

VCCINT 2.5V VCCIO 1.8V VCCIO

FLASH INTERFACEFPGA CONFIG INTERFACE

ON-BOARD USB BLASTER II

MAX CTL INTERFACEINSTALL R340 ONLY WHEN MAX V IS NOT POPULATED.

SDI INTERFACE

CLOCK INTERFACESJTAG INTERFACE

LED INTERFACE

PUSH BUTTON INTERFACE

DIPSWITCH INTERFACE

FPGA_DCLKFPGA_CONFIG_D1FPGA_CONFIG_D2FPGA_CONFIG_D3

FPGA_CONFIG_D5FPGA_CONFIG_D6

FPGA_CONFIG_D4

FPGA_nSTATUSFPGA_CONF_DONE

FPGA_CONFIG_D0

FPGA_CONFIG_D7

CLK_CONFIG

FPGA_MSEL1FPGA_MSEL2

FPGA_MSEL0

FPGA_MSEL3FPGA_MSEL4

FPGA_CONFIG_D8FPGA_CONFIG_D9FPGA_CONFIG_D10FPGA_CONFIG_D11FPGA_CONFIG_D12FPGA_CONFIG_D13FPGA_CONFIG_D14FPGA_CONFIG_D15

CLK_CONFIG

CLKIN_MAX_50

SENSE_SDO

SENSE_SCKSENSE_SDI

SENSE_CSn

FPGA_CvP_CONFDONEFPGA_PR_ERROR

CLK50_EN

Si570_EN

CLK125_ENCLOCK_SDA

CLOCK_SCL

HSMB_PRSNTnHSMA_PRSNTn

PGM_SEL

MAX_CONF_DONE

FPGA_nCONFIG

PGM_LED0PGM_CONFIG

OVERTEMP

SDI_A_RX_EN

SDI_A_TX_ENSDI_A_RX_BYPASS

FLASH_OEn

FLASH_ADVn

FLASH_CEn

FLASH_CLKFLASH_RESETn

FLASH_WEn

FLASH_RDYBSYn

CPU_RESETn

MAX_ERRORMAX_LOAD

SI571_EN

FM_D14FM_D15

FM_D10FM_D11FM_D12FM_D13

FM_D8FM_D9

FM_A1FM_A2FM_A3FM_A4FM_A5FM_A6FM_A7

FM_A14

FM_A8FM_A9

FM_A15

FM_A10FM_A11FM_A12FM_A13

FM_D1FM_D2FM_D3

FM_D0

FM_D4FM_D5FM_D6FM_D7

FPGA_PR_READYFPGA_PR_REQUESTFPGA_PR_DONE

PGM_LED1PGM_LED2

FACTORY_USER

CLK_SELCLK_ENABLE

MAX_RESETn

FACTORY_STATUS

ASSP_MODE

MAX_OEn

MAX_WEnMAX_CSn

MAX_CLK

M570_CLOCK

FACTORY_REQUESTM570_PCIE_JTAG_EN

USB_CFG0

USB_CFG1

USB_CFG2USB_CFG3USB_CFG4USB_CFG5USB_CFG6USB_CFG7USB_CFG8USB_CFG9

USB_CFG10

USB_CFG11

USB_CLK

EXTRA_SIG0

EXTRA_SIG1

EXTRA_SIG2

JTAG_TMS

JTAG_EPM2210_TDIJTAG_TCK

JTAG_BLASTER_TDI

FM_A21FM_A22

FM_A19FM_A20

FM_A18

FM_A16FM_A17

FM_A23FM_A24FM_A25FM_A26

JTAG_EPM2210_TDI JTAG_BLASTER_TDI

FPGA_CEn

ASSP_CPLD_MRn

FORCE_FAN

MAX_AS_CONF

2.5V

1.8V

2.5V

2.5V1.8V

2.5V

1.8V

1.8V

ASSP_MODE 20

FLASH_RDYBSYn 9,14

FM_A[26:1]5,10,14

FM_D[15:0]5,10,14

FLASH_CEn 10,14

FLASH_ADVn 5,14

FLASH_WEn4,14

FLASH_OEn 4,14

FLASH_RESETn 4,14FLASH_CLK 10,14

FPGA_CEn 10

FPGA_nCONFIG 10FPGA_DCLK 10,14FPGA_CONF_DONE 10FPGA_nSTATUS 10

FPGA_CONFIG_D[15:0] 10,14

FPGA_PR_DONE 10FPGA_PR_REQUEST 10FPGA_PR_READY 10FPGA_PR_ERROR 10FPGA_CvP_CONFDONE 10FPGA_MSEL0 10FPGA_MSEL1 10FPGA_MSEL2 10FPGA_MSEL3 10FPGA_MSEL4 10

M570_CLOCK 19

USB_CFG[11:0]19

M570_PCIE_JTAG_EN 19

FACTORY_STATUS 19

USB_CLK 9,19

EXTRA_SIG[2:0]19

FACTORY_REQUEST 19

MAX_OEn 5

MAX_WEn 5MAX_CLK 9

MAX_CSn 5

JTAG_TCK 10,11,18,19JTAG_EPM2210_TDI 11JTAG_TMS 10,11,19

JTAG_BLASTER_TDI 11,19

CLOCK_SDA 8CLOCK_SCL 8

CLKIN_MAX_50 8

Si570_EN 8CLK50_EN 8

SI571_EN 8

CLK125_EN 8

PGM_LED[2:0] 20

CPU_RESETn 10,20

SENSE_SCK 29SENSE_SDI 29

CLK_SEL 8,20CLK_ENABLE 20

OVERTEMP 29

HSMA_PRSNTn 6,18,20HSMB_PRSNTn 6,18,20

SENSE_CSn 29SENSE_SDO 29

FACTORY_USER 20

PGM_SEL 20PGM_CONFIG 20

MAX_RESETn 20MAX_ERROR 20MAX_LOAD 20MAX_CONF_DONE 20

MAX_AS_CONF 14

SDI_A_TX_EN 4,16SDI_A_RX_BYPASS 4,16SDI_A_RX_EN 4,16

ASSP_CPLD_MRn 21

FORCE_FAN 10

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B15 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B15 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B15 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C534

0.1uF

C514

0.1uF

C546

0.1uF

MAX VBANK3

U32C

5M2210ZF256

IOB3/CLK2J12

IOB3/CLK3H12

DIFFIO_R9PG12

DIFFIO_R9NG16

DIFFIO_R8PG13

DIFFIO_R8NG15

DIFFIO_R7PG14

DIFFIO_R7NF16

DIFFIO_R6PE16

DIFFIO_R6NF15

DIFFIO_R5PF13

DIFFIO_R5NE15

DIFFIO_R4PF14

DIFFIO_R4ND16

DIFFIO_R3PE12

DIFFIO_R3ND15

DIFFIO_R2PC15

DIFFIO_R2NE13

DIFFIO_R22PP15

DIFFIO_R22NP14

DIFFIO_R21PN15

DIFFIO_R21NN14

DIFFIO_R20PN16

DIFFIO_R20NM13

DIFFIO_R1PE14

DIFFIO_R1NC14

DIFFIO_R19PM15

DIFFIO_R19NL14

DIFFIO_R18PM16

DIFFIO_R18NL13

DIFFIO_R17PL15

DIFFIO_R17NL12

DIFFIO_R16PL16

DIFFIO_R16NL11

DIFFIO_R15PK15

DIFFIO_R15NK14

DIFFIO_R14PK16

DIFFIO_R14NK13

DIFFIO_R13PJ14

DIFFIO_R13NJ15

DIFFIO_R12PJ13

DIFFIO_R12NJ16

DIFFIO_R11PH13

DIFFIO_R11NH16

DIFFIO_R10PH14

DIFFIO_R10NH15

IOB3_21D13

IOB3_22D14

IOB3_23F11

IOB3_24F12

IOB3_25K12

IOB3_26M14

IOB3_27N13

C475

0.1uF

C517

0.1uF

X2

100MHz

VCC4

GND2

OUT3

EN1

C505

0.1uF

C547

0.1uF

MAX VBANK2

U32B

5M2210ZF256

DIFFIO_T9PB8

DIFFIO_T9NA8

DIFFIO_T8PD8

DIFFIO_T8NA7

DIFFIO_T7PC8

DIFFIO_T7NB7

DIFFIO_T6PB6

DIFFIO_T6NE7

DIFFIO_T5PA5

DIFFIO_T5ND7

DIFFIO_T4PE6

DIFFIO_T4NB5

DIFFIO_T3PB4

DIFFIO_T3ND6

DIFFIO_T2PC5

DIFFIO_T2NC4

DIFFIO_T1PD4

DIFFIO_T1NB1

DIFFIO_T18PC13

DIFFIO_T18NB16

DIFFIO_T17PD12

DIFFIO_T17NB14

DIFFIO_T16PC11

DIFFIO_T16NB13

DIFFIO_T15PE11

DIFFIO_T15NB12

DIFFIO_T14PB11

DIFFIO_T14NA12

DIFFIO_T13PE10

DIFFIO_T13NA11

DIFFIO_T12PA10

DIFFIO_T12NC9

DIFFIO_T11PB9

DIFFIO_T11ND9

DIFFIO_T10PA9

DIFFIO_T10NE9

IOB2_6A13

IOB2_7A15

IOB2_8A2

IOB2_9A4

IOB2_10A6

IOB2_11B10

IOB2_12B3

IOB2_13C10

IOB2_14C12

IOB2_15C6

IOB2_16C7

IOB2_17D10

IOB2_18D11

IOB2_19D5

IOB2_20E8

C502

0.1uF

C519

0.1uF

C477

0.1uF

MAX VBANK4

U32D

5M2210ZF256

DIFFIO_B13N/DEV_CLRnM9

DIFFIO_B13P/DEV_OEM8

DIFFIO_B9PP8

DIFFIO_B9NT7

DIFFIO_B8PM7

DIFFIO_B8NR7

DIFFIO_B7PR6

DIFFIO_B7NN7

DIFFIO_B6PT5

DIFFIO_B6NP7

DIFFIO_B5PR5

DIFFIO_B5NM6

DIFFIO_B4PP6

DIFFIO_B4NN6

DIFFIO_B3PR3

DIFFIO_B3NN5

DIFFIO_B2PT2

DIFFIO_B2NP5

DIFFIO_B22PR16

DIFFIO_B22NP13

DIFFIO_B21PP12

DIFFIO_B21NT15

DIFFIO_B20PN12

DIFFIO_B20NR14

DIFFIO_B1PR1

DIFFIO_B1NP4

DIFFIO_B19PT13

DIFFIO_B19NR13

DIFFIO_B18PR12

DIFFIO_B18NP11

DIFFIO_B17PT12

DIFFIO_B17NN11

DIFFIO_B16PP10

DIFFIO_B16NR11

DIFFIO_B15PN10

DIFFIO_B15NT11

DIFFIO_B14PM10

DIFFIO_B14NR10

DIFFIO_B12PR9

DIFFIO_B12NP9

DIFFIO_B11PT8

DIFFIO_B11NT9

DIFFIO_B10PN8

DIFFIO_B10NR8 IOB4_28

M11

IOB4_29M12

IOB4_30N9

IOB4_31R4

IOB4_32T10

IOB4_33T4

C504

0.1uF

MAX VBANK1

U32A

5M2210ZF256

DIFFIO_L19PN1

IOB1/CLK0H5

IOB1/CLK1J5

DIFFIO_L9PG1

DIFFIO_L9NG4

DIFFIO_L8PG2

DIFFIO_L8NG3

DIFFIO_L7PF1

DIFFIO_L7NF6

DIFFIO_L6PF4

DIFFIO_L6NF2

DIFFIO_L5PF3

DIFFIO_L5NE1

DIFFIO_L4PD1

DIFFIO_L4NE5

DIFFIO_L3PD2

DIFFIO_L3NE4

DIFFIO_L2PC3

DIFFIO_L2NE3

DIFFIO_L21PN3

DIFFIO_L21NP2

DIFFIO_L20PN2

DIFFIO_L20NM3

DIFFIO_L1PD3

DIFFIO_L1NC2

DIFFIO_L19NM4

DIFFIO_L18PL4

DIFFIO_L18NL3

DIFFIO_L17PM1

DIFFIO_L17NM2

DIFFIO_L16PL2

DIFFIO_L16NK3

DIFFIO_L15PK5

DIFFIO_L15NL1

DIFFIO_L14PJ3

DIFFIO_L14NK2

DIFFIO_L13PJ4

DIFFIO_L13NK1

DIFFIO_L12PH4

DIFFIO_L12NJ2

DIFFIO_L11PH3

DIFFIO_L11NJ1

DIFFIO_L10PH2

DIFFIO_L10NG5

IOB1_1E2

IOB1_2F5

IOB1_3H1

IOB1_4K4

IOB1_5L5

TMSN4TDOM5TDIL6TCKP3

C520

0.1uF

C515

0.1uF

C518

0.1uF

MAX VPower

U32E

5M2210ZF256

GNDINTF7

GNDINTG6

GNDINTH7

GNDINTH9

GNDIOA1

GNDIOA16

GNDIOB15

GNDIOB2

GNDIOG10

GNDIOG7

GNDIOG8

GNDIOG9

GNDIOK10

GNDIOK7

GNDIOK8

GNDIOK9

GNDIOR15

GNDIOR2

GNDIOT1

GNDIOT16

VCCINTH8VCCINTH10VCCINTG11VCCINTF10

VCCIO1C1

VCCIO1H6

VCCIO1J6

VCCIO1P1

VCCIO2A14

VCCIO2A3

VCCIO2F8

VCCIO2F9

VCCIO3C16

VCCIO3H11

VCCIO3J11

VCCIO3P16

VCCIO4L8

VCCIO4L9

VCCIO4T14

VCCIO4T3

GNDINTJ10

VCCINTJ7

VCCINTL7

GNDINTJ8

GNDINTK11

VCCINTK6VCCINTJ9

GNDINTL10

GNDIOT6

C536

0.1uF

C533

0.1uF

C516

0.1uF

R340 DNI

C476

0.1uF

C474

0.1uF

C537

0.1uF

C503

0.1uF

C478

2.2uF

Page 16: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

SDI Cable Driver, Equalizer, and SMB

75 Ohm Impedance

75 Ohm Impedance

RightAngle

SDI_A_TXDRV_P

SDI_A_TXBNC_P

SDI_A_TXBNC_N

SDI_A_TXDRV_N

SDI_A_IN_P1

SDI_A_EQIN_P1SDI_A_EQIN_N1

SDO_A_NSDO_A_P

SDI_A_TX_RSET

SDI_A_TXCAP_PSDI_A_TXCAP_N

AEC1

SDI_A_RX_CDn

3.3V_SDI_A

3.3V_SDI_A

3.3V_SDI_A

3.3V_SDI_A

3.3V_SDI_A

3.3V_SDI_A

3.3V

3.3V_SDI_A

3.3V_SDI_A

3.3V_SDI_A

SDI_A_RX_P 7SDI_A_RX_N 7

SDI_A_RX_EN4,15

SDI_A_RX_BYPASS4,15

SDI_A_TX_N7

SDI_A_TX_EN4,15

SDI_A_TX_SD_HDn4

SDI_A_TX_P7

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B16 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B16 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B16 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R273

0

R263

0

R290 750

D32

Green_LED

J11

Mini SMB1

2345

R284 75

CableDriver

U50

LMH0303

SDI1

SDI2

VEE3

RREF4

VCC9

SD/HD10

SDO12

SDO11

CENTERPAD17

RSTI5

ENABLE6

SDA7

SCL8

FAULT13

NC514

NC615

RSTO16

R291 75

C415

220nF

C459

0.1uF

R280 75

C417 4.7uF

U47

LMH0384

VEE11

SPI_EN4

SDI2

SDI3

AEC+5

AEC-6

BYPASS7

MUTEref8 VEE2

9

SDO11

SDO10

AUTO_SLEEP12

MUTE14

CD15

VCC113

VCC216

DAP17

R289

49.9

L11 5.6nH1 2

R29275

R27475

L10120 Ohm FB

C431 4.7uF

R27075

C346 1uF

C418 4.7uF

R278 75

J12

Mini SMB1

2 3 4 5

C373 1uF

R267

37.4

R268 75

L9 3.9nH1 2

R25710K

C63 4.7uF

L12 5.6nH1 2

C414

22uF

C381

220nF

C432 4.7uF

R277

49.9

C413

0.01uF

C62 4.7uF

C382

0.1uF

C372 1uF

Page 17: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

10/100/1000 EthernetRGMII Mode (default)

Place near 88E1111 PHY

ENET_LED_RX

ENET_LED_TX

ENET_LED_LINK100

ENET_LED_LINK1000

ENET_MDC

ENET_LED_TX

ENET_INTn

MDI_P1MDI_N1MDI_P2MDI_N2

ENET_RESETn

MDI_P3

ENET_LED_RX

ENET_LED_LINK1000ENET_LED_LINK100ENET_LED_LINK10

MDI_N3

ENET_XTAL_25MHZ

MDI_N0

ENET_RSET

ENET_MDIO

MDI_P0MDI_P1MDI_N1MDI_P2MDI_N2MDI_P3MDI_N3

MDI_N0MDI_P0 ENET_LED_RX

ENET_LED_DUPLEX

ENET_RX_D1

ENET_RX_D3

ENET_RX_D0

ENET_RX_D2

ENET_TX_D1

ENET_TX_D3

ENET_TX_D0

ENET_TX_D2

ENET_GTX_CLK

ENET_RX_DV

ENET_TX_EN

ENET_RX_CLK

ENET_LED_DUPLEX

ENET_LED_LINK10

2.5V

ENET_DVDD2.5V

2.5V

2.5V

2.5V

ENET_DVDD

2.5V

2.5V

2.5V

ENET_MDIO 4

ENET_RESETn 4

ENET_INTn 4

ENET_MDC 4

ENET_TX_D[3:0]4

ENET_RX_D[3:0]4

ENET_RX_DV 4ENET_RX_CLK 4

ENET_TX_EN 4ENET_GTX_CLK 4

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B17 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B17 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B17 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R207 220

R240 49.9

R494.7K

J9

HFJ11-1G02E

TD0_P1

TD0_N2

TD1_P3

TD1_N6

TD2_P4

TD2_N5

TD3_P7

TD3_N8

VCC9

GND10

GN

D_T

AB

11G

ND

_TA

B12

C50

0.1uF

X1

25.00MHz

VCC4

GND2

OUT3

EN1

R38 4.7K

C60

0.1uF

C45

0.1uF

R5210.0K

R39 4.7K

C318 0.01uF

D22Green_LED

C44

0.1uF

R238 49.9

D23Green_LED

C59

0.1uF

R239 49.9

GMII/MII/TBI INTERFACE

TEST

SGMII INTERFACE

JTAGMDI INTERFACE

MGMT

U11A

88E1111

COMA27

RESET_N28

CONFIG658 CONFIG559 CONFIG460 CONFIG361 CONFIG263 CONFIG164 CONFIG065

125CLK22

XTAL155

XTAL254

VSSC53

RSET30

SEL_FREQ56

MDI3_P42

MDI3_N43

MDI2_P39

MDI2_N41

MDI1_P33

MDI1_N34

MDI0_P29

MDI0_N31

MDIO24

MDC25

INT_N23

HSDAC_P37

HSDAC_N38

GTX_CLK8

TX_CLK4

TX_EN9

RXCLK2

RX_DV94

CRS84

COL83

S_CLK_P79

S_CLK_N80

S_IN_P82

S_IN_N81

S_OUT_P77

S_OUT_N75

LED_TX68

LED_RX69

LED_DUPLEX70

LED_LINK100073

LED_LINK10074

LED_LINK1076

RXD095

RXD192

RXD293

RXD391

RXD490

RXD589

RXD687

RXD786

RX_ER3

TXD011

TXD112

TXD214

TXD316

TXD417

TXD518

TXD619

TXD720

TX_ER7

TMS46 TDO50 TDI44 TCK49 TRST_N47

C38

0.1uF

D26Green_LED

R444.99K

C263 0.01uF

R212 220

C53

0.1uF

U11B

88E1111

NC113

VSS97

DVDD1

DVDD6

DVDD10

DVDD15

DVDD57

DVDD62

DVDD67

DVDD71

DVDD85

AVDD32

AVDD36

AVDD35

AVDD40

AVDD45

AVDD78

VD

DO

X26

VD

DO

X48

VD

DO

5

VD

DO

21

VD

DO

88

VD

DO

96

VD

DO

H72

VD

DO

H66

VD

DO

H52

NC251

R247 49.9R246 49.9

C47

0.1uF

C37

0.1uF

D25Green_LED

R230 49.9

C36

0.1uF

C61

0.1uF

R40 4.7K

C262 0.01uFR229 49.9

C35

0.1uF

R211 220

C294 0.01uF

D24Green_LED

R208 220

C58

0.1uF

R206 220

R43 4.7K

C345

0.01uF

R231 49.9

Page 18: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

HSMC Port A & Port B

A

HSMC PORT A INTERFACE

B

HSMC PORT B INTERFACE

DDR ODT

PLACE NEAR JTAG_TCK PIN NEAR HSMC PORT A PLACE NEAR JTAG_TCK PIN NEAR HSMC PORT B

HSMA_D1HSMA_D3

HSMA_RX_D_P0HSMA_RX_D_N0

HSMA_RX_D_P1HSMA_RX_D_N1

HSMA_RX_D_P2HSMA_RX_D_N2

HSMA_RX_D_P3HSMA_RX_D_N3

HSMA_RX_D_P4HSMA_RX_D_N4

HSMA_RX_D_P5HSMA_RX_D_N5

HSMA_RX_D_P6HSMA_RX_D_N6

HSMA_RX_D_P7HSMA_RX_D_N7

HSMA_CLK_IN_P1HSMA_CLK_IN_N1

HSMA_RX_D_P8HSMA_RX_D_N8

HSMA_RX_D_P9HSMA_RX_D_N9

HSMA_RX_D_P10HSMA_RX_D_N10

HSMA_RX_D_P11HSMA_RX_D_N11

HSMA_RX_D_P12HSMA_RX_D_N12

HSMA_RX_D_P13HSMA_RX_D_N13

HSMA_RX_D_P14HSMA_RX_D_N14

HSMA_RX_D_P15HSMA_RX_D_N15

HSMA_RX_D_P16HSMA_RX_D_N16

HSMA_CLK_IN_P2HSMA_CLK_IN_N2

HSMA_TX_D_P0HSMA_TX_D_N0

HSMA_TX_D_P1HSMA_TX_D_N1

HSMA_TX_D_P2HSMA_TX_D_N2

HSMA_TX_D_P3HSMA_TX_D_N3

HSMA_TX_D_P4HSMA_TX_D_N4

HSMA_TX_D_P5HSMA_TX_D_N5

HSMA_TX_D_P6HSMA_TX_D_N6

HSMA_TX_D_P7HSMA_TX_D_N7

HSMA_CLK_OUT_P1HSMA_CLK_OUT_N1

HSMA_TX_D_P8HSMA_TX_D_N8

HSMA_TX_D_P9HSMA_TX_D_N9

HSMA_TX_D_P10HSMA_TX_D_N10

HSMA_TX_D_P11HSMA_TX_D_N11

HSMA_TX_D_P12HSMA_TX_D_N12

HSMA_TX_D_P13HSMA_TX_D_N13

HSMA_TX_D_P14HSMA_TX_D_N14

HSMA_TX_D_P15HSMA_TX_D_N15

HSMA_TX_D_P16HSMA_TX_D_N16

HSMA_CLK_OUT_P2HSMA_CLK_OUT_N2

HSMA_D0HSMA_D2

HSMA_PRSNTn

JTAG_TCK

HSMB_DQ0

HSMB_CLK_OUT_P1HSMB_CLK_OUT_N1

HSMB_CLK_OUT_P2HSMB_CLK_OUT_N2

HSMB_WEn

HSMB_CLK_IN_P1HSMB_CLK_IN_N1

HSMB_CLK_IN_P2HSMB_CLK_IN_N2HSMB_PRSNTn

HSMB_RASnHSMB_CASn

HSMB_A1

HSMB_A0

HSMB_A2

HSMB_A3HSMB_A4

HSMB_A5

HSMB_A6HSMB_A7

HSMB_A8HSMB_A9

HSMB_A10

HSMB_A11HSMB_A12

HSMB_A13HSMB_A14

HSMB_A15

HSMB_BA0HSMB_BA1

HSMB_BA2HSMB_BA3

HSMB_DM0

HSMB_DM1

HSMB_DM2

HSMB_DM3

HSMB_DQ1

HSMB_DQ2HSMB_DQ3

HSMB_DQ4HSMB_DQ5

HSMB_DQ6HSMB_DQ7

HSMB_DQ8HSMB_DQ9

HSMB_DQ10HSMB_DQ11

HSMB_DQ12HSMB_DQ13

HSMB_DQ14HSMB_DQ15

HSMB_DQ16HSMB_DQ17

HSMB_DQ18HSMB_DQ19

HSMB_DQ20HSMB_DQ21

HSMB_DQ22HSMB_DQ23

HSMB_DQ24HSMB_DQ25

HSMB_DQ26HSMB_DQ27

HSMB_DQ28HSMB_DQ29

HSMB_DQ30HSMB_DQ31

HSMB_DQS_P0HSMB_DQS_N0

HSMB_DQS_P1HSMB_DQS_N1

HSMB_DQS_P2HSMB_DQS_N2

HSMB_DQS_P3HSMB_DQS_N3

HSMB_CKEHSMB_CSn

HSMB_C_PHSMB_C_N

HSMB_ADDR_CMD0

HSMA_RX_CP3HSMA_RX_CN3HSMA_RX_CP2HSMA_RX_CN2HSMA_RX_CP1HSMA_RX_CN1HSMA_RX_CP0HSMA_RX_CN0

HSMB_RX_CP3HSMB_RX_CN3HSMB_RX_CP2HSMB_RX_CN2HSMB_RX_CP1HSMB_RX_CN1HSMB_RX_CP0HSMB_RX_CN0

JTAG_TCK JTAG_TCK

12V3.3V

12V 3.3V

12V 3.3V12V

3.3V

HSMA_SCL 6HSMA_JTAG_TMS 11JTAG_FPGA_TDO 10,11

HSMA_TX_N07HSMA_TX_P07HSMA_TX_N17HSMA_TX_P17HSMA_TX_N27HSMA_TX_P27HSMA_TX_N37HSMA_TX_P37

HSMA_CLK_OUT_P[2:1]6,9

HSMA_CLK_OUT_N[2:1]6,9

HSMA_CLK_IN_N[2:1]9

HSMA_CLK_IN_P[2:1]9

HSMA_SDA6JTAG_TCK10,11,15,19

HSMA_D[3:0]6

HSMA_TX_D_P[16:0]6

HSMA_TX_D_N[16:0]6

HSMA_RX_D_P[16:0]6

HSMA_RX_D_N[16:0]6

HSMA_PRSNTn 6,15,20

HSMA_JTAG_TDO11HSMA_CLK_IN0 6HSMA_CLK_OUT06

HSMB_JTAG_TMS 11HSMB_JTAG_TDI 11

HSMB_SCL 6

HSMB_CLK_OUT_P[2:1]6

HSMB_TX_N37

HSMB_CLK_OUT_N[2:1]6

HSMB_TX_P37

HSMB_TX_N27HSMB_TX_P27

HSMB_TX_N17HSMB_TX_P17

HSMB_TX_N07HSMB_TX_P07

HSMB_SDA6

HSMB_CLK_OUT06HSMB_JTAG_TDO11

HSMB_CLK_IN0 6

HSMB_CLK_IN_P[2:1]6,9

HSMB_CLK_IN_N[2:1]6,9

HSMB_CASn 6HSMB_CKE 6

HSMB_DQS_P[3:0]6

HSMB_DQS_N[3:0]6

HSMB_RASn 6

HSMB_ADDR_CMD0 6

HSMB_DQ[31:0]6

HSMB_BA[3:0]6

HSMB_DM[3:0]6

HSMB_A[15:0]6

HSMB_CSn 6HSMB_WEn 6

HSMB_PRSNTn 6,15,20HSMB_C_P 6HSMB_C_N 6

HSMA_RX_N3 7HSMA_RX_P3 7

HSMA_RX_N0 7HSMA_RX_P0 7HSMA_RX_N1 7HSMA_RX_P1 7HSMA_RX_N2 7HSMA_RX_P2 7

HSMB_RX_N3 7HSMB_RX_P3 7

HSMB_RX_N2 7HSMB_RX_P2 7

HSMB_RX_N1 7HSMB_RX_P1 7

HSMB_RX_N0 7HSMB_RX_P0 7

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B18 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B18 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B18 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

BANK 1

BANK 2

BANK 3

J1

ASP-122953-01

11

33

55

77

99

1111

1313

1515

1717

1919

2121

2323

2525

2727

2929

3131

3333

3535

3737

3939

4141

4343

3.3V45

4747

4949

3.3V51

5353

5555

3.3V57

5959

6161

3.3V63

6565

6767

3.3V69

7171

7373

3.3V75

7777

7979

3.3V81

8383

8585

3.3V87

8989

9191

3.3V93

9595

9797

3.3V99

101101

103103

3.3V105

107107

109109

3.3V111

113113

115115

3.3V117

119119

22

44

66

88

1010

1212

1414

1616

1818

2020

2222

2424

2626

2828

3030

3232

3434

3636

3838

4040

4242

4444

12V46

4848

5050

12V52

5454

5656

12V58

6060

6262

12V64

6666

6868

12V70

7272

7474

12V76

7878

8080

12V82

8484

8686

12V88

9090

9292

12V94

9696

9898

12V100

102102

104104

12V106

108108

110110

12V112

114114

116116

12V118

120120

GN

D_1

_116

1

GN

D_1

_216

2

GN

D_1

_316

3

GN

D_1

_416

4

GN

D_2

_116

5

GN

D_2

_216

6

GN

D_2

_316

7

GN

D_3

_116

9G

ND

_2_4

168

GN

D_3

_217

0

GN

D_3

_317

1

GN

D_3

_417

2

121121

3.3V123

125125

127127

3.3V129

131131

133133

3.3V135

137137

139139

3.3V141

143143

145145

3.3V147

149149

151151

3.3V153

155155

157157

3.3V159

122122

12V124

126126

128128

12V130

132132

134134

12V136

138138

140140

12V142

144144

146146

12V148

150150

152152

12V154

156156

158158

PSNTn160

R1100

R111 DNI C1339.0pF

R1150

C132DNI

R1500R1670

C131

10uF

R1250

C130

10uF

R1490

R1410

C129

10uF

R1240R1160

R1610

BANK 1

BANK 2

BANK 3

J2

ASP-122953-01

11

33

55

77

99

1111

1313

1515

1717

1919

2121

2323

2525

2727

2929

3131

3333

3535

3737

3939

4141

4343

3.3V45

4747

4949

3.3V51

5353

5555

3.3V57

5959

6161

3.3V63

6565

6767

3.3V69

7171

7373

3.3V75

7777

7979

3.3V81

8383

8585

3.3V87

8989

9191

3.3V93

9595

9797

3.3V99

101101

103103

3.3V105

107107

109109

3.3V111

113113

115115

3.3V117

119119

22

44

66

88

1010

1212

1414

1616

1818

2020

2222

2424

2626

2828

3030

3232

3434

3636

3838

4040

4242

4444

12V46

4848

5050

12V52

5454

5656

12V58

6060

6262

12V64

6666

6868

12V70

7272

7474

12V76

7878

8080

12V82

8484

8686

12V88

9090

9292

12V94

9696

9898

12V100

102102

104104

12V106

108108

110110

12V112

114114

116116

12V118

120120

GN

D_1

_116

1

GN

D_1

_216

2

GN

D_1

_316

3

GN

D_1

_416

4

GN

D_2

_116

5

GN

D_2

_216

6

GN

D_2

_316

7

GN

D_3

_116

9G

ND

_2_4

168

GN

D_3

_217

0

GN

D_3

_317

1

GN

D_3

_417

2

121121

3.3V123

125125

127127

3.3V129

131131

133133

3.3V135

137137

139139

3.3V141

143143

145145

3.3V147

149149

151151

3.3V153

155155

157157

3.3V159

122122

12V124

126126

128128

12V130

132132

134134

12V136

138138

140140

12V142

144144

146146

12V148

150150

152152

12V154

156156

158158

PSNTn160

R1710

R1420

R1700

C128

10uF

R109 100

R1680R1620

R1690

Page 19: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

On-Board USB Blaster II USB INTERFACE

PLACE NEAR MAX II (U34)

JTAG INTERFACE

PLACE NEAR CY7C68013A

MAX II USB INTERFACE

ASSP JTAG INTERFACE

SW_USB_MAX_TDOSW_USB_MAX_TMS

SW_USB_MAX_TCK

SW_USB_MAX_TDI

FX2_D_NFX2_D_P

FX2_WAKEUPVBUS_5V

VBUS_5V

RESn_JTAG_TXJTAG_TX

FX2_PD4FX2_PD3

FX2_PD0FX2_PD1FX2_PD2

FX2_PD5FX2_PD6FX2_PD7

24M_XTALIN24M_XTALOUT

FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7

FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7

USB_CLK

FX2_RESETn

FX2_SDA MAX_SDA

RESn_SC_RXSC_RX

RESn_SC_TXSC_TX

RESn_JTAG_RXJTAG_RX

FX2_FLAGCFX2_FLAGB

FX2_WAKEUP

FX2_SLWRnFX2_SLRDn

FX2_FLAGA

FX2_SCLFX2_SDA

FX2_RESETn

USB_SCLUSB_SDAUSB_FULLUSB_EMPTY

FACTORY_REQUEST

JTAG_BLASTER_TDOJTAG_BLASTER_TDIJTAG_TMSJTAG_TCK

C_JTAG_TDOC_JTAG_TDIC_JTAG_TMSC_JTAG_TCK

FX2_PD2FX2_PD0

FX2_PD3FX2_PD1

JTAG_BLASTER_TDI

C_USB_MAX_TDIUSB_CLK

C_USB_MAX_TMS

FX2_PB5

MAX_SDA

C_USB_MAX_TCK

C_USB_MAX_TDOFX2_RESETn

USB_FULLUSB_EMPTYUSB_SCL

USB_ADDR0USB_ADDR1

SC_RX

USB_DATA5

JTAG_TX

FACTORY_REQUEST

USB_CFG2

USB_SDA

USB_RESETn

USB_DATA2

USB_DATA0

USB_OEn

SC_TX

USB_RDn

USB_DATA6

USB_DATA1

USB_WRn

USB_CFG1

USB_DATA3JTAG_RX

M570_PCIE_JTAG_EN

USB_DATA7

USB_DATA4

USB_CFG9

USB_CFG0

FACTORY_STATUS

M570_CLOCK

USB_CFG3

USB_CFG4

USB_CFG6

USB_CFG7

USB_CFG8

USB_CFG10

USB_CFG5

USB_CFG11

EXTRA_SIG0

EXTRA_SIG1

EXTRA_SIG2

C_JTAG_TDO

C_JTAG_TDIC_JTAG_TMS

C_JTAG_TCK

FX2_SCL

FX2_SLRDn

FX2_SLWRn

FX2_FLAGB

FX2_FLAGC

FX2_PA1

FX2_PA3

FX2_PA2

FX2_PA4

FX2_PA5

FX2_PA6

FX2_PA7

FX2_PB0

FX2_PB1

FX2_PB2

FX2_PB3

FX2_PB4

FX2_PB6

FX2_PB7

FX2_PD4

FX2_PD5

FX2_PD6

FX2_PD7

USB_DISABLEn

FX2_FLAGA

ASSP_CPLD_MAX_TDO

ASSP_CPLD_MAX_TCK

ASSP_CPLD_MAX_TMS

ASSP_CPLD_MAX_TDI

C_USB_MAX_TCK

C_USB_MAX_TDO

C_USB_MAX_TDI

C_USB_MAX_TMS

SW_USB_MAX_TDO

SW_USB_MAX_TMS

SW_USB_MAX_TCK

SW_USB_MAX_TDI 3.3V 3.3V

3.3V3.3V

1.5V 1.8V3.3V

1.8V

3.3V

3.3V

1.5V

2.5V

3.3V

1.8V

1.5V

USB_DATA[7:0]4

USB_FULL 4USB_EMPTY 4

USB_SDA 4

USB_RESETn 9USB_OEn 4USB_RDn 9USB_WRn 4

JTAG_BLASTER_TDO 10,11

JTAG_TMS 10,11,15JTAG_TCK 10,11,15,18

JTAG_BLASTER_TDI 11,15

USB_DISABLEn 11

USB_ADDR[1:0]4

USB_SCL 4

FACTORY_STATUS 15

M570_CLOCK 15

USB_CLK 9,15

FACTORY_REQUEST 15

M570_PCIE_JTAG_EN 15

USB_CFG[11:0] 15

EXTRA_SIG[2:0] 15

ASSP_CPLD_MAX_TDI 21

ASSP_CPLD_MAX_TMS 21ASSP_CPLD_MAX_TCK 21

ASSP_CPLD_MAX_TDO 21

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B19 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B19 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B19 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R3370

R35 DNI

Y1

24.00MHz

1 3

24

R850

R260 56.2

C67

0.1uF

R3220

R181M

MAX IIPower

U49C

EPM570GT100C3NEPM570T100Version = 1.1

GNDINT11

GNDINT37

GNDINT90

GNDINT65

GNDIO93

GNDIO32

GNDIO46

GNDIO79

VCCINT13VCCINT39

VCCIO131

VCCIO145

VCCIO19

VCCIO294

VCCIO280

VCCIO259

GNDIO60

GNDIO10

VCCINT63

VCCINT88

C174

0.1uF

R321DNI

R68 1.00k

R60 0

R177 10.0K

R61 0

R210 0

R62 0

R63 0

R810

R333 1.00K

D30

Green_LED

R77 1.00k

R329DNIR3280

C79

0.1uF

C86

0.1uF

R198 2.00K

R750

C134.7nF

R262 56.2

C205

0.1uF

U4

CY7C68013A_VFBGA

RDY0A1

RDY1B1

XTALINC1

AVCCD1

DMINUSE1

AGNDF1

VCCG1

GNDH1

PD7A2

CLKOUTB2

XTALOUTC2

AVCCD2

DPLUSE2

AGNDF2

IFCLKG2

RESERVEDH2

PD5A3PD4B3

PD6C3

SCLF3

SDAG3

PB0H3

GNDA4

GNDB4

GNDC4

PB1F4

PB3G4PB2H4

VCCA5

VCCB5

PB6F5PB5G5PB4H5

PD3A6PD2B6

PA7C6

PA4F6

PA1G6

PB7H6

PD1A7

WAKEUPB7

PA6C7

GNDD7

VCCE7

PA3F7

CTL1G7CTL0H7

PD0A8

RESETB8

PA5C8

GNDD8

VCCE8

PA2F8

PA0G8

CTL2H8

VCCC5

R74 1.00k

C80

0.1uF

C84

0.1uF

R261 56.2

R334DNI

R302 DNI

R338 1.00K

R820

U6

MAX811

GND1

RESET2

VCC4

MR3

C211 0.1uF

C206

0.1uF

MAX IIBANK2

U49B

EPM570GT100C3NEPM570T100Version = 1.1

IOB2_152

IOB2_253

IOB2_354

IOB2_455

IOB2_556

IOB2_657

IOB2_758

IOB2_861

IOB2_966

IOB2_1067

IOB2_1168

IOB2_1269

IOB2_1370

IOB2_1471

IOB2_1572

IOB2_1673

IOB2_1774

IOB2_1875

IOB2_1976

IOB2_2077

IOB2_2178

IOB2_2281

IOB2_2382

IOB2_2483

IOB2_2584

IOB2_2685

IOB2_2786

IOB2_2887

IOB2_2989

IOB2_3091

IOB2_3192

IOB2_3295

IOB2_3396

IOB2_3497

IOB2_3598

IOB2_3699

IOB2_37100

IOB2_381IOB2/GCLK2

62

IOB2/GCLK364

U5

TPD2EUSB30D-

2D+1

GND3

D28

Green_LED

R80 1.00k

R202100K

C156

0.1uF

R336DNI

R76 1.00k

R3350

C210

0.1uF

MAX IIBANK1

U49A

EPM570GT100C3NEPM570T100Version = 1.1

IOB1_2335

IOB1_2436

IOB1/GCLK012

IOB1/GCLK114

IOB1_12

IOB1_23

IOB1_34

IOB1_451

IOB1_55

IOB1_66

IOB1_77

IOB1_88

IOB1_915

IOB1_1016

IOB1_1117

IOB1_1218

IOB1_1319

IOB1_1420

IOB1_1521

IOB1_1626

IOB1_1727

IOB1_1828

IOB1_1929

IOB1_2030

IOB1_2133

IOB1_2234

IOB1_2538

IOB1_2640

IOB1_2741

IOB1_2842

IOB1_2947

IOB1_3048

IOB1_3149

IOB1_3250

TMS22TDO25TDI23TCK24

IOB1/DEV_OE43 IOB1/DEV_CLRn44

C157

0.1uF

C96

0.1uF

C149

12pF

D27

Green_LED

C173

0.1uF

D29

Green_LED

R209 2.00K

J18

DNI

11

33

55

77

22

44

66

88

99

1010

C185

0.1uF

C158

0.1uF

J5USB MINI-AB

12345

67

C150

12pF

R259 56.2

R176

20.0K

Page 20: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

PUSH BUTTON INTERFACE

LED INTERFACE

User I/O

DIP SWITCH INTERFACE

CLK_ENABLEFACTORY_USER

USER_PB1

USER_PB2

CLK_SEL

ASSP_MODE

USER_PB0

MAX_RESETn

CPU_RESETn

MAX_CONF_DONE RES_CONF_DONE1n

RESn_HSMA_RX_LEDHSMA_RX_LED

HSMA_TX_LED RESn_HSMA_TX_LED

PCIE_LED_X4

PCIE_LED_X1

HSMA_PRSNTn

PGM_SEL

PGM_CONFIG

RESn_PGM1_LED1

RESn_PGM1_LED2

PGM_LED1

PGM_LED2

PGM_LED0 RESn_PGM1_LED0

MAX_LOAD RES_MAX_LOAD1

MAX_ERROR RES_MAX_ERROR1

USER_DIPSW3USER_DIPSW4

USER_DIPSW0USER_DIPSW1USER_DIPSW2

USER_DIPSW5

RESn_LED1

RESn_LED2

USER_LED1

USER_LED2

USER_LED0 RESn_LED0

RESn_LED3

RESn_LED4

USER_LED3

USER_LED4

RESn_LED5

RESn_LED6

USER_LED5

USER_LED6

RESn_LED7USER_LED7

RESn_HSMB_RX_LEDHSMB_RX_LED

HSMB_TX_LED RESn_HSMB_TX_LED

HSMB_PRSNTn

USER_DIPSW6USER_DIPSW7

I2C_SDA_DISPI2C_SCL_DISP

I2C_SDA_DISPI2C_SCL_DISP

SPI_SS_DISP

SPI_SS_DISP

2.5V

2.5V

2.5V

2.5V

2.5V

3.3V

2.5V

2.5V

2.5V

1.8V

2.5V

2.5V

2.5V

3.3V

5.0V

2.5V5.0V

2.5V5.0V

USER_DIPSW[7:0] 6

CPU_RESETn 10,15

HSMB_RX_LED 6HSMB_TX_LED 6

USER_PB[2:0]4

PCIE_LED_X1 4PCIE_LED_X4 4

HSMB_PRSNTn 6,15,18

USER_LED[7:0]4

PGM_SEL 15PGM_CONFIG 15MAX_RESETn 15

PGM_LED[2:0]15

CLK_SEL 8,15CLK_ENABLE 15FACTORY_USER 15

MAX_ERROR 15MAX_LOAD 15MAX_CONF_DONE 15HSMA_RX_LED 6HSMA_TX_LED 6HSMA_PRSNTn 6,15,18

ASSP_MODE 15

DISP_I2C_SDA 4DISP_I2C_SCL 4

DISP_SPISS 4

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B20 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B20 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B20 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R356 10.0K

R114 56.2

R17

2

DNI

OPEN

SW4

TDA04H0SB1

12345

678

S4

PB Switch1 2

D1 Green_LED

D12 Green_LED

D5 Red_LED

D4

Green_LED

R145 10.0K

R155 56.2

R108 56.2

R148 100, 1%

U12

MAX3373

VCCIO21

GND2

VL3

VL_IO24VL_IO15

VCCIO18

VCC7

TRI_STATE6

R143 10.0KD7 Green_LED

R151 56.2

R341 10.0K

R104 56.2

D18 Green_LED

D2 Green_LED

R131 56.2

R1790

S5

PB Switch1 2

R112 56.2

R347 10.0K

S7

PB Switch1 2

D45YELLOW LED

R357 56.2

D16 Green_LED

R23

4

DNI

R113 56.2

D9 Green_LED

R164 56.2

R13910.0K

D14 Green_LEDR153 56.2

R23

5

DNI

R165 56.2

R163 56.2

D3

Green_LED

D10 Green_LED

R350 10.0K

S1

PB Switch1 2

D6 Green_LED

R13810.0K

D13 Green_LED D17 Green_LED

R130 56.2

R346 10.0K

R14010.0K

J10

LCD_HEADER

123456789

10

R132 56.2

R13710.0K

R147 56.2

S6

PB Switch1 2

R154 56.2

R128 10.0K

D8 Green_LED

S2

PB Switch1 2

R13610.0K

R358 56.2

R144 10.0K

D35YELLOW LED

R129 56.2

D34YELLOW LED

R2410

R13510.0K

R152 56.2

R126 10.0K

U38

MAX3373

VCCIO21

GND2

VL3

VL_IO24VL_IO15

VCCIO18

VCC7

TRI_STATE6

R105 56.2

R127 10.0K

D11 Green_LED S3

PB Switch1 2

R13410.0K

D44YELLOW LED

D15 Green_LED

R146 56.2

R17

3

DNI

B3

2x16 LCD I2C

SW1

TDA08H0SB1

12345678

161514131211109

D20

Green_LED

R13310.0K

D19

Green_LED

R156 56.2

Page 21: Cyclone V GT Development Kit Board

8

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6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

ASSP CPLD

PLACE NEAR MAX II EPM570

MVE ASSP Core Interface

DATA FLOWS FROM A to Y

DATA FLOWS FROM A to Y

ASSP_CPLD_MRnASSP_CPLD_RESETn

ASSP_CPLD_RESETn

SC_CLK

SC_V_IN

SC_SHIFT_EN

SC_DATAOUT ASSP_DATAOUT

ASSP_CLKSC_CLK

SC_SYS_RESET

SC_SYS_RESET ASSP_SYS_RESET

ASSP_TEST2

SC_DATAINSC_V_IN

ASSP_RANDOM_INASSP_RUN_IN

SC_DATAIN

SC_DATAOUT

SC_SHIFT_EN ASSP_SHIFT_EN

SC_TEST2

ASSP_TEST1SC_TEST2

SC_TEST1

SC_TEST1

1.8V

3.3V

3.3V 3.3V1.8V

1.8V

3.3V

3.3V

3.3V

3.3V 1.5V

3.3V 1.5V1.5V

1.5V

ASSP_CPLD_MRn 15

ASSP_RANDOM_IN 4

ASSP_DATAOUT 4

ASSP_CLK 4ASSP_RUN_IN 4ASSP_SYS_RESET 4

ASSP_TEST1 4ASSP_TEST2 4

ASSP_CPLD_MAX_TDI 19ASSP_CPLD_MAX_TCK 19

ASSP_CPLD_MAX_TMS 19ASSP_CPLD_MAX_TDO 19

ASSP_SHIFT_EN 4

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B21 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B21 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B21 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C104

0.1uF

C421

0.1uF

U34

DNI

VCCI1

A02

A13

A24

A35

A46

GND7

VCCO14

Y013

Y112

Y211

Y310

Y49

OE8

GND_EPAD15

MAX IIBANK1

U23A

DNI

IOB1_23L1

IOB1_24L10

IOB1/GCLK0F2

IOB1/GCLK1E1

IOB1_1B1

IOB1_2C1

IOB1_3C2

IOB1_4D1

IOB1_5D2

IOB1_6D3

IOB1_7E2

IOB1_8F1

IOB1_9F3

IOB1_10G1

IOB1_11G2

IOB1_12H1

IOB1_13H2

IOB1_14H3

IOB1_15J6

IOB1_16K10

IOB1_17K3

IOB1_18K4

IOB1_19K5

IOB1_20K6

IOB1_21K7

IOB1_22K9

IOB1_25L11

IOB1_26L2

IOB1_27L3

IOB1_28L4

IOB1_29L5

IOB1_30L6

IOB1_31L7

IOB1_32L9

TMSJ1TDOK2TDIJ2TCKK1

IOB1/DEV_OEL8 IOB1/DEV_CLRnK8

C122

0.1uFC434

0.1uF

C105

0.1uF

C422

0.1uF

C433

0.1uF

MAX IIPower

U23C

DNI

GNDINTC5

GNDINTE8

GNDINTG4

GNDINTJ5

GNDIOD5

GNDIOD7

GNDIOE4

GNDIOG8

VCCINTJ7VCCINTG3

VCCIO1E3

VCCIO1J4

VCCIO1J8

VCCIO2C4

VCCIO2C8

VCCIO2G9

GNDIOH5

GNDIOH7

VCCINTC7

VCCINTE9

U51

DNI

GND1

RESET2

VCC4

MR3

C121

0.1uF

U31

DNI

VCCI1

A02

A13

A24

A35

A46

GND7

VCCO14

Y013

Y112

Y211

Y310

Y49

OE8

GND_EPAD15

C440

0.1uF

MAX IIBANK2

U23B

DNI

IOB2_1A1

IOB2_2A10

IOB2_3A11

IOB2_4A2

IOB2_5A3

IOB2_6A4

IOB2_7A5

IOB2_8A6

IOB2_9A7

IOB2_10A8

IOB2_11A9

IOB2_12B10

IOB2_13B11

IOB2_14B2

IOB2_15B3

IOB2_16B4

IOB2_17B5

IOB2_18B6

IOB2_19B7

IOB2_20B8

IOB2_21B9

IOB2_22C10

IOB2_23C11

IOB2_24C6

IOB2_25D10

IOB2_26D11

IOB2_27D9

IOB2_28E10

IOB2_29E11

IOB2_30F11

IOB2_31F9

IOB2_32G10

IOB2_33H10

IOB2_34H11

IOB2_35H9

IOB2_36J10

IOB2_37J11

IOB2_38K11IOB2/GCLK2

F10

IOB2/GCLK3G11

C461

0.1uF

R304

100K

C439

0.1uF

C480

0.1uF

Page 22: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power - Cyclone V GT Power

(2.5V)

20mm Coin Cell

C5_VCC

C5_2.5V

C5_VCCIO_2.5V

C5_VCCIO_2.5V

C5_VCCIO_2.5V

C5_VCCIO_2.5V

C5_VCCIO_VAR

C5_VCCIO_1.5V

VREF_DDR3B

C5_VCCIO_1.5V

C5_VCCIO_1.5V

C5_VCCIO_1.5V

VREF_DDR3A

VREF_DDR3A

C5_VCCIO_1.8V

VREF_DDR3B

VCCBAT2.5V_VCCBAT_SKT

2.5V

VREF_HSMB

VREF_HSMB C5_VCCIO_VAR

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B22 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B22 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B22 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R248

DNI

C334

0.1uF

Cyclone V GT I/O Power

5CGTFD9E5F35

U13J

Version = 0.2 Preliminary

VCCIO3AAD13

VCCIO3AAM7

VCCIO3AAK11

VCCIO3AAJ8

VCCIO3AAG12

VCCIO3BAB17

VCCIO3BAN10

VCCIO3BAM17

VREFB3AN0AH11

VCCIO3BAH15

VCCIO3BAE16

VREFB3BN0AH18

VCCIO4AAN30

VCCIO4AAM27

VCCIO4AAK21

VREFB4AN0AG20

VCCIO5AAK31

VCCIO5AAF29

VCCIO5AY26

VREFB5AN0AE27

VCCIO6AP23

VCCIO6AT29VCCIO6AU32VCCIO6AG32

VREFB5BN0V29

VREFB6AN0P29VCCIO6AJ28

VCCIO6AM27VCCIO6AN30

VCCIO7AE26VCCIO7AF29

VCCIO7AG22VCCIO7AH25

VCCIO7AK21

VCCIO8AB17

VREFB7AN0G19VCCIO7AB27VCCIO7AC30

VCCIO8AE16VCCIO8AE6

VCCIO8AG12

VCCIO4AAH25

VCCIO4AAL24

VCCIO4AAN20

VCCIO5AAE26

VCCIO5BV25

VCCIO6AK31

VCCIO8AF9

VCCIO8AK11

VCCIO7AC20

VCCIO4AAD23

VCCIO4AAJ28

VCCIO4AAC20

VCCIO5AAB27

VCCIO5BW28

VCCIO6AP33

VCCIO7AA24

VCCIO7AD23

VCCIO8AH15

VCCIO3AAF9

VCCIO3BAL14

VCCIO5AAA24

VCCIO6AR26

VCCIO7AF19

VCCIO8AC10

VCCIO4AAJ18

VCCIO4AAG22

VCCIO4AAF19

VCCIO8AD13

VCCIO7AJ18

VCCIO8AB7

VCCIO8AA14VCCIO8AB12

VREFB8AN0G16

VCCIO5BY31 VCCIO5B

AC30 VCCIO5BAD33 VCCIO5BAG32

R184100, 1%

R249

0

Cyclone V GT Power

5CGTFD9E5F35

U13K

Version = 0.2 Preliminary

GNDL24

GNDAP2

GNDAP4

GNDAP8

GNDAP13

GNDAP18

GNDAP23

GNDAP28

GNDAP33

GNDAN6

GNDAN15

GNDAN25

GNDAM3

GNDAM12

GNDAM22

GNDAM32

GNDAL5

GNDAL9

GNDAL19

GNDAL29

GNDAL34

GNDAK1

GNDAK2

GNDAK3

GNDAK6

GNDAK16

GNDAK26

GNDAH5

GNDAD18

GNDAD28

GNDAC3

GNDAH2 GNDAH1 GND

AJ33 GNDAJ23 GNDAJ13 GND

AJ5 GNDAJ4 GNDAJ3

GNDAC4

GNDAC5

GNDAC6

GNDAC8

GNDAC10

GNDAC15

GNDAC25

GNDAB1

GNDAB2

GNDAB5

GNDAB6

GNDAB7

GNDAB9

GNDAB11

GNDAB12

GNDAB22

GNDAB32

GNDAA3

GNDAA4

GNDAA5

GNDAA6

GNDAA8

GNDAA10

GNDAA12

GNDAA14

GNDAA19

GNDAA29

GNDAA34

GNDY1

GNDY2

GNDY5

GNDY6

GNDY7

GNDAH10

GNDAH20

GNDAH30

GNDAG3

GNDAG4

GNDAG5

GNDAG6

GNDAG7

GNDAG17

GNDAG27

GNDAF1

GNDAF2

GNDAF5

GNDAF6

GNDAF7

GNDY21GNDY19GNDY17GNDY15GNDY13GNDY11GNDY10GNDY9

GNDW3

GNDW4

GNDW5

GNDW6

GNDW8

GNDW10

GNDW12

GNDW14

GNDW16

GNDAF24 GNDAF14

GNDAF34

GNDAE3

GNDAE4

GNDAE5

GNDAE6

GNDAE7

GNDAE8

GNDAE9

GNDAE11

GNDAE21

GNDAE31 GND

V7GNDV6GNDV5GNDV2GNDV1GNDW33GNDW23GNDW22GNDW20GNDW18

GNDV9

GNDAD1

GNDAD2 GND

V11

GNDV13

GNDV15

GNDV17

GNDV19

GNDV21

GNDV30

GNDAD10 GND

AD9 GNDAD7 GNDAD6 GNDAD5

Cyclone V GT Power

5CGTFD9E5F35

U13L

Version = 0.2 Preliminary

GNDA9

GNDA19

GNDA29

GNDH8

GNDJ26

NC1AP3

NC2AN1

NC3AN2

NC4AN3

NC5AM1

NC6AM2

NC7AL1

NC8AL2

NC9AL3

NC10AL4

NC11AK4

NC12AH6

NC13AH7

NC14AG8

NC15AF8

NC16L10

NC17L26

NC18K9

NC19K27

NC20J6

NC21J7

NC22J8

NC23J9

NC24J27

NC25H6

NC26G6

NC27F31

NC28F32

NC29F33

NC30E32

NC31E33

NC32E34

NC33D6

NC34D31

NC35D32

NC36D34

NC37C2

NC38C19

NC39C33

NC40C34

NC41B33

NC42A30

NC43A31

NC44A32

NC45A33

R216100, 1%

BT1

Battery

2

POS2

NE

G1

3

POS3

Cyclone V GT Power

5CGTFD9E5F35

U13O

Version = 0.2 Preliminary

GNDU3

GNDU4

GNDU5

GNDU6

GNDU8

GNDU10

GNDU12

GNDU14

GNDU16

GNDU18

GNDU20

GNDU22

GNDU27

GNDT1

GNDT2

GNDT5

GNDT6

GNDT7

GNDT9

GNDT11

GNDT13

GNDT15

GNDT17

GNDT19

GNDT21

GNDT24

GNDT34

GNDR16

GNDM12

GNDM17

GNDM22

GNDR14 GNDR12 GNDR10 GND

R8 GNDR6 GNDR5 GNDR4 GNDR3

GNDM32

GNDL3

GNDL4

GNDL5

GNDL6

GNDL7

GNDL8

GNDL9

GNDL14

GNDL19

GNDL29

GNDL34

GNDK1

GNDK2

GNDK5

GNDK6

GNDK7

GNDK8

GNDK16

GNDK26

GNDJ3

GNDJ4

GNDJ5

GNDJ13

GNDJ23

GNDJ33

GNDH1

GNDH2

GNDH5

GNDH10

GNDH20

GNDH30

GNDG3

GNDR18

GNDR20

GNDR22

GNDR31

GNDP1

GNDP2

GNDP5

GNDP6

GNDP7

GNDP9

GNDP11

GNDP13

GNDP15

GNDP17

GNDP19

GNDF5GNDF2GNDF1GNDG27GNDG17GNDG7GNDG5GNDG4

GNDF14

GNDF24

GNDF34

GNDE2

GNDE3

GNDE4

GNDE5

GNDE11

GNDE21

GNDP28 GNDP21

GNDN3

GNDN4

GNDN5

GNDN6

GNDN8

GNDN10

GNDN11

GNDN16

GNDN18

GNDN20

GNDN25 GND

C4GNDC3GNDD33GNDD28GNDD18GNDD8GNDD5GNDD2GNDD1GNDE31

GNDC5

GNDM1

GNDM2 GND

C15

GNDC25

GNDB2

GNDB22

GNDB32

GNDB34

GNDA4

GNDM10 GND

M9 GNDM7 GNDM6 GNDM5

C188

47nF

Cyclone V GT Power

Core and Periphery

Configuration Power

Battery Back-up Power

PLL Analog Power

IO Pre-Driver Power2.5V, 3.0V, 3.3V

Auxiliary Power2.5V

1.2V-3.0V

1.1V

2.5V

1.8V-3.3V

5CGTFD9E5F35

U13I

Version = 0.2 Preliminary

VCCR19

VCCAA13

VCCY12 VCCY14

DNU4J24 DNU5J17

VCCPD3AAE15

VCCPD3AAE13

VCCPD3B4AAE17

VCCPD3B4AAF15

VCCPD3B4AAF16

VCCPD7A8AJ16VCCPD7A8AJ14VCCPD7A8AK20VCCPD7A8AK17VCCPD7A8AK15VCCPD7A8AJ22

VCCPD6AN26VCCPD6AT26VCCPD6AU26VCCPD6AP26

VCCPD5BV26

VCCPD3B4AAF20

VCCPD3B4AAF21

VCCPD3B4AAE22

VCCPD5AAA26VCCPD5AAB26

VCCPD5BW25

VCCPD7A8AJ19

VCCPD7A8AJ21

VCCPGMAF12

VCCPGMAD27

VCCPGMH11

VCCBATH9

VCC_AUXJ10

VCC_AUXK18

VCC_AUXK24

VCC_AUXAE24

VCC_AUXAE18

VCC_AUXAE12

VCCA_FPLLAC11

VCCA_FPLLM11

VCCT12

VCCR21

VCCN15

VCCN19

VCCN17

DNU3AF17

VCCT18

VCCT16

VCCT22

VCCT20

VCCU15

VCCN21

VCCP16

VCCP12

VCCP18 VCCP20 VCCP22

VCCR15

VCCR13

VCCU17 VCCU19 VCCU21

VCCY16 VCCY18

VCCW21

VCCW19

VCCW17

VCCW15

VCCW13

VCCV16

VCCV20

VCCV14

VCCV12

VCCV22

VCCV18

DNU2AG9

DNU1D3

DNU0D4

VCCR17

VCCT14

VCCU13

VCCA_FPLLAD26

VCCA_FPLLM26R253

10

Page 23: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 1 - DC Input & 12V, 3.3V Output

POWER LED

19VDC Input

This should be a copperpour not a trace.

SW2

LTC3855_S2PLTC3855_S2N

PG_12V

VFB2

INTVCC_1

SW1

VFB2

LTC3855_S1N

INTVCC_1

3.3V_SHDNn

DIFFOUT

12V_SHDNn

DIFFOUT

3.3V_MUXVCCP

3.3V_MUXVCC

3.3V_SHDNn12V_SHDNn

SW1

LTC3855_S1P

INTVCC_1

3.3V_ITEMP1

12V_ITEMP2

5.0V

12V_MUX

3.3V_MUX

DC_IN

3.3V_MUX

3.3V3.3V_OUT

3.3V_PCIE

3.3V_MUX

12V_OUT

12V_PCIE

12V

12V_MUX

DC_INPUT

DC_IN DC_IN

DC_IN

5.0V

3.3V_MUX

DC_IN

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B23 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B23 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B23 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C23222uF25V

R21511.3K

U44

LTC4357

OUT1

GND4VDD6

NC5

GATE3

IN2

EP_GND7

C41

47uF35V

drain-tabQ2RJK0301DPB

4

5

31 2

U41

LTC4357

OUT1

GND4VDD6

NC5

GATE3

IN2

EP_GND7

R1720.0K

C264

1000pF

gnd-pad

U40

LTC3855EUJ

TK/SS11 ITH12

VFB13

SGND14

VFB25

ITH26

TK/SS27

SENSE2+8

SENSE2-9

PGOOD217

NC18

PGOOD116

TG220

BOOST221

PGND222

BG223

EXTVCC24 INTVCC25

PGND128

SW219

DIFFP10

DIFFN11

DIFFOUT12

RUN213

ILIM114

ILIM215

VIN26

BG127

BOOST129

TG130

SW131

CLKOUT32 PHSASMD33 MODE/PLLIN34 FREQ35

ITEMP236

ITEMP137 RUN138

SENSE1+39

SENSE1-40

SGND241

U16FDMC8878

5

123

4C65

47uF35V

R2520.003

D39

MMBD1205

R1420.0K

C18722uF25V

R22111.5K

C21533pF

R194100K

D38CMDSH-3

D40CMDSH-3

drain-tabQ3RJK0301DPB

4

5

31 2

U19

FDMC8878

5

1 2 3

4

R192

DNI

C24627pF

R200

DNI

C207

0.1uF

L3

1.2uH1 2

R199

DNI

R2362.37K

V4

SENSE_PAD

RSNS1

SNS2

R271DNI

D31 LTC4352CDD

VIN1

CPO10

SOURCE12 GATE11 OUT

8

UV

3

OV

4S

TATU

S5

FAU

LT6

VCC2

REV7EP13GND9

R22610.0K

C21622uF25V

R31100K

R193 4.02K

V1

SENSE_PAD

RS

NS

1S

NS

2

drain-tabQ4RJK0305DPB

4

5

31 2

C214

270pF

C233 0.1uF

R2275.76K

U9FDMC8878

5

123

4

R21 100K

R2640.003

R20322.1K

R22510.0K

R224169.0K

R201

DNI

C21222uF25V

R191100K

SW2SW_SLIDE_DPDT

1

236

5

4

L4

1.2uH1 2

D21BLUE LED

C208

1000pF

U46

LTC4357

OUT1

GND4VDD6

NC5

GATE3

IN2

EP_GND7

R22845.3K

C213 0.1uF

R214215.0K

R1781.00k

C225

4.7uF

C18622uF25V

V2

SENSE_PAD

RSNS1

SNS2

drain-tabQ1RJK0305DPB

4

5

31 2

C248100uF

6.3v

C48

330uF

10V

V3

SENSE_PAD

RS

NS

1S

NS

2

R55DNI

J8CONN JACK PWR

3

21

C245

0.1uF

C3580.1uF

C32

68uF25V

C383

0.1uF C247100pF

R2202.55K

U17

FDMC8878

5

1 2 3

4

U14FDMC8878

5

123

4

D33 LTC4352CDD

VIN1

CPO10

SOURCE12

GATE11

OUT8

UV

3

OV

4S

TATU

S5

FAU

LT6

VCC2

REV7

EP13

GND9

R2130

C24422uF25V

Page 24: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 2 - 1.1V (C5_VCC)

FSW = 350kHz

CAD Note:Regulator input capsPlace near regulator controller

C5_VCC_SW

C5_VCC_REF

C5_VCC_TRACK

C5_VCC_SW

PGD_C5_VCC C5_VCC_BOOST

C5_VCC_INTVCC

C5_VCC_INTVCC

C5_VCC_INTVCC

C5_VCC_INTVCC

C5_VCC_INTVCC

C5_VCC_MODE

RUN_C5_VCC

C5_VCC_VOUT

C5_VCC_SNS_N

C5_VCC_SNS_P

C5_VCC_SNS_P

C5_VCC_SNS_N

PGOOD_C5_VCCC5_VCC

12V

12V

1.1V_REG_VCC

1.1V_REG_VCC

12V

3.3V

PGOOD_C5_VCC 25,26,27,28

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B24 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B24 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B24 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C87100UF6.3V

V36

SENSE_PAD

RS

NS

1S

NS

2

C50822uF25V1210

R70 0.001

D42

CMDSH-3

R87115K (1%)

V35

SENSE_PAD

RS

NS

1S

NS

2

C438270pF

C420

0.1uF

R99 21K (1%)

R10116.5K1%

L7 0.47uH

Isat = 20A

Wurth Elektronik744314047

1 2

R279

DNI

R78 0.001

R10213.7K

1%

U24B

LTC3613EWKH_6

PVIN72

PVIN83

PVIN94

PVIN105

PVIN116

PVIN127

PVIN138

PVIN149

SGND316

SGND417

SGND519

SGND628

SGND729 PGND9

37PGND838PGND739PGND640PGND541PGND442PGND343PGND244

SW945SW846SW747SW648SW549SW450SW351

NC52

PVIN653 PVIN554 PVIN455 PVIN356

SGND259

SW258

PVIN257

C10147pF

U24A

LTC3613EWKH_6

PGOOD13

SNS+14

SNS-15

VOUT18

VOSNS-20

VOSNS+21

TRACK/SS22

ITH23

VRNG24

RT25

RUN26

EXTVCC30

MODE/PLLIN31

INTVCC233

PGND136

NC27

SW110

PVIN11

BOOST11

SVIN132

SG

ND

12

INTVCC134

SW235

R310 10

R303 0

R294100K

C4164.7uF

C106

0.01uFR283DNI

C88100UF6.3V

C110

0.1uF

C69330uF6.3V

C419DNI

R28210.0K

C11622uF25V1210

R311 10C479

1.0nF

C48922uF25V1210

R8610.0K

R880

C11422uF25V1210

Page 25: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 3 - 1.2V (C5 GTB)

CAD Note:Regulator input capsPlace near regulator controller

Design Note:Ith is tied to INTVCC forinternal compensation

CAD Note:Overlap R?? & R??pads at 1 of the pinsPlace resistor & capnear pin 6

Design Note:tss = Css x 0.6V/2uARamp rate ~990us

Cad Note:Place output caps near inductor

Design Note:Prefer 0603 size cap25V rated voltage is sufficient

C5_GXB_RUN

C5_GXB_SVIN

C5_GXB_INTVCC

C5_GXB_FB

C5_GXB_FB

PGOOD_C5_GXB_1.2V

C5_GXB_SW

C5_GXB_BOOST

C5_GXB_SS

C5_GXB_RT

C5_GXB_ITHC5_GXB_INTVCC

PGOOD_C5_VCC

PGOOD_C5_VCC

C5_GXB_1.2V C5_VCCE_GXBL

3.3V

12V

C5_VCCL_GXBL

3.3V

PGOOD_C5_VCC24,26,27,28

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B25 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B25 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B25 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R8910K

C107 2.2uF

C4880.1uF50V

D43

CMDSH-3

C94 1.0nF

R92 DNI

C507

22uF

C1130.1uF25V

C11522uF25V1210

C95 3.3nF

L13 3A, 30 Ohm FB

C108 1uF

C11722uF25V1210

R9410.0K

EXPOSED PAD

LTC3605EUFU25

RT1

PHMODE2

MODE3

FB4

TRACK/SS5

ITH6

RU

N7

PGO

OD

8

VON

9

PG

ND

10

SW

11

SW

12

SW13

SW14

SW15

SW16

PVIN17

PVIN18

SV

IN19

BOO

ST20

INTV

CC

21

SG

ND

22

CLK

OU

T23

CLK

IN24

PG

ND

25

C99

39pF

R9310.0K

R100316.0K

C98 68pF

R84 DNI

R103 10

R307 0.003

R91 10.0K

C111

22uF

C506

22uF

R83 DNI

L8

1.2uHIsat = 11A

C112

22uF

R90 100K

Page 26: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 4 - 2.5V (C5 2.5V), 1.8V & 5.0V

Cad Note:Place capacitors near PVIN pins

Design Note:Ith is tied to INTVCC forinternal compensation

Cad Note:Place capacitors near inductor

C5_2.5V_RUNC5_2.5V_BOOST

C5_2.5V_RUN

C5_2.5V_ION

C5_2.5V_ITHC5_2.5V_INTVCC

C5_2.5V_ITH_CR

PGOOD_C5_2.5V

C5_2.5V_INTVCC

C5_2.5V_SW

C5_2.5V_VFB

C5_2.5V_VRNG

1.8V_ADJ

3.3V

12V

3.3V2.5V

C5_2.5V

C5_VCCIO_2.5V

2.5V 1.8V C5_VCCIO_1.8V12V

5.0V

PGOOD_C5_VCC24,25,27,28

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B26 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B26 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B26 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

D41CMDSH-3

R29910.0K

L5 3A, 30 Ohm FB

C37522uF25V1210

C42

10uF

C81

47UF

R298 DNI

C359

47UF

C100 1000pF

U21

LTC3608

SW8

SG

ND

10

SG

ND

14

SG

ND

15

PGOOD16

VRNG17

ITH18

FCB19

SG

ND

20

NC221

ION22

VFB23

NC324

NC425

SG

ND

26

SG

ND

27

NC528

EXTVCC29

SVIN30

INTVCC31

INTVCC32

SW33

PG

ND

34

PG

ND

35

PG

ND

36

PG

ND

37

PG

ND

38

PG

ND

39

PG

ND

40

SW41

SW42

SW43

SW44

SW45

SW46

SW47

PV

IN_E

PA

D53

SG

ND

_EP

AD

54

SW_EPAD55

NC19

BOOST11

RUN/SS12

VON13

PV

IN1

PV

IN2

PV

IN3

PV

IN4

PV

IN5

PV

IN6

PV

IN7

PV

IN48

PV

IN49

PV

IN50

PV

IN51

PV

IN52

R219

499K

C374

47UF

C68

47UF

R64187

C424 0.22uF10V

R53 0.003

C442 15pF

C74

1uF

C85

2.2uF

C43

1uF

C7622uF25V1210

C49

2.2uF

R300 100K

C77

10uF

R95 0

C441 470pF

R29775K

C423 4.7uF

U10

LT3085EDCB

OUT1

IN6 IN5 OUT

2Vcontrol4

EP_GND7

SET3

C4610pF

R2959.53K

R96DNI

R29630.1K

R305 21K (1%)

L6 0.47uH

Isat = 20A

Wurth Elektronik744314047

1 2

C387

22uF

R79 0.003U18

LT3022EDHC

NC11

NC38

AGND7

VOUT4

SHDN9

EP_GND17

VIN14

NC22

ADJ5

AGND6

NC516 NC415

VIN13

PGND11PGND10

VOUT3

VIN12

R69 1.50K

Page 27: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 5 - 1.5V, VTT_DDR3, VREF_DDR3, ENET_DVDD

CAD Note:Regulator input capsPlace near regulator controller

Design Note:Ith is tied to INTVCC forinternal compensation

CAD Note:Overlap R?? & R??pads at 1 of the pinsPlace resistor & capnear pin 6

Design Note:tss = Css x 0.6V/2uARamp rate ~990us

Cad Note:Place output caps near inductor

Design Note:Prefer 0603 size cap25V rated voltage is sufficient

DDR3 VTT, VREF

DDR3 VTT, VREF

1.5V_RUN

1.5V_SVIN

1.5V_INTVCC

1.5V_FB

1.5V_FB

PGOOD_1.5V

1.5V_SW

1.5V_BOOST

1.5V_SS

1.5V_RT

1.5V_ITH1.5V_INTVCC

DVDD_1.0V_ADJ

1.5V_DDR3 C5_VCCIO_1.5V

3.3V

12V

3.3V

1.5V ENET_DVDDVREF_DDR3A VTT_DDR3A

1.5V_DDR3

3.3V

VREF_DDR3B

3.3V

1.5V_DDR3

VTT_DDR3B

5.0V

3.3V

1.5V

PGOOD_C5_VCC24,25,26,28

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B27 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B27 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B27 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

C153

22uF

C120

1.0nF

C295

1.0nF

C2 3.3nF

C249

0.1uF

C15122uF25V1210

C31

10uF

U39

LTC3025-1

BIAS1

GND2

ADJ5

OUT4

SHDN6

EP_GND7

IN3

C543

10uF

C56

10uF

C34

2.2uF

C539

10uF

D36

CMDSH-3

C360

10uF

R6 100K

EXPOSED PAD

LTC3605EUFU1

RT1

PHMODE2

MODE3

FB4

TRACK/SS5

ITH6

RU

N7

PGO

OD

8

VON

9

PG

ND

10

SW

11

SW

12

SW13

SW14

SW15

SW16

PVIN17

PVIN18

SV

IN19

BOO

ST20

INTV

CC

21

SG

ND

22

CLK

OU

T23

CLK

IN24

PG

ND

25

C388

10uF

C1440.1uF50V

C425

10uF

C118

10uF

R10267K

C203

1uF

C2122uF25V1210

C1 4.7nF

R37 750

R197

10.0K

C33

22uF4V

C26

22uF

R15 10

U53

TPS51200

VIN10

EN7

PGOOD9

REFOUT6

GN

D_P

AD

11

PG

ND

4

GN

D8

VLDOIN2

REFIN1

VO3

VOSNS5

R910.0K

C529

0.1uF

C204

10uF C172

22uF

C538

10uF

C542

10uF

R4 16.9K

R342 10.0K

C540

10uF

C11 1uF

C4

39pF

C29

1uF

L2

1.2uHIsat = 11A

R34810.0K

R2 0

C25

22uF

C541

10uF

R34310.0K

C51

1uF

C152

22uF

R3DNI

R7 DNI

R815.0K

C119

1uF

C55

10uF

C1430.1uF25V

R24310.0K

C184

2.2uF

U43

TPS51200

VIN10

EN7

PGOOD9

REFOUT6

GN

D_P

AD

11

PG

ND

4

GN

D8

VLDOIN2

REFIN1

VO3

VOSNS5

C335

10uF

R196 27.4K

U7

LT3022EDHC

NC11

NC38

AGND7

VOUT4

SHDN9

EP_GND17

VIN14

NC22

ADJ5

AGND6

NC516 NC415

VIN13

PGND11PGND10

VOUT3

VIN12

R36187

C435

10uF

C10 2.2uF

R237 10.0K

C3 56pF

R25010.0K

R174 0.003

Page 28: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 6 - LTC3605 VAR

CAD Note:Regulator input capsPlace near regulator controller

Design Note:Ith is tied to INTVCC forinternal compensation

CAD Note:Overlap R?? & R??pads at 1 of the pinsPlace resistor & capnear pin 6

Design Note:tss = Css x 0.6V/2uARamp rate ~990us

Cad Note:Place output caps near inductor

Design Note:Prefer 0603 size cap25V rated voltage is sufficient

1.2V1.5VJUMPER 3-4

Setting

JUMPER 1-2

JUMPER 5-6

VCCIO HSMB SELECT

1.8VNO JUMPER

C5_VCCIO_VAR Voltage

2.5V

C5_VAR_RUN

C5_VAR_SVIN

C5_VAR_INTVCC

C5_VAR_FB

C5_VAR_FB

PGOOD_C5_VAR

C5_VAR_SW

C5_VAR_BOOST

C5_VAR_SS

C5_VAR_RT

C5_VAR_ITHC5_VAR_INTVCC

PGOOD_C5_VCC

VCCIO_VADJ C5_VCCIO_VAR

3.3V

12V

3.3VVCCIO_VADJ

PGOOD_C5_VCC24,25,26,27

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B28 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B28 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B28 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

R11 54.9K

C522uF25V1210

R16 10

D37

CMDSH-3C12 1uF

R32 14.0K 1%

R34 0

C7

22uF

C137

22uF

C16 2.2uF

R123 0.003

R2831.6K

R5 28.7K

C136

22uF

L1

1.2uHIsat = 11A

J17

DNI

1 23 45 6

C1420.1uF25V

R29 DNI

C27 3.3nF

EXPOSED PAD

LTC3605EUFU2

RT1

PHMODE2

MODE3

FB4

TRACK/SS5

ITH6

RU

N7

PGO

OD

8

VON

9

PG

ND

10

SW

11

SW

12

SW13

SW14

SW15

SW16

PVIN17

PVIN18

SV

IN19

BOO

ST20

INTV

CC

21

SG

ND

22

CLK

OU

T23

CLK

IN24

PG

ND

25

R2710.0K

R26169.0K

C1410.1uF50V

C6

22uF

R33DNI

C22

39pF

R1 14.7K

R30 100K

C23 10pF

C13822uF25V1210

C28 220pF

Page 29: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Power 6 - Power Monitor

SENSE5_CSn

SENSE5_SDO

SENSE5_SDO

SENSE5_SDI

SENSE5_SDI

SENSE5_SCK

SENSE5_SCK

SENSE5_CSn

C5_VCCIO_1.5V_N

C5_VCCIO_1.5V_P

C5_VCCIO_2.5V_N

C5_VCCIO_2.5V_P

C5_VCCIO_1.8V_N

C5_VCCIO_1.8V_P

C5_VCC_N

C5_VCC_P

C5_VCCEL_GXBL_N

C5_VCCEL_GXBL_P

C5_VCCEL_GXBL_NC5_VCCEL_GXBL_P

TSENSE_FAN_CNTL

C5_VCC_NC5_VCC_P

C5_VCCIO_2.5V_NC5_VCCIO_2.5V_P

C5_VCCIO_1.8V_NC5_VCCIO_1.8V_P

C5_VCCIO_1.5V_NC5_VCCIO_1.5V_P

C5_VCCIO_VAR_N

C5_VCCIO_VAR_P

C5_VCCIO_VAR_PC5_VCCIO_VAR_N

5.0V

5.37V_MONITOR

5.0V 2.5V

2.5V

C5_VCCIO_2.5V

1.8V

C5_VCCIO_1.8V

1.5V_DDR3

1.1V_REG_VCC

C5_VCC

C5_VCCE_GXBL

2.5V

C5_GXB_1.2V

C5_VCCIO_1.5V

12V

5.0V 2.5V

5.37V_MONITOR12V

VCCIO_VADJ

C5_VCCIO_VAR

SENSE_SCK 15SENSE_SDI 15

SENSE_CSn 15SENSE_SDO 15

OVERTEMP 15

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B29 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B29 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B29 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

V38

SENSE_PADRSNS

1SNS

2

C52

10uF

R66

10K

V40

SENSE_PADRSNS

1SNS

2

R71 10.0K

V6

SENSE_PADRSNS

1SNS

2

C700.1uF

U42

LT3009xDC

ADJ/NC1

OUT12

OUT23

SHDN4

VIN5

GND6

GND_TAB7

V39

SENSE_PADRSNS

1SNS

2

V43

SENSE_PADRSNS

1SNS

2

Q5

FDV305N

R670

B2

FAN_2pin_Conn

C78

1uF

V18

SENSE_PADRSNS

1SNS

2

V19

SENSE_PADRSNS

1SNS

2

V44

SENSE_PADRSNS

1SNS

2

J15

22_23_2021

12

U45

LTC2418

CH021

CH122

CH223

CH324

CH425

CH526

CH627

CH728

CH81

CH92

CH103

CH114

CH125

CH136

CH147

CH158

COM10

GND15

VCC9

REF+11

REF-12

F019

CSn16SCK18SDI20SDO17

NC113

NC214

C6610uF

V42

SENSE_PADRSNS

1SNS

2

R233 4.70M

U48

MAX3378

VL1

IO VL12

IO VL23

IO VL34

IO VL45

NC16

GND7

VCC14

IO VCC113

IO VCC212

IO VCC311

IO VCC410

NC29

/TS8

R65

10K

R232590K

R58DNI

V41

SENSE_PADRSNS

1SNS

2

V37

SENSE_PADRSNS

1SNS

2

V5

SENSE_PADRSNS

1SNS

2

R56

10K

R57

10K

R540

C57

10uF

C82

0.1uF

C83

0.1uF

Page 30: Cyclone V GT Development Kit Board

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Cyclone V GT DecouplingC5_VCC

VREF_DDR3AC5_VCCL_GXBL

C5_VCCIO_1.5V

C5_VCCIO_2.5V

C5_VCCE_GXBL

C5_2.5V

C5_VCCIO_1.8VVREF_DDR3B

C5_VCCIO_VAR

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B30 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B30 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

Title

Size Document Number Rev

Date: Sheet of

B

Cyclone V GT FPGA Development Kit Board

B30 30Thursday, May 02, 2013

150-0321004-B1 (6XX-44179R)

Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121Copyright (c) 2013, Altera Corporation. All Rights Reserved.

SCREW5

C198

47nF

SCREW6

C320

0.01uF

C378

1uF

C275

0.1uF

C349

0.1uF

C279

47nF

C398

4.7uF

C231

0.47uF

C330

0.01uF

SCREW2

C102

330uF10V

C277

47nF

C254

0.22uF

C329

0.22uF

STANDOFF1

C379

0.1uF

C230

0.01uF

C338

0.01uF

C331

4.7uF

C302

22nF

C195

0.22uF

C385

0.1uF

C178

4.7uF

C371

22nF

C333

0.01uF

C180

1uF

C404

4.7uF

C257

4.7uF

C243

22nF

C17

330uF4V

C310

47nF

C40

330uF10V

C286

47nF

C408

47nF

C344

0.01uF

C229

0.1uF

C201

22nF

C324

0.47uF

C292

22nF

C239

0.01uF

C228

0.47uF

C176

0.01uF

C199

47nF

C429

100uF

C177

0.47uF

C255

0.22uF

C194

1uF

C405

0.1uF

C223

100uF

C356

22nF

C92

330uF4V

C339

0.01uF

C340

0.01uF

C253

0.1uF

C171

0.01uF

C258

0.01uF

C397

22nF

C369

0.1uF

C64

220uF

C306

47nF

C308

47nF

C235

100uF

C309

0.1uF

C282

0.22uF

C285

2.2uF

C291

0.01uF

C350

0.47uF

C170

4.7uF

C376

4.7uF

C24

330uF10V

STANDOFF4

C192

22nF

C357

0.01uF

C293

0.01uF

C315

0.1uF

C283

47nF

C396

4.7uF

C168

47nF

C240

0.01uF

C370

1uF

C227

4.7uF

C401

0.1uF

C237

4.7uF

C342

0.01uF

C226

330uF4V

C162

22nF

C175

22nF

C317

0.01uF

C197

47nF

C303

0.1uF

C14

100uF

C259

22nF

C400

4.7uF

C323

47nF

C241

0.01uF

C380

22nF

C395

22nF

C384

100uF

C325

0.1uF

C236

0.22uF

C278

1uF

C311

1uF

C348

0.1uF

C337

100uF

C347

100uF

C352

47nF

C251

0.1uF

C252

0.01uF

C261

4.7uF

C273

100uF

C326

0.47uF

STANDOFF2

C386

22nF

C280

0.22uF

C30

330uF4V

C409

4.7uF

C304

0.1uF

C403

0.1uF

C368

0.1uF

C428

100uF

C290

47nF

SCREW3

C193

0.22uF

C75

220uF

C164

0.01uF

C407

4.7uF

C242

22nF

C327

0.1uF

C179

1uF

C353

22nF

C313

47nF

C287

47nF

C256

47nF

C289

0.1uF

C341

0.01uF

C411

4.7uF

C167

47nF

C354

22nF

C406

47nF

C274

0.01uF

C189

0.01uF

C165

0.01uF

C305

0.22uF

C427

100uF

C54

220uF

C328

0.01uFSCREW4

C169

0.1uF

C202

4.7uF

C276

0.01uF

C183

0.01uF

C166

47nF

C39

220uF

C399

1uF

C181

0.1uF

C367

0.01uF

C314

1uF

C402

22nF

PCB1

C191

22nF

C200

4.7uF

SCREW1

C224

4.7uF

C430

100uF

C163

22nF

C410

22nF

C355

1uF

C93

220uF

C307

4.7uF

C322

47nF

STANDOFF3

C281

47nF

C343

0.01uF

C284

0.1uF

C182

0.1uF

C332

0.01uF

C209

0.22uF

C316

0.01uF

C312

47nF

C351

0.1uF

C321

0.1uF

C288

22nF

C238

0.01uF

C260

0.47uF

C412

4.7uF

C196

47nF

C377

47nF

C190

22nF