CVE_FabioValente_HW
3
Curriculum Vitae Fabio Valente PERSONAL INFORMATION Fabio Valente Via delle Sorgenti 4, Santa Maria Hoe’ (LC), Italy 347-8930543 [email protected] Sex M | Date of birth 11/08/1967 | Nationality Italian JOB APPLIED FOR POSITION PREFERRED JOB STUDIES APPLIED FOR Algorithm design engineer WORK EXPERIENCE 2004 –Nov 2014 Project and team leader – ASIC/FPGA lab Alcatel Lucent Italy ▪Definition of architecture for data cards on TSS/PSS products in ALU OPTIC division ▪FPGA architecture definition and implementation - RTL development (SystemVerilog, VHDL) - Testbench for RTL validation (SV,UVM) - Testbench for QoS architecture validation (C-language,ns2,OPNET) - Validation of FPGA functionalities in data cards ▪Team activity coordination ▪Coordination of activities with CEFRIEL and Padua University (masters on networking) Business or sector OPTIC division 1997 –2004 Senior FPGA designer – ASIC/FPGA lab Alcatel Italy ▪Definition of architecture for data cards on OMSN products in Alcatel OPTIC division ▪FPGA architecture definition and implementation - RTL development (Verilog) - Testbench for RTL validation (Verilog, C-language) - Testbench for QoS architecture validation (C-language,ns2,OPNET) - Validation of FPGA functionalities in data cards Business or sector OPTIC division 1992 –1997 firmware designer – R&D lab Alcatel Italy © European Union, 2002-2013 | http://europass.cedefop.europa.eu Page 1 / 3
-
Upload
fabio-valente -
Category
Documents
-
view
45 -
download
0
Transcript of CVE_FabioValente_HW
Curriculum Vitae Fabio Valente
PERSONAL INFORMATION Fabio Valente
Via delle Sorgenti 4, Santa Maria Hoe’ (LC), Italy
347-8930543
Sex M | Date of birth 11/08/1967 | Nationality Italian
JOB APPLIED FORPOSITION
PREFERRED JOBSTUDIES APPLIED FOR
Algorithm design engineer
WORK EXPERIENCE
2004 –Nov 2014 Project and team leader – ASIC/FPGA labAlcatel Lucent Italy
▪ Definition of architecture for data cards on TSS/PSS products in ALU OPTIC division▪ FPGA architecture definition and implementation
- RTL development (SystemVerilog, VHDL)- Testbench for RTL validation (SV,UVM)- Testbench for QoS architecture validation (C-language,ns2,OPNET)- Validation of FPGA functionalities in data cards
▪ Team activity coordination▪ Coordination of activities with CEFRIEL and Padua University (masters on networking)
Business or sector OPTIC division
1997 –2004 Senior FPGA designer – ASIC/FPGA labAlcatel Italy
▪ Definition of architecture for data cards on OMSN products in Alcatel OPTIC division▪ FPGA architecture definition and implementation
- RTL development (Verilog)- Testbench for RTL validation (Verilog, C-language)- Testbench for QoS architecture validation (C-language,ns2,OPNET)- Validation of FPGA functionalities in data cards
Business or sector OPTIC division
1992 –1997 firmware designer – R&D labAlcatel Italy
▪ firmware development for a HDTV codec running on Texas Instrument DSP MVP ▪ Definition and implementation of the algorithms for speech recognition in a noisy car
environment
Business or sector Central Research division
EDUCATION AND TRAINING
1987-1992 Laurea degree in Electronic EngineeringPadua Univeristy
PERSONAL SKILLS
© European Union, 2002-2013 | http://europass.cedefop.europa.eu Page 1 / 2
Curriculum Vitae Replace with First name(s) Surname(s)
Mother tongue(s) Italian
Other language(s) UNDERSTANDING SPEAKING WRITING
Listening Reading Spoken interaction Spoken production
Replace with language Good Good Good Good GoodEnglish
Replace with language Basic Basic Basic Basic BasicSpanish
Communication skills ▪ good communication skills gained through my experience as team manager in Alcatel Lucent
Organisational / managerial skills ▪ leadership (I was responsible for a team of 4 people)
Job-related skills
Computer skills ▪ good command of Microsoft and Linux environment▪ C-language▪ Verilog/System Verilog for RTL design and validation, VHDL for RTL design
Other skills
Driving licence ▪ B
ADDITIONAL INFORMATION
PublicationsPresentations
ProjectsConferences
SeminarsHonours and awards
MembershipsReferences
▪ PATENT: OUTPUT DRIVEN GLOBAL SCHEDULING SCHEME (Cucchi Silvio, Valente Fabio, POST Georg,NOIRIE Ludovic)
▪ PATENT: CENTRAL SCHEDULER FOR TIME-SLOTTED PACKET SWITCH MATRIX (Cucchi Silvio, Valente Fabio, POST Georg,NOIRIE Ludovic)
▪ PATENT: MOTION ESTIMATION IN VIDEO CODING (Cucchi Silvio, Valente Fabio)▪ PUBLICATION: QoS guarantees on DiffServ architectures with GPS-like scheduling
disciplines (IEEE GLOBECOM 2007)▪ PUBLICATION: Differentiated services multicast in IP networks (ICN 2004)▪ PUBLICATION: Traffic Engineering based on distributed CAC in diffserv architecture ( EISTA
2004)▪ PUBLICATION: Voice controlled mobile phone for car environment ( Eusicpo 1996)▪ PUBLICATION: SW implementation of a real time HDTV MPEG2 encoder ( HDTV 1997
Montreux)
ANNEXES
© European Union, 2002-2013 | http://europass.cedefop.europa.eu Page 2 / 2
