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DIGITAL CIRCUITSParameters of the integrated logic circuits

Static transfer characteristic

Noise margins

Fan-out & fan-in

Propagation time

Power Dissipation

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Static Transfer Characteristic

Output voltage variation function of input dcvoltage

Cannt be defined an unique voltage value forlogic 1 or 0

Transfer characteristic isnt unique characteristic bounded by two limit curves

to each input or output variable, two voltageintervals (domains) will be associated: allowed,and respectively guaranteed

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Static Transfer Characteristic for an Inverter

Four

voltageranges

Two for

inputs Two for

outputs

Defined byeightvoltage

values

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Input/Output voltage values VILmin minimum voltage level for logic 0 at input

VILmax

- maximum voltage level for logic 0 at input

VIHmin - minimum voltage level for logic 1 at input

VIHmax - maximum voltage level for logic 1 at input

VOLmin - minimum voltage level for logic 0 at output

VOLmax - maximum voltage level for logic 0 at output VOHmin - minimum voltage level for logic 1 at output

VOHmax - maximum voltage level for logic 1 at output

Index meaningI input

O output

L lowlogic 0

H - highlogic 1

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Defining the working regions

A logic circuit will work properly if the input voltagelevels will have admitted values (work in allowed

regions) Obtained output voltage levels will be into guaranteed

regions

Considering that output voltage will become inputvoltage for driven circuit(s), have five working regions: Normal working region for logic 0 and logic 1

Working region in presence of noise signals for logic 0 and

respectively 1 Transitory region

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Normal working region (no noise signals)

For low input voltage level (L), between

values VIL2 - VIL1 For high input voltage level (H) between

values VIH2 - VIH1

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Working region when noise signals apply

For low input voltage level (L), between

values VILmax VILmin For high input voltage level (H) between

values VIHmax - VIHmin

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Transitory region For input voltage levels between VIHmin

VILmax Those input voltages driving circuit from one

stable state to the other

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Noise margins

Noise (immunity) margins: stability at static

perturbations

the noise margin is the peak amount of spurious or"noise" voltage that may be superimposed on a weak

gate output voltage signal before the receiving gatemight interpret it wrongly

Guaranteed noise margin for a logic state is given by

difference between guaranteed output voltage level ofthe driving circuit and the worst case for the inputvoltage level accepted for that state by the driven

circuit

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Guaranteed noise margins (manufacturers

specifications)

For logic 0 state:

ML=VILmax-VOLmax For logic 1 state:

MH=VOHmin-VIHmin

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Example for TTL family

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Fan-out and Fan-in

The input of a circuit is a load for its drivercircuit

For a logic circuit generates guaranteed outputvoltage levels is a must to be driven at inputswith corresponding current levels

For circuit interconnection, important to designthe output current of the driving circuit, and to

consider the sum of input currents of the drivencircuits

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Fan-in factor for logic circuits

Fan-in (FI) and Fan-out (FO) factors are definedbased on some current values, thosecorrespondind to allowed input voltages and

respectively to guaranteed output voltages, inthe worst case: IILmax, IIHmin, IOLmax i IOHmin

For any integrated circuits family, a basic

(fundamental) gate is defined, and the fan-in/fan-out values for the rest of circuits are definedas multiples of the values for that basic gate

For an input, the FI value means the number N(N>1) of standard inputs (i.e. of basic gate)equivalent to that input: FI=N

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Fan-out factor for logic circuits

),min(,, HLIH

OH

H

IL

OL

L FOFOFOI

IFO

I

IFO =

=

=

When interconnecting logic circuits (from afamily), the following relations must be satisfied(associate with the worst case):

==

11

,i

n

IHOH

i

n

ILOL IIII

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Propagation Time

Propagation times (delay) (tpHL si tpLH) are defined for halves theinput/output signal amplitudes

Average propagation time: tpd=(tpHL+tpLH)/2

Important parameter for any circuit, giving sign of performance

Raising-up and fall-downtimes (tr , tf) are definedusing ratios of signalamplitude (0.1 and 0.9)

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Power Dissipation

Parameter depending on:

Power supply voltage (VCC

);

Absorbed currents from VCC whenoutput is logic 1 (ICCH), or 0 logic (ICCL);

Output current on shortcircuit (IOS);

Average power consumption (Pm);

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Average power dissipation on cc

V2I+

I=2 P+

P=P CCCCLCCHLH

CC

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Power dissipation on ac

Important power component, due to charging/discharging of stray output capacitances Cp

Power consumption during the switching

regime:

VCP CCPC f2

=

f switching frequency

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Total power dissipation

VCVIIPPP CCPCCCCLCCHC fCCm 22 ++

=+=

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TTL Logic Integrated Circuits

General considerations TTL standard series

TTL basic (fundamental) gateCircuit description

Gate operation

Parameters of TTL basic gate

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General Considerations

TTL (Transistor-Transistor-Logic)

Family with a lot of circuit series,developed based on a trade-off between

propagation speed and power dissipation Standard, high-speed (H), Low power (L),

Schottky (S)

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Gate operation for one input 0

T1 saturated, voltage from

T1 collector lowers,

transistor T2 off Low voltage level from T2

emitter drives T3off

High potential of T2collector opens transistorT4

UR2 low, UBE(T4)+UD1,5V,Ue>3,4V corresponding tologic level "1"

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Gate operation when both inputs at logic 1

T1 base-emitter junctionsreverse biased (reverse activeregion)

T1 base-collector junction andbase-emitter junctions of T2 &T3 make a chain of opendiodes (forward biased by R1from power supply), T2 & T3

saturated T4 off due to base potential,

lower than emitters, due topresence of diode D

Ue=UCES(T3) corresponding tologic "0"

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Transistors T4 & T3 switch in counter-time,making R

4being low (130), building a

low output impedance and a small timeconstant for charge/discharge of output

stray capacitances

BA=Ue *

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Logic Levels

VILmax = 0.8 V

VIHmin = 2 V

VOLmax = 0.4 V

VOHmin = 2.4 V

VT = 1.3V, threshold voltage, same

value for input and output voltages

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Noise Margins

Guaranteed values

ML = VILmax VOLmax = 0.8V 0.4V = 0.4VMH = VOHmin VIHmin = 2.4V 2V = 0.4V

Real values

ML = VT VOL = 1.3V 0.2V = 1.1V

MH = VOH VT = 3.5V 1.3V = 2.2V

It implies that prefered output idle state being '1'logic, and switching command being zeroactive, i.e. a signal going from high to low

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Input & output currents

By convention: positive value if gate

sinks current and negative value if gategenerates currents

IIH

= 40 A

IIL = -1,6 mA

IOH

= -800 A

IOL = 16 mA

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Fan-in/ fan-out

FIL = 1, IIL = - 1,6mA

FIH = 1, IIH = 40A

10),min(,2040

800,10

6.1

16===

==

=

= HLH

IL

OL

L FOFOFOA

AFO

mA

mA

I

IFO

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Static transfer characteristic

0V

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Input Characteristics

Vi < 0,8V

Vi grows over 0,8V, Ii lowersin absolute value

Vi > 1,3V, Ii tends abruptlytoward 0

Vi= 1,7V, I

i=0

Vi > 2 2,25V, Ii 28A

R

V-V-V=I

1

IBE(T1)CC

I

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Output Characteristics

VOL = f(IOL) IOL depends on T3 base

current, wich depends on T2emitter current, as:

R

V-V-V=I

2

CEs(T2)BE(T3)CC

C(T2)

R

V-V-V-V=I

1

BE(T3)BE(T2)BC(T1)CC

B(T2)

IE(T2) = IB(T2) + IC(T2) =3,2mA

R

V-I=I-I=I

3

BE(T3)

E(T2)3E(T2)B(T3)

T3 saturated, N=20, output current:IOL = NIB(T3) = 49mA

IOL

O Ch i i

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Output Characteristics

VOH = f(IOH) Figure below presents in positive domainVOH=f(IS) characteristics, where load current ISis considered IS= -IOH

T4 on, tending toward saturation

T4 when in forward active region, segment 1,VOH and IS are in relation:

IS

VOH= 3,7 - 32IS T4 saturated, curve 2, relation becomes:

V-V-1+

IR-V=V DBE(T4)

N

S2CCO

R

V-V-V-V+

R

V-V-V-V=I+I=I=I

4

CE(T4)DOCC

2

BE(T4)DOCC

C(T4)B(T4)E(T4)S

VO 4,5 - ISR4 Curves 1 and 2 cross eachother at IS 5mA

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Power dissipation

ICCH=IR1=(VCC-VB(T1))/R11mA

ICCL=IE(T2)=IC(T2)+IB(T2)=(VCC - VC(T2))/R2+(VCC-VB(T1))/R13,3mA

PCC 10mW

PC=CpVCC2f

Cp=15pF; f=1MHz, PC0,4mW; f=20MHz, PC7,5mW

Besides the two components PCC and PC, there is another, dueto simultaneous conduction of transistors T3 and T4. This extra

power consumption PDS has the formula:

V2I+I=P CC

CCLCCHCC

)

T

t

2

I+

T

t

2.2

I(V=P

rCCmaxcCCmaxCCDS

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P ti D l

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Propagation Delay

Given by charging/discharging times of stray capacitance fromgates output and by switching times of transistors

tpHL = tc1 + tdes

tpLH = tc2 + tinc tpd = (tpHL + tpLH)/2

Switching times: tc1 = 5ns and tc2 = 8ns

Charging/discharging times of stray capacitances:

Formula for tinc, short-circuit current value is considered IOS For IOS = 18mA results tinc = 2.5ns

Calculated values: tpHL = 8ns i tpLH = 10.5ns

Data book values: tpHL = 8ns and tpLH= 12ns, resulting tpd = 10ns

I

V-VC=t

OL

OLOHpdes

I

V-VC=t

OH

OLOHpinc

P d P bl

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Proposed Problems

Find out the maximum value of a resistor may be connectedbetween two standard TTL gates, without modifying the circuitbehavior. How this resistor is affecting the noise margins?

Design a circuit based on a NAND TTL standard gate, able to

drive a LED. For the LED, following values are considered:VLED=1,6V and ILED=10mA.

Design a circuit based on a NOR TTL standard gate, able todrive a LED. For the LED, following values are considered:

VLED=0,65V and ILED=20mA. Design a positive edge detector circuit, using NAND gates.

If a pulse train signal is propagating through a NAND gate, howthis influences the filling factor of one pulse? But if propagatingthrough two NAND gates? Input signal has a 20MHz frequencyand a filling factor of .