CS 201The Memory Hierarchy

Gerson RobboyPortland State University

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memory hierarchy overview(traditional)•• CPU registersCPU registers•• main memory (RAM)main memory (RAM)•• secondary memory (DISK)secondary memory (DISK)•• why? what is different between these entities?why? what is different between these entities?•• what role does caching play?what role does caching play?•• how many different kinds of secondary memory arehow many different kinds of secondary memory are

there these days?there these days?•• can we find out how fast these secondary memoriescan we find out how fast these secondary memories

are?are?•• note: this stuff is mostly an architectural overview -note: this stuff is mostly an architectural overview -

when does it impact programming?when does it impact programming?

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Random-Access Memory (RAM)Key featuresKey features

RAM is packaged as a chip. Basic storage unit is a cell (one bit per cell). Multiple RAM chips form a memory.

Static RAM (Static RAM (SRAMSRAM)) Each cell stores bit with a six-transistor circuit. Retains value indefinitely, as long as it is kept powered. Relatively insensitive to disturbances such as electrical noise. Faster and more expensive than DRAM.

Dynamic RAM (Dynamic RAM (DRAMDRAM)) Each cell stores bit with a capacitor and transistor. Value must be refreshed every 10-100 ms. Sensitive to disturbances. Slower and cheaper than SRAM.

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SRAM vs DRAM Summary

Tran. Accessper bit time Persist? Sensitive? Cost Applications

SRAM 6 1X Yes No 100x cache memories

DRAM 1 10X No Yes 1X Main memories,frame buffers

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Typical Bus Structure ConnectingCPU and MemoryA A busbus is a collection of parallel wires that carry is a collection of parallel wires that carry

address, data, and control signals.address, data, and control signals.Buses are typically shared by multiple devices.Buses are typically shared by multiple devices.

mainmemory

I/O bridgebus interface

ALU

register file

CPU chip

system bus memory bus

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Disk GeometryDisks consist of Disks consist of plattersplatters, each with two , each with two surfacessurfaces..Each surface consists of concentric rings called Each surface consists of concentric rings called trackstracks..Each track consists of Each track consists of sectorssectors separated by separated by gapsgaps..

spindle

surfacetracks

track k

sectors

gaps

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Disk Geometry (Muliple-Platter View) Aligned tracks form a cylinder. Aligned tracks form a cylinder.

surface 0surface 1surface 2surface 3surface 4surface 5

cylinder k

spindle

platter 0

platter 1

platter 2

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Disk CapacityCapacity:Capacity: maximum number of bits that can be stored. maximum number of bits that can be stored.

Vendors express capacity in units of gigabytes (GB), where 1 GB =10^9.

Capacity is determined by these technology factors:Capacity is determined by these technology factors: Recording density (bits/in): number of bits that can be squeezed

into a 1 inch segment of a track. Track density (tracks/in): number of tracks that can be squeezed

into a 1 inch radial segment. Areal density (bits/in2): product of recording and track density.

Modern disks partition tracks into disjoint subsets called Modern disks partition tracks into disjoint subsets called recordingrecordingzoneszones Each track in a zone has the same number of sectors, determined

by the circumference of innermost track. Each zone has a different number of sectors/track

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Exercise: Computing Disk CapacityWhat is the capacity of a disk with:What is the capacity of a disk with:

512 bytes/sector 300 sectors/track (on average) 20,000 cylinders 5 platters

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Disk Operation (Single-Platter View)

The disksurfacespins at a fixedrotational rate

spindle

By moving radially, the armcan position the read/writehead over any track.

The read/write headis attached to the endof the arm and flies over the disk surface ona thin cushion of air.

spindle

spindle

spin

dlespindle

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Disk Operation (Multi-Platter View)

arm

read/write heads move in unison

from cylinder to cylinder

spindle

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Disk Access TimeAverage time to access some target sector approximated by :Average time to access some target sector approximated by :

Taccess = Tavg seek + Tavg rotation + Tavg transfer

Seek timeSeek time ( (Tavg Tavg seek)seek) Time to position heads over cylinder containing target sector. Typical Tavg seek = 9 ms

Rotational latencyRotational latency ( (TavgTavg rotation) rotation) Time waiting for first bit of target sector to pass under r/w head. Tavg rotation = 1/2 x 1/RPMs x 60 sec/1 min

Transfer timeTransfer time ( (Tavg Tavg transfer)transfer) Time to read the bits in the target sector. Tavg transfer = 1/RPM x 1/(avg # sectors/track) x 60 secs/1 min.

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Disk Access Time ExampleGiven:Given:

Rotational rate = 7,200 RPM Average seek time = 9 ms. Avg # sectors/track = 400.

Derived:Derived: Tavg rotation = 1/2 x (60 secs/7200 RPM) x 1000 ms/sec = 4 ms. Tavg transfer = 60/7200 RPM x 1/400 secs/track x 1000 ms/sec =

0.02 ms Taccess = 9 ms + 4 ms + 0.02 ms

Important points:Important points: Access time dominated by seek time and rotational latency. First bit in a sector is the most expensive, the rest are free. SRAM access time is about 4 ns/doubleword, DRAM about 60 ns

Disk is about 40,000 times slower than SRAM, 2,500 times slower then DRAM.

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Logical Disk BlocksModern disks present a simpler abstract view of theModern disks present a simpler abstract view of the

complex sector geometry:complex sector geometry: The set of available sectors is modeled as a sequence of b-

sized logical blocks (0, 1, 2, ...)

Mapping between logical blocks and actual (physical)Mapping between logical blocks and actual (physical)sectorssectors Maintained by hardware/firmware device called disk

controller. Converts requests for logical blocks into

(surface,track,sector) triples.

Allows controller to set aside spare cylinders for eachAllows controller to set aside spare cylinders for eachzone.zone. Accounts for the difference in “formatted capacity” and

“maximum capacity”.

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I/O Bus

mainmemory

I/O bridgebus interface

ALU

register fileCPU chip

system bus memory bus

disk controller

graphicsadapter

USBcontroller

mousekeyboard monitordisk

I/O bus Expansion slots forother devices suchas network adapters.

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Storage Trends

Why can’t the access time of a disk be reduced a lot more?

metric 1980 1985 1990 1995 2000 2000:1980

$/MB 8,000 880 100 30 1 8,000access (ns) 375 200 100 70 60 6typical size(MB) 0.064 0.256 4 16 64 1,000

DRAM

metric 1980 1985 1990 1995 2000 2000:1980

$/MB 19,200 2,900 320 256 100 190access (ns) 300 150 35 15 2 100

SRAM

metric 1980 1985 1990 1995 2000 2000:1980

$/MB 500 100 8 0.30 0.05 10,000access (ms) 87 75 28 10 8 11typical size(MB) 1 10 160 1,000 9,000 9,000

Disk

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CPU Clock Rates

1980 1985 1990 1995 2000 2003 2003:1980CPU 8080 286 386 Pent P-III P-IVMHz 1 6 20 150 750 2000 2000ns/cycle 1,000 166 50 6 1.6 0.5 2000

Summary: In 25 years -•DRAM Memory has gotten 10,000 times bigger and cheaper,and only around 6 times faster•Disks have gotten 10,000 times bigger and cheaper andaround 10 times faster•CPUs have gotten 2000 to 3000 times faster

•Disks and memory are orders of magnitude slower incomparison

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The CPU-Memory Gap The increasing gap between DRAM, disk, and CPU The increasing gap between DRAM, disk, and CPU

speeds.speeds.

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

1980 1985 1990 1995 2000

year

ns

Disk seek time

DRAM access time

SRAM access time

CPU cycle time

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Another way of looking at it1980:1980:

DRAM access = 375 ns. = ~ 0.4 CPU cycles Disk access = ~100 msec = ~1000 CPU cycles

NowNow DRAM access = 60 ns. = ~ 120 CPU cycles Disk access = ~10 msec = ~20,000,000 CPU cycles

This suggests weThis suggests we’’d like to use SRAM, if only it werend like to use SRAM, if only it weren’’tt100 times as expensive as DRAM.100 times as expensive as DRAM.

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Memory HierarchiesSome fundamental and enduring properties ofSome fundamental and enduring properties of

hardware and software:hardware and software: Fast storage technologies cost more per byte and have less

capacity. The gap between CPU and main memory speed is widening. Well-written programs tend to exhibit good locality.

These fundamental properties complement each other.These fundamental properties complement each other.

They suggest an approach for organizing memory andThey suggest an approach for organizing memory andstorage systems known as a storage systems known as a memory hierarchymemory hierarchy..

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An Example Memory Hierarchy

registers

on-chip L1cache (SRAM)

main memory(DRAM)

local secondary storage(local disks)

Larger, slower,

and cheaper (per byte)storagedevices

remote secondary storage(distributed file systems, Web servers)

Local disks hold filesretrieved from disks onremote network servers.

Main memory holds diskblocks retrieved from localdisks.

off-chip L2cache (SRAM)

L1 cache holds cache lines retrievedfrom the L2 cache memory.

CPU registers hold words retrievedfrom L1 cache.

L2 cache holds cache linesretrieved from main memory.

L0:

L1:

L2:

L3:

L4:

L5:

Smaller,faster,and

costlier(per byte)storage devices

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CachesCache:Cache: A smaller, faster storage device that contains a A smaller, faster storage device that contains a

subset of the data in a larger, slower device.subset of the data in a larger, slower device.Fundamental idea of a memory hierarchy:Fundamental idea of a memory hierarchy:

For each k, the faster, smaller device at level k serves as acache for the larger, slower device at level k+1.

Why do memory hierarchies work?Why do memory hierarchies work? Programs tend to access the data at level k more often than

they access the data at level k+1. Thus, the storage at level k+1 can be slower, and thus larger

and cheaper per bit. Goal: A large pool of memory that costs as much as the

cheap storage near the bottom, but that serves data toprograms at the rate of the fast storage near the top.

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Examples of Caching in the Hierarchy

Hardware0On-Chip TLBAddresstranslations

TLB

Webbrowser

10,000,000Local diskWeb pagesBrowsercacheWeb cache

Network buffercache

Buffer cache

VirtualMemory

L2 cacheL1 cache

Registers

Cache Type

Web pages

Parts of filesParts of files

4-KB page32-byte block32-byte block

4-byte word

What Cached

Web proxyserver

1,000,000,000Remote serverdisks

OS100Main memory

Hardware1On-Chip L1Hardware10Off-Chip L2

AFS/NFSclient

10,000,000Local disk

Hardware+OS

100Main memory

Compiler0 CPU registers

ManagedBy

Latency(cycles)

Where Cached

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Processor Chip

Intel Pentium Cache Hierarchy

L1 Data1 cycle latency

16 KB4-way assoc

Write-through32B lines

L1 Instruction16 KB, 4-way

32B lines

Regs. L2 Unified128KB--2 MB4-way assocWrite-back

Write allocate32B lines

MainMemory

Up to 4GB

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More recent info for Pentium-4 L1 data cacheL1 data cache

8K bytes, on the cpu 2 cycle latency

L1 instruction cache replaced with L1 instruction cache replaced with ““execution traceexecution tracecachecache”” Optimized for fetching and decoding instructions

L2 cache (unified? data only?)L2 cache (unified? data only?) 256K - 1 MB, also on the cpu 8-way set associative, 64-byte cache line size 18 cycle latency, even though it’s on the CPU

2 MB L3 cache off chip2 MB L3 cache off chip Memory has around 92 cycle latencyMemory has around 92 cycle latency

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The memory cacheStores values from main memory, recently accessed byStores values from main memory, recently accessed by

the processor.the processor.Controlled by the hardware Controlled by the hardware –– completely invisible to completely invisible to

softwaresoftware except for the performance

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Cache Performance MetricsMiss RateMiss Rate

Fraction of memory references not found in cache(misses/references)

Typical numbers: 3-10% for L1 can be quite small ( < 1%) for L2, depending on size, etc.

Hit TimeHit Time Time to deliver a line in the cache to the processor (includes

time to determine whether the line is in the cache) Typical numbers:

2 clock cycles for L1 ~20 clock cycles for L2

Miss PenaltyMiss Penalty Additional time required because of a miss

Typically ~100 cycles for main memory

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sparc vs intel•• older older sparc sparc had 32 register files availablehad 32 register files available•• more registers for runtime codemore registers for runtime code•• RISC architecture -RISC architecture - goal of 1 cycle per instructiongoal of 1 cycle per instruction

• lots of loads/stores

•• Intel -Intel - registers focused on specific tasksregisters focused on specific tasks•• however 8 more with 64 bit architecturehowever 8 more with 64 bit architecture