Compressed Memory Hierarchy
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Transcript of Compressed Memory Hierarchy
Compressed Memory Hierarchy
Dongrui SHEJianhua HUI
The research paper:
A compressed memory hierarchy using an indirect index cache.By Erik G. Hallnor and Steven K. Reinhardt
Advanced Computer Architecture Laboratory
EECS Department
University of Michigan
Outline
Introduction Memory eXpansion Technology Cache-compression IIC & IIC-C Evaluation Summary
Introduction
Memory capacity and Memory bandwidth The amount of cache cannot be
increased without bound;
Scarce resource: memory bandwidth;
Application of data compression
First, adding a compressed main memory system (Memory Expansion Technology, MXT)
Second, Storing compressed data in the cache, then data be transmitted in compressed form between main memory and cache
A key challenge
Management of variable-sized data blocks:
128-byte Block
After compression, 58 bytes unused
Outline
Introduction Memory eXpansion Technology(MXT) Cache-compression IIC & IIC-C Evaluation Summary
Memory eXpansion Technology
A server class system with hardware compressed main memory.
Using LZSS compression algorithm. For most applications, two to one compression (2:l).
Hardware compression of memory has a negligible performance penalty.
Hardware organization
Sector translation table
Each entry has 4 physical addr that each points to a 256B sector.
Outline
Introduction Memory eXpansion Technology(MXT) Cache-compression IIC & IIC-C Evaluation Summary
Cache compression
Most designs for power savings, using more conventional cache structures:unused storage benefits only by not consuming power.
To use the space freed by compression, new cache structure is needed.
Outline
Introduction Memory eXpansion Technology(MXT) Cache-compression IIC & IIC-C Evaluation Summary
Conventional Cache Structure
Tag associated statically with a block
When data is compressed
tag
tag
Solution: Indirect Index Cache
A tag entry not associated with a particular data block
A tag entry contains a pointer to data block
IIC structure
The cache can be fully associative
TAG offset
TE TE TE TE
hash
CHAIN CHAINTE
=?
Hit?
TAG =?
Hit?
=?
Hit?
=?
Hit?
=?
Hit?
DATA
DATA
TAG STATUS INDEX REPL
TAG
Extend IIC to compressed data
Tag contains multiple pointers to smaller data blocks
Software-managed Blocks grouped into prioritized pools based
on frequency
Victim is chosen from lowest-priority non-empty pool
Generational Replacement
Additional Cost
Compression/decompression engine More space for the tag entries Extra resource for replacement
algorithm
Area is roughly 13% larger
Outline
Introduction Memory eXpansion Technology(MXT) Cache-compression IIC & IIC-C Evaluation Summary
Evaluation
Method: SPEC CPU2000 Benchmarks: Main memory: 150 cycle latency, bus
width 32, with MXT L1: 1 cycle latency, split 16KB, 4-way,
64B block size L2:12 cycle latency, unified 256KB, 8-
way,128B block size L3:26 cycle latency, unified 1MB,8-
way,128B block size, with IIC-C
Evaluation
lsd
Benchmarks relative to a traditional 128B-Block,8-way, LRU 1MB Cache
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
1.12
1.14
LRU 1.1MB IIC 1MB IIC-C 1MB LRU 2MB
Over 50% gain with only 10% area overhead
Evaluation Benchmarks as main memory latency increases
relative to IIC only with the same cache size
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.1
1.11
150 600300 1200
Summary
Advantages: Increase Effective Capacity & Bandwidth; Power Saving From Less Memory Access
Drawbacks: Increase Hardware Complexity Power Consumption of Additional Hardware
Future work
Overall power consumption study
Use it in embedded system
ENDThank you !
Question time.