CPLD UG606 (v12.1) 2010 4 19
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(v.12.1)

CPLD 2 http://japan.xilinx.com UG606 (v12.1) 2010 4 19

HDL
BUF ()FD (D
)
FD4CE


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 3

4 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
AND7 ......................................................................................................... 80
AND8 ......................................................................................................... 81
AND9 ......................................................................................................... 82
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 5
CB4RLE ................................................................................................... 139
CB4X1 ..................................................................................................... 141
CB4X2 ..................................................................................................... 143
CB8CE ..................................................................................................... 145
CB8CLE ................................................................................................... 147
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CD4CE..................................................................................................... 218
CD4CLE................................................................................................... 220
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 7
CLK_DIV2RSD........................................................................................... 265
CLK_DIV2SD............................................................................................. 266
CLK_DIV4................................................................................................. 267
CLK_DIV4R............................................................................................... 268
CLK_DIV4RSD........................................................................................... 269
CLK_DIV4SD............................................................................................. 270
CLK_DIV6................................................................................................. 271
CLK_DIV6R............................................................................................... 272
CLK_DIV6RSD........................................................................................... 273
CLK_DIV6SD............................................................................................. 274
CLK_DIV8................................................................................................. 275
CLK_DIV8R............................................................................................... 276
CLK_DIV8RSD........................................................................................... 277
CLK_DIV8SD............................................................................................. 278
COMP16................................................................................................... 279
8 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
FD8RE ..................................................................................................... 309
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FDSRE ..................................................................................................... 368
10 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
IOBUFE.................................................................................................... 434
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 11
NAND6..................................................................................................... 480
NAND7..................................................................................................... 481
NAND8..................................................................................................... 482
NAND9..................................................................................................... 483
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OR2 ......................................................................................................... 520
OR2B1 ..................................................................................................... 521
OR2B2 ..................................................................................................... 522
OR3 ......................................................................................................... 523
OR3B1 ..................................................................................................... 524
OR3B2 ..................................................................................................... 525
OR3B3 ..................................................................................................... 526
OR4 ......................................................................................................... 527
OR4B1 ..................................................................................................... 528
OR4B2 ..................................................................................................... 529
OR4B3 ..................................................................................................... 530
OR4B4 ..................................................................................................... 531
OR5 ......................................................................................................... 532
OR5B1 ..................................................................................................... 533
OR5B2 ..................................................................................................... 534
OR5B3 ..................................................................................................... 535
OR5B4 ..................................................................................................... 536
OR5B5 ..................................................................................................... 537
OR6 ......................................................................................................... 538
OR7 ......................................................................................................... 539
OR8 ......................................................................................................... 540
OR9 ......................................................................................................... 541
PULLDOWN ............................................................................................. 542
PULLUP ................................................................................................... 543
SR16CE .................................................................................................... 544
SR16CLE .................................................................................................. 546
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SR8CLED.................................................................................................. 572
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XOR9 ....................................................................................................... 632
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 15
CPLD
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1

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1 :
ACC1 : 1-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset
ACC16 : 16-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset
ACC4 : 4-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset
ACC8 : 8-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset
ADD1 : 1-Bit Full Adder with Carry-In and Carry-Out
ADD16 : 16-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow
ADD4 : 4-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow
ADD8 : 8-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow
ADSU1 : 1-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out
ADSU16 : 16-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow
ADSU4 : 4-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow
ADSU8 : 8-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow
CPLD
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1 :
BUF16 : 16-Bit General Purpose Buffer
BUF4 : 4-Bit General Purpose Buffer
BUF8 : 8-Bit General Purpose Buffer
BUFE : Internal 3-State Buffer with Active High Enable
BUFE16 : 16-Bit Internal 3-State Buffer with Active High Enable
BUFE4 : 4-BitInternal 3-State Buffer with Active High Enable
BUFE8 : 8-Bit Internal 3-State Buffer with Active High Enable
BUFG : Global Clock Buffer
BUFGSR : Global Set/Reset Input Buffer
BUFGTS : Global 3-State Input Buffer
BUFT : Internal 3-State Buffer with Active Low Enable
BUFT16 : 16-Bit Internal 3-State Buffers with Active Low Enable
BUFT4 : 4-Bit Internal 3-State Buffers with Active Low Enable
BUFT8 : 8-Bit Internal 3-State Buffers with Active Low Enable

CLK_DIV10R : Global Clock Divide by 10 with Synchronous Reset
CLK_DIV10RSD : Global Clock Divide by 10 with Synchronous Reset and Start Delay
CLK_DIV10SD : Global Clock Divide by 10 with Start Delay
CLK_DIV12 : Simple Global Clock Divide by 12
CLK_DIV12R : Global Clock Divide by 12 with Synchronous Reset
CLK_DIV12RSD : Global Clock Divide by 12 with Synchronous Reset and Start Delay
CLK_DIV12SD : Global Clock Divide by 12 with Start Delay
CLK_DIV14R : Global Clock Divide by 14 with Synchronous Reset
CLK_DIV14RSD : Global Clock Divide by 14 with Synchronous Reset and Start Delay
CLK_DIV14SD : Global Clock Divide by 14 with Start Delay
CLK_DIV16 : Simple Global Clock Divide by 16
CLK_DIV16R : Global Clock Divide by 16 with Synchronous Reset
CPLD
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CLK_DIV16RSD : Global Clock Divide by 16 with Synchronous Reset and Start Delay
CLK_DIV16SD : Global Clock Divide by 16 with Start Delay
CLK_DIV2 : Simple Global Clock Divide by 2
CLK_DIV2R : Global Clock Divide by 2 with Synchronous Reset
CLK_DIV2RSD : Global Clock Divide by 2 with Synchronous Reset and Start Delay
CLK_DIV2SD : Global Clock Divide by 2 with Start Delay
CLK_DIV4 : Simple Global Clock Divide by 4
CLK_DIV4R : Global Clock Divide by 4 with Synchronous Reset
CLK_DIV4RSD : Global Clock Divide by 4 with Synchronous Reset and Start Delay
CLK_DIV4SD : Global Clock Divide by 4 with Start Delay
CLK_DIV6 : Simple Global Clock Divide by 6
CLK_DIV6R : Global Clock Divide by 6 with Synchronous Reset
CLK_DIV6RSD : Global Clock Divide by 6 with Synchronous Reset and Start Delay
CLK_DIV6SD : Global Clock Divide by 6 with Start Delay
CLK_DIV8 : Simple Global Clock Divide by 8
CLK_DIV8R : Global Clock Divide by 8 with Synchronous Reset
CLK_DIV8RSD : Global Clock Divide by 8 with Synchronous Reset and Start Delay
CLK_DIV8SD : Global Clock Divide by 8 with Start Delay


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CB16CE : 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
CB16CLE : 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear
CB16CLED : 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear
CB16RE : 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
CB16RLE : 16-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset
CB16X1 : 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear
CB16X2 : 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchro-nous Reset
CB2CE : 2-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
CB2CLE : 2-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear
CB2CLED : 2-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear
CB2RE : 2-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
CB2RLE : 2-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset
CB2X1 : 2-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear
CB4CE : 4-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
CB4CLE : 4-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear
CB4CLED : 4-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear
CB4RE : 4-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
CB4RLE : 4-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset
CB4X1 : 4-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear
CB4X2 : 4-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchronous Reset
CB8CE : 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
CB8CLE : 8-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear
CB8CLED : 8-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear
CPLD
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CB8RE : 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
CB8RLE : 8-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset
CB8X1 : 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear
CB8X2 : 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchronous Reset
CBD16CE : 16-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD16CLE : 16-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD16CLED : 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD16RE : 16-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset
CBD16RLE : 16-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset
CBD16X1 : 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD16X2 : 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset
CBD2CE : 2-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD2CLE : 2-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD2CLED : 2-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD2RE : 2-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset
CBD2RLE : 2-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset
CBD2X1 : 2-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD2X2 : 2-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset
CBD4CE : 4-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD4CLE : 4-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD4CLED : 4-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CPLD
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CBD4RE : 4-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset
CBD4RLE : 4-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset
CBD4X1 : 4-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD4X2 : 4-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset
CBD8CE : 8-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD8CLE : 8-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD8CLED : 8-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD8RE : 8-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset
CBD8X1 : 8-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
CBD8X2 : 8-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset
CD4CE : 4-Bit Cascadable BCD Counter with Clock Enable and Asynchronous Clear
CD4CLE : 4-Bit Loadable Cascadable BCD Counter with Clock Enable and Asynchronous Clear
CD4RE : 4-Bit Cascadable BCD Counter with Clock Enable and Synchronous Reset
CD4RLE : 4-Bit Loadable Cascadable BCD Counter with Clock Enable and Synchronous Reset
CDD4CE : 4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Asynchronous Clear
CDD4CLE : 4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Asynchronous Clear
CDD4RE : 4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Synchronous Reset
CDD4RLE : 4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Synchronous Reset
CJ4CE 4-Bit Johnson Counter with Clock Enable and Asynchronous Clear
CJ4RE : 4-Bit Johnson Counter with Clock Enable and Synchronous Reset
CJ5CE : 5-Bit Johnson Counter with Clock Enable and Asynchronous Clear
CPLD
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CJ5RE : 5-Bit Johnson Counter with Clock Enable and Synchronous Reset
CJ8CE : 8-Bit Johnson Counter with Clock Enable and Asynchronous Clear
CJ8RE : 8-Bit Johnson Counter with Clock Enable and Synchronous Reset
CJD4CE : 4-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Asynchronous Clear
CJD4RE : 4-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Synchronous Reset
CJD5CE : 5-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Asynchronous Clear
CJD5RE : 5-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Synchronous Reset
CJD8CE : 8-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Asynchronous Clear
CJD8RE : 8-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Synchronous Reset
CR16CE : 16-Bit Negative-Edge Binary Ripple Counter with Clock Enable and Asynchronous Clear
CR8CE : 8-Bit Negative-Edge Binary Ripple Counter with Clock Enable and Asynchronous Clear
CRD16CE : 16-Bit Dual-Edge Triggered Binary Ripple Counter with Clock Enable and Asynchronous Clear
CRD8CE : 8-Bit Dual-Edge Triggered Binary Ripple Counter with Clock Enable and Asynchronous Clear


FD16 : Multiple D Flip-Flop
FD16CE : 16-Bit Data Register with Clock Enable and Asynchronous Clear
FD16RE : 16-Bit Data Register with Clock Enable and Synchronous Reset
FD4 : Multiple D Flip-Flop
CPLD
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FD4CE : 4-Bit Data Register with Clock Enable and Asynchronous Clear
FD8 : Multiple D Flip-Flop
FD8CE : 8-Bit Data Register with Clock Enable and Asynchronous Clear
FD8RE : 8-Bit Data Register with Clock Enable and Synchronous Reset
FDC : D Flip-Flop with Asynchronous Clear
FDCE : D Flip-Flop with Clock Enable and Asynchronous Clear
FDCP : D Flip-Flop with Asynchronous Preset and Clear
FDCPE : D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
FDD : Dual Edge Triggered D Flip-Flop
FDD16 : Multiple Dual Edge Triggered D Flip-Flops
FDD16CE : 16-Bit Dual Edge Triggered Data Register with Clock Enable and Asynchronous Clear
FDD16RE : 16-Bit Dual Edge Triggered Data Register with Clock Enable and Synchronous Reset
FDD4 Multiple Dual Edge Triggered D Flip-Flop
FDD4CE : 4-Bit Dual Edge Triggered Data Register with Clock Enable and Asynchronous Clear
FDD4RE : 4-Bit Dual Edge Triggered Data Register with Clock Enable and Synchronous Reset
FDD8 : Multiple Dual Edge Triggered D Flip-Flops
FDD8CE : 8-Bit Dual Edge Triggered Data Register with Clock Enable and Asynchronous Clear
FDD8RE : 8-Bit Dual Edge Triggered Data Register with Clock Enable and Synchronous Reset
FDDC : D Dual Edge Triggered Flip-Flop with Asynchronous Clear
FDDCE : Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Clear
FDDCP : Dual Edge Triggered D Flip-Flop Asynchronous Preset and Clear
FDDCPE : Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
FDDP : Dual Edge Triggered D Flip-Flop with Asynchronous Preset
FDDPE : Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Preset
FDDR : Dual Edge Triggered D Flip-Flop with Synchronous Reset
FDDRE : Dual Edge Triggered D Flip-Flop with Clock Enable and Synchronous Reset
CPLD
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FDDRS : Dual Edge Triggered D Flip-Flop with Synchronous Reset and Set
FDDRSE : Dual Edge Triggered D Flip-Flop with Synchronous Reset and Set and Clock Enable
FDDS : Dual Edge Triggered D Flip-Flop with Synchronous Set
FDDSE : D Flip-Flop with Clock Enable and Synchronous Set
FDDSR : Dual Edge Triggered D Flip-Flop with Synchronous Set and Reset
FDDSRE : Dual Edge Triggered D Flip-Flop with Synchronous Set and Reset and Clock Enable
FDP : D Flip-Flop with Asynchronous Preset
FDPE : D Flip-Flop with Clock Enable and Asynchronous Preset
FDR : D Flip-Flop with Synchronous Reset
FDRE : D Flip-Flop with Clock Enable and Synchronous Reset
FDRS : : D Flip-Flop with Synchronous Reset and Set
FDRSE : D Flip-Flop with Synchronous Reset and Set and Clock Enable
FDS : D Flip-Flop with Synchronous Set
FDSE : D Flip-Flop with Clock Enable and Synchronous Set
FDSR D Flip-Flop with Synchronous Set and Reset
FDSRE : D Flip-Flop with Synchronous Set and Reset and Clock Enable
FJKC : J-K Flip-Flop with Asynchronous Clear
FJKCE : J-K Flip-Flop with Clock Enable and Asynchronous Clear
FJKCP : J-K Flip-Flop with Asynchronous Clear and Preset
FJKCPE : J-K Flip-Flop with Asynchronous Clear and Preset and Clock Enable
FJKP : J-K Flip-Flop with Asynchronous Preset
FJKPE : J-K Flip-Flop with Clock Enable and Asynchronous Preset
FJKRSE : J-K Flip-Flop with Clock Enable and Synchronous Reset and Set
FJKSRE : J-K Flip-Flop with Clock Enable and Synchronous Set and Reset
FTC : Toggle Flip-Flop with Asynchronous Clear
FTCE : Toggle Flip-Flop with Clock Enable and Asynchronous Clear
FTCLE : Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Clear
FTCLEX : Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Clear
CPLD
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FTCP : Toggle Flip-Flop with Asynchronous Clear and Preset
FTCPE : Toggle Flip-Flop with Clock Enable and Asynchronous Clear and Preset
FTCPLE : Loadable Toggle Flip-Flop with Clock Enable and Asynchronous Clear and Preset
FTDCE : Dual-Edge Triggered Toggle Flip-Flop with Clock Enable and Asynchronous Clear
FTDCLE : Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Clear
FTDCLEX : Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Clear
FTDCP : Dual-Edge Triggered Toggle Flip-Flop with Asynchronous Clear and Preset
FTDRSE : Dual-Edge Triggered Toggle Flip-Flop with Synchronous Reset, Set, and Clock Enable
FTDRSLE : Dual-Edge Triggered Toggle Flip-Flop with Clock Enable and Synchronous Reset and Set
FTP : Toggle Flip-Flop with Asynchronous Preset
FTPE : Toggle Flip-Flop with Clock Enable and Asynchronous Preset
FTPLE : Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Preset
FTRSE : Toggle Flip-Flop with Clock Enable and Synchronous Reset and Set
FTRSLE : Toggle/Loadable Flip-Flop with Clock Enable and Synchronous Reset and Set
FTSRE : Toggle Flip-Flop with Clock Enable and Synchronous Set and Reset
FTSRLE : Toggle/Loadable Flip-Flop with Clock Enable and Synchronous Set and Reset

KEEPER : KEEPER Symbol
PULLDOWN : Resistor to GND for Input Pads, Open-Drain, and 3-State Outputs
PULLUP : Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs
VCC : VCC-Connection Signal Tag
CPLD
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1 :
IOBUFE : Bi-Directional Buffer
OBUF : Output Buffer
OBUFE : 3-State Output Buffer with Active-High Output Enable
OBUFE16 : 16-Bit 3-State Output Buffer with Active-High Output Enable
OBUFE4 : 4-Bit 3-State Output Buffer with Active-High Output Enable
OBUFE8 : 8-Bit 3-State Output Buffer with Active-High Output Enable
OBUFT : 3-State Output Buffer with Active Low Output Enable
OBUFT16 : 16-Bit 3-State Output Buffer with Active Low Output Enable
OBUFT4 : 4-Bit 3-State Output Buffers with Active-Low Output Enable
OBUFT8 : 8-Bit 3-State Output Buffers with Active-Low Output Enable
CPLD
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LD16 : Multiple Transparent Data Latch
LD4 : Multiple Transparent Data Latch
LD8 : Multiple Transparent Data Latch
LDC : : Transparent Data Latch with Asynchronous Clear
LDCP : Transparent Data Latch with Asynchronous Clear and Preset
LDG : Transparent Datagate Latch
LDG16 : 16-bit Transparent Datagate Latch
LDG4 : 4-Bit Transparent Datagate Latch
LDG8 : 8-Bit Transparent Datagate Latch
LDP : : Transparent Data Latch with Asynchronous Preset

AND2 : 2- Input AND Gate with Non-Inverted Inputs
AND2B1 : 2-Input AND Gate with 1 Inverted and 1 Non-Inverted Inputs
AND2B2 : 2-Input AND Gate with Inverted Inputs
AND3 : 3- Input AND Gate with Non-Inverted Inputs
AND3B1 : 3-Input AND Gate with 1 Inverted and 2 Non-Inverted Inputs
AND3B2 : 3-Input AND Gate with 2 Inverted and 1 Non-Inverted Inputs
AND3B3 : 3-Input AND Gate with Inverted Inputs
AND4 : 4- Input AND Gate with Non-Inverted Inputs
AND4B1 : 4-Input AND Gate with 1 Inverted and 3 Non-Inverted Inputs
AND4B2 : 4-Input AND Gate with 2 Inverted and 2 Non-Inverted Inputs
AND4B3 : 4-Input AND Gate with 3 Inverted and 1 Non-Inverted Inputs
AND4B4 : 4-Input AND Gate with Inverted Inputs
AND5 : 5- Input AND Gate with Non-Inverted Inputs
AND5B1 : 5-Input AND Gate with 1 Inverted and 4 Non-Inverted Inputs
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 29
1 :

AND5B2 : 5-Input AND Gate with 2 Inverted and 3 Non-Inverted Inputs
AND5B3 : 5-Input AND Gate with 3 Inverted and 2 Non-Inverted Inputs
AND5B4 : 5-Input AND Gate with 4 Inverted and 1 Non-Inverted Inputs
AND5B5 : 5-Input AND Gate with Inverted Inputs
AND6 : 6- Input AND Gate with Non-Inverted Inputs
AND7 : 7- Input AND Gate with Non-Inverted Inputs
AND8 : 8- Input AND Gate with Non-Inverted Inputs
AND9 : 9- Input AND Gate with Non-Inverted Inputs
INV : Inverter
NAND2 : 2- Input NAND Gate with Non-Inverted Inputs
NAND2B1 : 2-Input NAND Gate with 1 Inverted and 1 Non-Inverted Inputs
NAND2B2 : 2-Input NAND Gate with Inverted Inputs
NAND3 : 3- Input NAND Gate with Non-Inverted Inputs
NAND3B1 : 3-Input NAND Gate with 1 Inverted and 2 Non-Inverted Inputs
NAND3B2 : 3-Input NAND Gate with 2 Inverted and 1 Non-Inverted Inputs
NAND3B3 : 3-Input NAND Gate with Inverted Inputs
NAND4 : 4- Input NAND Gate with Non-Inverted Inputs
NAND4B1 : 4-Input NAND Gate with 1 Inverted and 3 Non-Inverted Inputs
NAND4B2 : 4-Input NAND Gate with 2 Inverted and 2 Non-Inverted Inputs
NAND4B3 : 4-Input NAND Gate with 3 Inverted and 1 Non-Inverted Inputs
NAND4B4 : 4-Input NAND Gate with Inverted Inputs
NAND5 : 5- Input NAND Gate with Non-Inverted Inputs
NAND5B1 : 5-Input NAND Gate with 1 Inverted and 4 Non-Inverted Inputs
NAND5B2 : 5-Input NAND Gate with 2 Inverted and 3 Non-Inverted Inputs
NAND5B3 : 5-Input NAND Gate with 3 Inverted and 2 Non-Inverted Inputs
NAND5B4 : 5-Input NAND Gate with 4 Inverted and 1 Non-Inverted Inputs
CPLD
30 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
1 :
NAND6 : 6- Input NAND Gate with Non-Inverted Inputs
NAND7 : 7- Input NAND Gate with Non-Inverted Inputs
NAND8 : 8- Input NAND Gate with Non-Inverted Inputs
NAND9 : 9- Input NAND Gate with Non-Inverted Inputs
NOR2 : 2-Input NOR Gate with Non-Inverted Inputs
NOR2B1 : 2-Input NOR Gate with 1 Inverted and 1 Non-Inverted Inputs
NOR2B2 : 2-Input NOR Gate with Inverted Inputs
NOR3 : 3-Input NOR Gate with Non-Inverted Inputs
NOR3B1 : 3-Input NOR Gate with 1 Inverted and 2 Non-Inverted Inputs
NOR3B2 : 3-Input NOR Gate with 2 Inverted and 1 Non-Inverted Inputs
NOR3B3 : 3-Input NOR Gate with Inverted Inputs
NOR4 : 4-Input NOR Gate with Non-Inverted Inputs
NOR4B1 : 4-Input NOR Gate with 1 Inverted and 3 Non-Inverted Inputs
NOR4B2 : 4-Input NOR Gate with 2 Inverted and 2 Non-Inverted Inputs
NOR4B3 : 4-Input NOR Gate with 3 Inverted and 1 Non-Inverted Inputs
NOR4B4 : 4-Input NOR Gate with Inverted Inputs
NOR5 : 5-Input NOR Gate with Non-Inverted Inputs
NOR5B1 : 5-Input NOR Gate with 1 Inverted and 4 Non-Inverted Inputs
NOR5B2 : 5-Input NOR Gate with 2 Inverted and 3 Non-Inverted Inputs
NOR5B3 : 5-Input NOR Gate with 3 Inverted and 2 Non-Inverted Inputs
NOR5B4 : 5-Input NOR Gate with 4 Inverted and 1 Non-Inverted Inputs
NOR5B5 : 5-Input NOR Gate with Inverted Inputs
NOR6 : 6-Input NOR Gate with Non-Inverted Inputs
NOR7 : 7-Input NOR Gate with Non-Inverted Inputs
NOR8 : 8-Input NOR Gate with Non-Inverted Inputs
NOR9 : 9-Input NOR Gate with Non-Inverted Inputs
OR2 : 2-Input OR Gate with Non-Inverted Inputs
OR2B1 : 2-Input OR Gate with 1 Inverted and 1 Non-Inverted Inputs
OR2B2 : 2-Input OR Gate with Inverted Inputs
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 31
1 :
OR3 : 3-Input OR Gate with Non-Inverted Inputs
OR3B1 : 3-Input OR Gate with 1 Inverted and 2 Non-Inverted Inputs
OR3B2 : 3-Input OR Gate with 2 Inverted and 1 Non-Inverted Inputs
OR3B3 : 3-Input OR Gate with Inverted Inputs
OR4 : 4-Input OR Gate with Non-Inverted Inputs
OR4B1 : 4-Input OR Gate with 1 Inverted and 3 Non-Inverted Inputs
OR4B2 : 4-Input OR Gate with 2 Inverted and 2 Non-Inverted Inputs
OR4B3 : 4-Input OR Gate with 3 Inverted and 1 Non-Inverted Inputs
OR4B4 : 4-Input OR Gate with Inverted Inputs
OR5 : 5-Input OR Gate with Non-Inverted Inputs
OR5B1 : 5-Input OR Gate with 1 Inverted and 4 Non-Inverted Inputs
OR5B2 : 5-Input OR Gate with 2 Inverted and 3 Non-Inverted Inputs
OR5B3 : 5-Input OR Gate with 3 Inverted and 2 Non-Inverted Inputs
OR5B4 : 5-Input OR Gate with 4 Inverted and 1 Non-Inverted Inputs
OR5B5 : 5-Input OR Gate with Inverted Inputs
OR6 : 6-Input OR Gate with Non-Inverted Inputs
OR7 : 7-Input OR Gate with Non-Inverted Inputs
OR8 : 8-Input OR Gate with Non-Inverted Inputs
OR9 : 9-Input OR Gate with Non-Inverted Inputs
XNOR2 : 2-Input XNOR Gate with Non-Inverted Inputs
XNOR3 : 3-Input XNOR Gate with Non-Inverted Inputs
XNOR4 : 4-Input XNOR Gate with Non-Inverted Inputs
XNOR5 : 5-Input XNOR Gate with Non-Inverted Inputs
XNOR6 : 6-Input XNOR Gate with Non-Inverted Inputs
XNOR7 : 7-Input XNOR Gate with Non-Inverted Inputs
XNOR8 : 8-Input XNOR Gate with Non-Inverted Inputs
XNOR9 : 9-Input XNOR Gate with Non-Inverted Inputs
XOR2 : 2-Input XOR Gate with Non-Inverted Inputs
XOR3 : 3-Input XOR Gate with Non-Inverted Inputs
XOR4 : 4-Input XOR Gate with Non-Inverted Inputs
XOR5 : 5-Input XOR Gate with Non-Inverted Inputs
CPLD
32 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
1 :

M2_1 : 2-to-1 Multiplexer
M2_1B2 : 2-to-1 Multiplexer with D0 and D1 Inverted
M2_1E : 2-to-1 Multiplexer with Enable
M4_1E : 4-to-1 Multiplexer with Enable
M8_1E : 8-to-1 Multiplexer with Enable


SR16CE : 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear
SR16CLE : 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear
SR16CLED : 16-Bit Shift Register with Clock Enable and Asynchronous Clear
SR16RE : 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset
SR16RLE : 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset
SR16RLED : 16-Bit Shift Register with Clock Enable and Synchronous Reset
SR4CE : 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear
SR4CLE : 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear
SR4CLED : 4-Bit Shift Register with Clock Enable and Asynchronous Clear
SR4RE : 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset
SR4RLE : 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset
SR4RLED : 4-Bit Shift Register with Clock Enable and Synchronous Reset
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 33
1 :

SR8CE : 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear
SR8CLE : 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear
SR8CLED : 8-Bit Shift Register with Clock Enable and Asynchronous Clear
SR8RE : 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset
SR8RLE : 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset
SR8RLED : 8-Bit Shift Register with Clock Enable and Synchronous Reset
SRD16CE : 16-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear
SRD16CLE : 16-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear
SRD16CLED : 16-Bit Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear
SRD16RE : 16-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset
SRD16RLE : 16-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset
SRD16RLED : 16-Bit Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset
SRD4CE : 4-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear
SRD4CLE : 4-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear
SRD4CLED : 4-Bit Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear
SRD4RE : 4-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset
SRD4RLE : 4-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset
SRD4RLED : 4-Bit Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset
SRD8CE : 8-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear
SRD8CLE : 8-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear
SRD8CLED : 8-Bit Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear
CPLD
34 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
1 :

SRD8RE : 8-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset
SRD8RLE : 8-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset
SRD8RLED : 8-Bit Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 35
CPLD
36 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2
[Language Templates]) HDL

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 37
2 :
ACC1

1 1
1 (R)
R High (C) Low High 0
(CE) Low C
(L) High CE (C) Low High D0 1

ADD CE High 1 (B0) (CI) 1
Low High Q0
(CO) Q0 CO B0
CO CI ACC1
CO CO CI High
ADD Low CE High 1 B0 CI
Low High Q0 (CO) Q0
CO B0
CO CI ACC1 CO
CO CI Low
Low CPLD High
PRLD
CPLD
38 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 39
2 :
ACC16 : 16-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset


16 16 2 2
16
(L) High CE (C) Low High D
ACC16 D15 D0 16
16 2 16 2 2
2 2 2 2
2
(CO) 2 OFL
• 2 0 15
CO (High) CO Low
Low CO CO
B15 B0 ACC16 CO CI
2 High ADD CO

• 2 -8 +7 OFL
High (OFL) OFL
B (B15 B0) ACC4 OFL
CI
40 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
(R) R High (C) Low High
0 (CE) Low C
Low CPLD High
PRLD

1 X X X X ↑ 0
0 1 X X Dn ↑ Dn
0 0 1 1 X ↑ Q0 + Bn + CI
0 0 1 0 X ↑ Q0 - Bn - CI
0 0 0 X X ↑
Q0 : Q
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 41
2 :
ACC4


4 4 2 2
4
(L) High CE (C) Low High D
ACC4 D3 D0 4
4 2 4 2 2
2 2 2 2
2
(CO) 2 OFL
• 2 0 15
CO (High) CO Low
Low CO CO
B3 B0 ACC4 CO CI
2 High ADD CO

CPLD
42 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
• 2 -8 +7 OFL
High (OFL) OFL
B (B3 B0) ACC4 OFL
CI
2 CO
(R) R High (C) Low High
0 (CE) Low C
Low CPLD High
PRLD

1 X X X X ↑ 0
0 1 X X Dn ↑ Dn
0 0 1 1 X ↑ Q0 + Bn + CI
0 0 1 0 X ↑ Q0 - Bn - CI
0 0 0 X X ↑
Q0 : Q
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 43
2 :
ACC8 : 8-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset


8 8 2 2
8
(L) High CE (C) Low High D
ACC8 D7 D0 8
8 2 8 2 2
2 2 2 2
2
(CO) 2 OFL
• 2 0 255
CO (High) CO Low
Low CO CO
B3 B0 ACC8 CO CI
2 High ADD CO

• 2 -128 +127
OFL High (OFL)
OFL B (B3 B0) ACC8 OFL
CI
44 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
(R) R High (C) Low High
0 (CE) Low C
Low CPLD High
PRLD

1 X X X X ↑ 0
0 1 X X Dn ↑ Dn
0 0 1 1 X ↑ Q0 + Bn + CI
0 0 1 0 X ↑ Q0 - Bn - CI
0 0 0 X X ↑
Q0 : Q
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 45
2 :
ADD1

1 2 1
(A B) (CI) 2 (S0) (CO)


46 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
ADD16

2 (CI) (CO) (OFL)
A15 A0B15 B0 CI S15 S0 CO ( OFL)


CI : CI
2 2
16 2 16 2 2
2 2 2 2
2
CO 2 OFL 2 CO
2 OFL
2
2 0 65535 2 OFL
2
(High) 2 CO
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 47
2 :

48 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
ADD4

2 (CI) (CO) (OFL)
A3 A0B3 B0 CI S3 S0 CO ( OFL)

CI : CI
2 2
4 2 4 2 2
2 2 2 2
2 CO
2 OFL 2 CO
2 OFL
2
2 0 15 2 OFL
2
(High) 2 CO
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 49
2 :

50 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
ADD8

2 (CI) (CO) (OFL)
A7 A0B7 B0 CI S7 S0 CO ( OFL)

CI : CI
2 2
8 2 8 2 2
2 2 2 2
2 CO
2 OFL 2 CO
2 OFL
2
2 0 255 2 OFL
2
(High) 2 CO

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 51
2 :

52 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
ADSU1


ADD High 2 1 (A0 B0) (CI) 1 (S0)
(CO) ADD Low B0 A0 (S0) (CO)

CO CO CI High CO
CO CI Low
(ADD=1)
(ADD=0)
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 53
2 :


54 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
ADSU16 : 16-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow


ADD High 2 16 (A15 A0 B15 B0) (CI) 16
(S15 S0) (CO) ( (OFL)
ADD Low A15 A0 B15 B0 (CO)
(OFL)
CO CI High CO CI Low
OFL High

CI* : ADD = 0CICO Low
CI* : ADD = 1CICO High
2 2
16 2 16 2 2
2 2 2 2
2
CO 2 OFL
2 2

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 55
2 :
2
2 0 65535
CO (High) CO Low
Low
2 High ADD CO

2
OFL High 2 CO

56 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
ADSU4


ADD High 2 4 (A3 A0 B3 B0) (CI) 4 (S3
S0) (CO) ( (OFL)
ADD Low A3 A0 B3 B0 4 (S3 S0) (CO)
(OFL)
CO CI High CO CI Low
OFL High

CI* : ADD = 0CICO Low
CI* : ADD = 1CICO High
2 2
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 57
2 :
4 2 4 2 2
2 2 2 2
2 CO
2 OFL
2 2

2
2 0 15
CO (High) CO Low
Low
2 High ADD CO

2
OFL High 2 CO

58 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
ADSU8


ADD High 2 8 (A7 A0 B7 B0) (CI) 8 (S7
S0) (CO) ( (OFL)
ADD Low A7 A0 B7 B0 8 (S7 S0) (CO)
(OFL)
CO CI High CO CI Low
OFL High

CI* : ADD = 0CICO Low
CI* : ADD = 1CICO High
2 2
8 2 8 2 2
2 2 2 2
2 CO
2 OFL
2 2

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 59
2 :
2
2 0 255
CO (High) CO Low
Low
2 High ADD CO

2
OFL High 2 CO

60 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
AND2

12 16 AND
CLB


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 61
2 :
AND2B1
: 2-Input AND Gate with 1 Inverted and 1 Non-Inverted Inputs

12 16 AND
CLB


62 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
AND2B2

12 16 AND
CLB


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 63
2 :
AND3

12 16 AND
CLB


64 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
AND3B1
: 3-Input AND Gate with 1 Inverted and 2 Non-Inverted Inputs

12 16 AND
CLB


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 65
2 :
AND3B2
: 3-Input AND Gate with 2 Inverted and 1 Non-Inverted Inputs

12 16 AND
CLB


66 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
AND3B3

12 16 AND
CLB


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 67
2 :
AND4

12 16 AND
CLB


68 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
AND4B1
: 4-Input AND Gate with 1 Inverted and 3 Non-Inverted Inputs

12 16 AND
CLB


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 69
2 :
AND4B2
: 4-Input AND Gate with 2 Inverted and 2 Non-Inverted Inputs

12 16 AND
CLB


70 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
AND4B3
: 4-Input AND Gate with 3 Inverted and 1 Non-Inverted Inputs

12 16 AND
CLB


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 71
2 :
AND4B4

12 16 AND
CLB


72 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
AND5

12 16 AND
CLB


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 73
2 :
AND5B1
: 5-Input AND Gate with 1 Inverted and 4 Non-Inverted Inputs

12 16 AND
CLB


74 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
AND5B2
: 5-Input AND Gate with 2 Inverted and 3 Non-Inverted Inputs

12 16 AND
CLB


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 75
2 :
AND5B3
: 5-Input AND Gate with 3 Inverted and 2 Non-Inverted Inputs

12 16 AND
CLB


76 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
AND5B4
: 5-Input AND Gate with 4 Inverted and 1 Non-Inverted Inputs

12 16 AND
CLB


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 77
2 :
AND5B5

12 16 AND
CLB


78 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
AND6

12 16 AND
CLB


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 79
2 :
AND7

12 16 AND
CLB


80 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
AND8

12 16 AND
CLB


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 81
2 :
AND9

12 16 AND
CLB


82 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
BRLSHFT4

4 4 (I3 I0) 4
(S1 S0) (1 4) 4 (O3 O0)


S1 S0 I0 I1 I2 I3 O0 O1 O2 O3
0 0 a b c d a b c d
0 1 a b c d b c d a
1 0 a b c d c d a b
1 1 a b c d d a b c

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 83
2 :
BRLSHFT8

8 8 (I7 I0) 8
(S2 S0) (1 8) 8 (O7 O0)



S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 a b c d e f g h a b c d e f g h
0 0 1 a b c d e f g h b c d e f g h a
0 1 0 a b c d e f g h c d e f g h a b
0 1 1 a b c d e f g h d e f g h a b c
1 0 0 a b c d e f g h e f g h a b c d
1 0 1 a b c d e f g h f g h a b c d e
1 1 0 a b c d e f g h g h a b c d e f
1 1 1 a b c d e f g h h a b c d e f g
CPLD
84 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 85
2 :
BUF
86 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
BUF16
16 CPLD OPT=OFF
LOGIC_OPT=OFF

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 87
2 :
BUF4
4 CPLD OPT=OFF
LOGIC_OPT=OFF

88 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
BUF8
8 CPLD OPT=OFF
LOGIC_OPT=OFF

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 89
2 :
BUFE


(I) (O) High (E)
E High E Low
(Z ) FPGA


1 E High E High

High FPGA PULLUP
NGDBuild PULLUP

90 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
BUFE16


(I15 I0) (O15 O0) High (E)
E High
E Low (Z ) FPGA
BUFE
1 E High E
High


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 91
2 :
BUFE4


(I3 I0) (O3 O0) High (E)
E High
E Low (Z ) FPGA
BUFE
1 E High E
High


92 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
BUFE8


(I7 I0) (O7 O0) High (E)
E High
E Low (Z ) FPGA
BUFE
1 E High E
High


UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 93
2 :
BUFG


94 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
BUFGSR
/ (GSR) GSR CPLD

IPAD IOPAD GSR
OBUF
PRE
/ Low /

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 95
2 :
BUFGTS
(GTS) CPLD

IPAD IOPAD BUFGTS GTS
OBUF
E OBUFT
Low
BUFGTS
BUFGTS


96 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
BUFT


(I) (O) High (T)
T Low T High
(Z ) FPGA

BUFT 1 T
Low CPLD BUFE/BUFT
BUFT High FPGA BUFT
High PULLUP
PULLUP NGDBuild PULLUP

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 97
2 :
BUFT16


(I15 I0) (O15 O0) Low (T)
T Low
T High (Z ) FPGA

BUFT 1 T
Low CPLD BUFE/BUFT
BUFT High FPGA BUFT
High PULLUP
PULLUP NGDBuild PULLUP

98 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
BUFT4


(I3 I0) (O3 O0) Low (T)
T Low
T High (Z ) FPGA

BUFT 1 T
Low CPLD BUFE/BUFT
BUFT High FPGA BUFT
High PULLUP
PULLUP NGDBuild PULLUP

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 99
2 :

100 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
BUFT8


(I7 I0) (O7 O0) Low (T)
T Low
T High (Z ) FPGA

BUFT 1 T
Low CPLD BUFE/BUFT
BUFT High FPGA BUFT
High PULLUP
PULLUP NGDBuild PULLUP

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 101
2 :
CB16CE
: 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

(CLR)
High (C) (Q) (TC)
(CEO) 0 (CE) High (C)
Low High (Q) CE Low
Q High TC High
1 CEO CE C CLR
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

1 X X 0 0 0
0 0 X 0
0 1 ↑ TC CEO
z = - 1
CEO = TCCE
CPLD
102 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 103
2 :
CB16CLE
: 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear


(CLR) High (C) (Q)
(TC) (CEO) 0 (L) High
Low High (CE) (D)
CE High Low High Q
CE Low Q High TC High
1 CEO CE CL CLR
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

CPLD
104 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :

CLR L CE C Dz - D0 Qz - Q0 TC CEO
1 X X X X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X 0
0 0 1 ↑ X TC CEO
z = - 1
CEO = TCCE
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 105
2 :
CB16CLED
: 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear


(CLR) High (C) (Q)
(TC) (CEO) 0 (L) High
(C) Low High (CE) (D)
CE HighUP Low Low High Q
CE UP High Q CE Low

Q UP High TC High
Q UP Low TC High
1 CEO CE CUPL CLR
TC CE High CEO (High)
CE TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
CPLD CB2X1CB4X1CB8X1CB16X1

Low CPLD High PRLD

CPLD
106 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :


CLR L CE C UP Dz - D0 Qz - Q0 TC CEO
1 X X X X X 0 0 0
0 1 X ↑ X Dn Dn TC CEO
0 0 0 X X X 0
0 0 1 ↑ 1 X TC CEO
0 0 1 ↑ 0 X TC CEO
z = - 1
TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP)
CEO = TCCE
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 107
2 :
CB16RE
: 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

(R) High
(C) Low High (Q) (TC)
(CEO) 0 (CE) High (C)
Low High (Q) CE Low
Q High TC High
1 CEO CE C R
TC CE High CEO (High) CE TC
n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

1 X ↑ 0 0 0
0 0 X 0
0 1 ↑ TC CEO
z = - 1
CEO = TCCE
CPLD
108 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 109
CPLD
110 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB16RLE
: 16-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset


(R) High (C) Low High (Q)
(TC) (CEO) 0
(L) High (C) Low High CE D
CE High Low High Q
CE Low Q High TC
High Q CE High CEO High

1 CEO CE CL R
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 111
2 :

R L CE C Dz - D0 Qz - Q0 TC CEO
1 X X ↑ X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X 0
0 0 1 ↑ X TC CEO
z = - 1
CEO = TCCE
112 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB16X1
: 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear



(CLR) CLR High
(Q) 0 TCU TCD 0 1
CEOU CEOD Low High (L) High (C)
Low High CE D
CEU HighCLR L Low Low High Q
CED HighCLR L Low Q CEU CED Low
CEU CED High CEU CED High
CEOU CEOD
Q CEU High CEOU High
Q LowCED High CEOD High
CEOU CEOD CEU CED
LCLR

Q High CEU TCU
High Q Low CED TCD High
TCU () TCD (
) AND TCUCEOUCEOD
AND CEU
CED Q

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 113
2 :
0 (TCU LowTCD High) High PRLD


CLR L CEU CED C Dz - D0 Qz - Q0 TCU TCD CEOU CEOD
1 X X X X X 0 0 1 0 CEOD
0 1 X X ↑ Dn Dn TCU TCD CEOU CEOD
0 0 0 0 X X 0 0
0 0 1 0 ↑ X
TCU TCD CEOU 0
TCU TCD 0 CEOD
TCU TCD
CEOU = TCUCEU
CEOD = TCDCED
114 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB16X2 : 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchro-nous Reset

CPLD

(R) R High (C)
Low High (Q) 0 TCU TCD
0 1 CEOU CEOD Low High (L)
High (C) Low High CE D

CEU HighR L Low Low High Q
CED HighR L Low Q CEU CED Low
CEU CED High CEU CED
High CEOU CEOD
Q CEU High CEOU High
Q LowCED High CEOD High
CEOU CEOD CEU CED
CL R

Q High CEU TCU
High Q Low CED TCD High
TCU () TCD (
) AND TCUCEOUCEOD
AND CEU
CED Q

0 (TCU LowTCD High) High PRLD

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 115
2 :


R L CEU CED C Dz - D0 Qz - Q0 TCU TCD CEOU CEOD
1 X X X ↑ X 0 0 1 0 CEOD
0 1 X X ↑ Dn Dn TCU TCD CEOU CEOD
0 0 0 0 X X 0 0
0 0 1 0 ↑ X
TCU TCD CEOU 0
TCU TCD 0 CEOD
TCU TCD
116 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB2CE
: 2-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

(CLR)
High (C) (Q) (TC)
(CEO) 0 (CE) High (C)
Low High (Q) CE Low
Q High TC High
1 CEO CE C CLR
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

1 X X 0 0 0
0 0 X 0
0 1 ↑ TC CEO
z = - 1
CEO = TCCE
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 117
2 :

118 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB2CLE
: 2-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear


(CLR) High (C) (Q)
(TC) (CEO) 0 (L) High
Low High (CE) (D)
CE High Low High Q
CE Low Q High TC High
1 CEO CE CL CLR
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 119
2 :

CLR L CE C Dz - D0 Qz - Q0 TC CEO
1 X X X X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X 0
0 0 1 ↑ X TC CEO
z = - 1
CEO = TCCE
120 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB2CLED
: 2-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear


(CLR) High (C) (Q)
(TC) (CEO) 0 (L) High
(C) Low High (CE) (D)
CE HighUP Low Low High Q
CE UP High Q CE Low

Q UP High TC High
Q UP Low TC High
1 CEO CE CUPL CLR
TC CE High CEO (High)
CE TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
CPLD CB2X1CB4X1CB8X1CB16X1

Low CPLD High PRLD

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 121
2 :


CLR L CE C UP Dz - D0 Qz - Q0 TC CEO
1 X X X X X 0 0 0
0 1 X ↑ X Dn Dn TC CEO
0 0 0 X X X 0
0 0 1 ↑ 1 X TC CEO
0 0 1 ↑ 0 X TC CEO
z = - 1
TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP)
CEO = TCCE
122 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB2RE
: 2-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

(R) High
(C) Low High (Q) (TC)
(CEO) 0 (CE) High (C)
Low High (Q) CE Low
Q High TC High
1 CEO CE C R
TC CE High CEO (High) CE TC
n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

1 X ↑ 0 0 0
0 0 X 0
0 1 ↑ TC CEO
z = - 1
CEO = TCCE
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 123
2 :

124 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB2RLE
: 2-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset


(R) High (C) Low High (Q)
(TC) (CEO) 0
(L) High (C) Low High CE D
CE High Low High Q
CE Low Q High TC
High Q CE High CEO High

1 CEO CE CL R
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 125
2 :

R L CE C Dz - D0 Qz - Q0 TC CEO
1 X X ↑ X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X 0
0 0 1 ↑ X TC CEO
z = - 1
CEO = TCCE
126 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB2X1
: 2-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear



(CLR) CLR High
(Q) 0 TCU TCD 0 1
CEOU CEOD Low High (L) High (C)
Low High CE D
CEU HighCLR L Low Low High Q
CED HighCLR L Low Q CEU CED Low
CEU CED High CEU CED High
CEOU CEOD
Q CEU High CEOU High
Q LowCED High CEOD High
CEOU CEOD CEU CED
LCLR

Q High CEU TCU
High Q Low CED TCD High
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 127
2 :
TCU () TCD (
) AND TCUCEOUCEOD
AND CEU
CED Q

0 (TCU LowTCD High) High PRLD


CLR L CEU CED C Dz - D0 Qz - Q0 TCU TCD CEOU CEOD
1 X X X X X 0 0 1 0 CEOD
0 1 X X ↑ Dn Dn TCU TCD CEOU CEOD
0 0 0 0 X X 0 0
0 0 1 0 ↑ X
TCU TCD CEOU 0
TCU TCD 0 CEOD
TCU TCD
CEOU = TCUCEU
CEOD = TCDCED
128 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB2X2 : 2-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchronous Reset

CPLD

(R) R High (C)
Low High (Q) 0 TCU TCD
0 1 CEOU CEOD Low High (L)
High (C) Low High CE D

CEU HighR L Low Low High Q
CED HighR L Low Q CEU CED Low
CEU CED High CEU CED
High CEOU CEOD
Q CEU High CEOU High
Q LowCED High CEOD High
CEOU CEOD CEU CED
CL R

Q High CEU TCU
High Q Low CED TCD High
TCU () TCD (
) AND TCUCEOUCEOD
AND CEU
CED Q

0 (TCU LowTCD High) High PRLD

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 129
2 :


R L CEU CED C Dz - D0 Qz - Q0 TCU TCD CEOU CEOD
1 X X X ↑ X 0 0 1 0 CEOD
0 1 X X ↑ Dn Dn TCU TCD CEOU CEOD
0 0 0 0 X X 0 0
0 0 1 0 ↑ X
TCU TCD CEOU 0
TCU TCD 0 CEOD
TCU TCD
130 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB4CE : 4-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

(CLR)
High (C) (Q) (TC)
(CEO) 0 (CE) High (C)
Low High (Q) CE Low
Q High TC High
1 CEO CE C CLR
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

1 X X 0 0 0
0 0 X 0
0 1 ↑ TC CEO
z = - 1
CEO = TCCE
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 131
2 :

132 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB4CLE
: 4-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear


(CLR) High (C) (Q)
(TC) (CEO) 0 (L) High
Low High (CE) (D)
CE High Low High Q
CE Low Q High TC High
1 CEO CE CL CLR
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 133
2 :

CLR L CE C Dz - D0 Qz - Q0 TC CEO
1 X X X X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X 0
0 0 1 ↑ X TC CEO
z = - 1
CEO = TCCE
134 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB4CLED
: 4-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear


(CLR) High (C) (Q)
(TC) (CEO) 0 (L) High
(C) Low High (CE) (D)
CE HighUP Low Low High Q
CE UP High Q CE Low

Q UP High TC High
Q UP Low TC High
1 CEO CE CUPL CLR
TC CE High CEO (High)
CE TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
CPLD CB2X1CB4X1CB8X1CB16X1

Low CPLD High PRLD

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 135
2 :


CLR L CE C UP Dz - D0 Qz - Q0 TC CEO
1 X X X X X 0 0 0
0 1 X ↑ X Dn Dn TC CEO
0 0 0 X X X 0
0 0 1 ↑ 1 X TC CEO
0 0 1 ↑ 0 X TC CEO
z = - 1
TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP)
CEO = TCCE
136 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB4RE : 4-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

(R) High
(C) Low High (Q) (TC)
(CEO) 0 (CE) High (C)
Low High (Q) CE Low
Q High TC High
1 CEO CE C R
TC CE High CEO (High) CE TC
n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

1 X ↑ 0 0 0
0 0 X 0
0 1 ↑ TC CEO
z = - 1
CEO = TCCE
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 137
2 :

138 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB4RLE
: 4-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset


(R) High (C) Low High (Q)
(TC) (CEO) 0
(L) High (C) Low High CE D
CE High Low High Q
CE Low Q High TC
High Q CE High CEO High

1 CEO CE CL R
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 139
2 :

R L CE C Dz - D0 Qz - Q0 TC CEO
1 X X ↑ X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X 0
0 0 1 ↑ X TC CEO
z = - 1
CEO = TCCE
140 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB4X1
: 4-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear



(CLR) CLR High
(Q) 0 TCU TCD 0 1
CEOU CEOD Low High (L) High (C)
Low High CE D
CEU HighCLR L Low Low High Q
CED HighCLR L Low Q CEU CED Low
CEU CED High CEU CED High
CEOU CEOD
Q CEU High CEOU High
Q LowCED High CEOD High
CEOU CEOD CEU CED
LCLR

Q High CEU TCU
High Q Low CED TCD High
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 141
2 :
TCU () TCD (
) AND TCUCEOUCEOD
AND CEU
CED Q

0 (TCU LowTCD High) High PRLD


CLR L CEU CED C Dz - D0 Qz - Q0 TCU TCD CEOU CEOD
1 X X X X X 0 0 1 0 CEOD
0 1 X X ↑ Dn Dn TCU TCD CEOU CEOD
0 0 0 0 X X 0 0
0 0 1 0 ↑ X
TCU TCD CEOU 0
TCU TCD 0 CEOD
TCU TCD
CEOU = TCUCEU
CEOD = TCDCED
142 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB4X2
: 4-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchronous Reset

CPLD

(R) R High (C)
Low High (Q) 0 TCU TCD
0 1 CEOU CEOD Low High (L)
High (C) Low High CE D

CEU HighR L Low Low High Q
CED HighR L Low Q CEU CED Low
CEU CED High CEU CED
High CEOU CEOD
Q CEU High CEOU High
Q LowCED High CEOD High
CEOU CEOD CEU CED
CL R

Q High CEU TCU
High Q Low CED TCD High
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 143
2 :
TCU () TCD (
) AND TCUCEOUCEOD
AND CEU
CED Q

0 (TCU LowTCD High) High PRLD


R L CEU CED C Dz - D0 Qz - Q0 TCU TCD CEOU CEOD
1 X X X ↑ X 0 0 1 0 CEOD
0 1 X X ↑ Dn Dn TCU TCD CEOU CEOD
0 0 0 0 X X 0 0
0 0 1 0 ↑ X
TCU TCD CEOU 0
TCU TCD 0 CEOD
TCU TCD
144 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB8CE
: 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

(CLR)
High (C) (Q) (TC)
(CEO) 0 (CE) High (C)
Low High (Q) CE Low
Q High TC High
1 CEO CE C CLR
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

1 X X 0 0 0
0 0 X 0
0 1 ↑ TC CEO
z = - 1
CEO = TCCE
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 145
2 :

146 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB8CLE
: 8-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear


(CLR) High (C) (Q)
(TC) (CEO) 0 (L) High
Low High (CE) (D)
CE High Low High Q
CE Low Q High TC High
1 CEO CE CL CLR
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 147
2 :

CLR L CE C Dz - D0 Qz - Q0 TC CEO
1 X X X X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X 0
0 0 1 ↑ X TC CEO
z = - 1
CEO = TCCE
148 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB8CLED
: 8-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear


(CLR) High (C) (Q)
(TC) (CEO) 0 (L) High
(C) Low High (CE) (D)
CE HighUP Low Low High Q
CE UP High Q CE Low

Q UP High TC High
Q UP Low TC High
1 CEO CE CUPL CLR
TC CE High CEO (High)
CE TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
CPLD CB2X1CB4X1CB8X1CB16X1

Low CPLD High PRLD

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 149
2 :


CLR L CE C UP Dz - D0 Qz - Q0 TC CEO
1 X X X X X 0 0 0
0 1 X ↑ X Dn Dn TC CEO
0 0 0 X X X 0
0 0 1 ↑ 1 X TC CEO
0 0 1 ↑ 0 X TC CEO
z = - 1
TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP)
CEO = TCCE
150 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB8RE
: 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

(R) High
(C) Low High (Q) (TC)
(CEO) 0 (CE) High (C)
Low High (Q) CE Low
Q High TC High
1 CEO CE C R
TC CE High CEO (High) CE TC
n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

1 X ↑ 0 0 0
0 0 X 0
0 1 ↑ TC CEO
z = - 1
CEO = TCCE
CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 151
2 :

152 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
CPLD
153 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CB8RLE
: 8-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset


(R) High (C) Low High (Q)
(TC) (CEO) 0
(L) High (C) Low High CE D
CE High Low High Q
CE Low Q High TC
High Q CE High CEO High

1 CEO CE CL R
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

CPLD
154 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :

R L CE C Dz - D0 Qz - Q0 TC CEO
1 X X ↑ X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X 0
0 0 1 ↑ X TC CEO
z = - 1
CEO = TCCE
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 155
2 :
CB8X1
: 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear



(CLR) CLR High
(Q) 0 TCU TCD 0 1
CEOU CEOD Low High (L) High (C)
Low High CE D
CEU HighCLR L Low Low High Q
CED HighCLR L Low Q CEU CED Low
CEU CED High CEU CED High
CEOU CEOD
Q CEU High CEOU High
Q LowCED High CEOD High
CEOU CEOD CEU CED
LCLR

Q High CEU TCU
High Q Low CED TCD High
TCU () TCD (
) AND TCUCEOUCEOD
AND CEU
CED Q

156 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
0 (TCU LowTCD High) High PRLD


CLR L CEU CED C Dz - D0 Qz - Q0 TCU TCD CEOU CEOD
1 X X X X X 0 0 1 0 CEOD
0 1 X X ↑ Dn Dn TCU TCD CEOU CEOD
0 0 0 0 X X 0 0
0 0 1 0 ↑ X
TCU TCD CEOU 0
TCU TCD 0 CEOD
TCU TCD
CEOU = TCUCEU
CEOD = TCDCED
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 157
2 :
CB8X2
: 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchronous Reset

CPLD

(R) R High (C)
Low High (Q) 0 TCU TCD
0 1 CEOU CEOD Low High (L)
High (C) Low High CE D

CEU HighR L Low Low High Q
CED HighR L Low Q CEU CED Low
CEU CED High CEU CED
High CEOU CEOD
Q CEU High CEOU High
Q LowCED High CEOD High
CEOU CEOD CEU CED
CL R

Q High CEU TCU
High Q Low CED TCD High
TCU () TCD (
) AND TCUCEOUCEOD
AND CEU
CED Q

158 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
0 (TCU LowTCD High) High PRLD


R L CEU CED C Dz - D0 Qz - Q0 TCU TCD CEOU CEOD
1 X X X ↑ X 0 0 1 0 CEOD
0 1 X X ↑ Dn Dn TCU TCD CEOU CEOD
0 0 0 0 X X 0 0
0 0 1 0 ↑ X
TCU TCD CEOU 0
TCU TCD 0 CEOD
TCU TCD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 159
2 :
CBD16CE : 16-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear


(CLR) High (C) (Q)
(TC) (CEO) 0 (CE) High
(C) Low High High Low (Q) CE
Low Q High TC High
1 CEO CE C CLR
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

1 X X 0 0 0
0 0 X 0
0 1 ↑ TC CEO
0 1 ↓ TC CEO
z = - 1
CEO = TCCE
160 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 161
2 :
CBD16CLE
: 16-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear


(CLR) High (C)
(Q) (TC) (CEO) 0
(L) High Low High (CE)
(D) CE High Low High High
Low Q CE Low
Q High TC High
1 CEO CE CL CLR
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

CPLD
162 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :

CLR L CE C Dz : D0 Qz : Q0 TC CEO
1 X X X X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 1 X ↓ Dn Dn TC CEO
0 0 0 X X 0
0 0 1 ↑ X TC CEO
0 0 1 ↓ X TC CEO
z = - 1
CEO = TCCE
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 163
2 :
CBD16CLED
: 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear


(CLR) High (C)
(Q) (TC) (CEO) 0
(L) High (C) Low High (CE)
(D) CE HighUP Low Low High
High Low Q CE UP High Q
CE Low
Q UP High TC High
Q UP Low TC High
1 CEO CE CUPL CLR
TC CE High CEO (High)
CE TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
CB2X1CB4X1CB8X1CB16X1
Low CPLD High PRLD

CPLD
164 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :


CLR L CE C UP Dz : D0 Qz : Q0 TC CEO
1 X X X X X 0 0 0
0 1 X ↑ X Dn Dn TC CEO
0 1 X ↓ X Dn Dn TC CEO
0 0 0 X X X 0
0 0 1 ↑ 1 X TC CEO
0 0 1 ↓ 1 X TC CEO
0 0 1 ↑ 0 X TC CEO
0 0 1 ↓ 0 X TC CEO
z = - 1
TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP)
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 165
2 :
CBD16RE
: 16-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset


(R) High (C) Low High High
Low (Q) (TC) (CEO) 0
(CE) High (C) Low High High Low
(Q) CE Low Q High
TC High
1 CEO CE C R
TC CE High CEO (High) CE TC
n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

1 X ↑ 0 0 0
1 X ↓ 0 0 0
0 0 X 0
0 1 ↑ TC CEO
0 1 ↓ TC CEO
z = - 1
CEO = TCCE
CPLD
166 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 167
2 :
CBD16RLE
: 16-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset


(R) High (C) Low High
High Low (Q) (TC) (CEO)
0
(L) High (C) Low High High Low
CE D CE High Low High
High Low Q CE Low
Q High TC High Q CE High CEO
High
1 CEO CE CL R
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

CPLD
168 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :

R L CE C Dz : D0 Qz : Q0 TC CEO
1 X X ↑ X 0 0 0
1 X X ↓ X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 1 X ↓ Dn Dn TC CEO
0 0 0 X X 0
0 0 1 ↑ X TC CEO
0 0 1 ↓ X TC CEO
z = - 1
CEO = TCCE
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 169
2 :
CBD16X1 : 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear


(CLR) CLR High
(Q) 0 TCU TCD 0 1
CEOU CEOD Low High (L) High (C) Low
High High Low CE D
CEU HighCLR L Low Low High High Low Q
CED HighCLR L Low Q CEU CED Low
CEU CED High CEU
CED High CEOU CEOD
Q CEU High CEOU High
Q LowCED High CEOD High
CEOU CEOD CEU CED
LCLR

Q High CEU TCU High
Q Low CED TCD High
TCU () TCD (
) AND TCUCEOUCEOD
AND CEU
CED Q

Low CPLD High PRLD

CPLD
170 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :


CLR L CEU CED C Dz - D0 Qz - Q0 TCU TCD CEOU CEOD
1 X X X X X 0 0 1 0 CEOD
0 1 X X ↑ Dn Dn TCU TCD CEOU CEOD
0 1 X X ↓ Dn Dn TCU TCD CEOU CEOD
0 0 0 0 X X 0 0
0 0 1 0 ↑ X
TCU TCD CEOU 0
TCU TCD CEOU 0
TCU TCD 0 CEOD
TCU TCD 0 CEOD
TCU TCD
TCU TCD
CEOU = TCUCEU
CEOD = TCDCED
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 171
2 :
CBD16X2
: 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset



(R) R High (C)
Low High High Low (Q) 0
TCU TCD 0 1 CEOU CEOD Low High
(L) High (C) Low High High Low
CE D
CEU HighR L Low Low High High Low Q
CED HighR L Low Q CEU
CED Low CEU CED High
CEU CED High CEOU CEOD

Q CEU High CEOU High
Q LowCED High CEOD High
CEOU CEOD CEU CED
CL R

Q High CEU TCU
High Q Low CED TCD High
TCU () TCD (
) AND TCUCEOUCEOD
AND CEU
CED Q

172 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
Low CPLD High PRLD


R L CEU CED C Dz : D0 Qz : Q0 TCU TCD CEOU CEOD
1 X X X ↑ X 0 0 1 0 CEOD
1 X X X ↓ X 0 0 1 0 CEOD
0 1 X X ↑ Dn Dn TCU TCD CEOU CEOD
0 1 X X ↓ Dn Dn TCU TCD CEOU CEOD
0 0 0 0 X X 0 0
0 0 1 0 ↑ X TCU TCD CEOU 0
0 0 1 0 ↓ X TCU TCD CEOU 0
0 0 0 1 ↑ X TCU TCD 0 CEOD
0 0 0 1 ↓ X TCU TCD 0 CEOD
0 0 1 1 ↑ X TCU TCD
0 0 1 1 ↓ X TCU TCD
z = - 1
CEOU = TCUCEU
CEOD = TCDCED
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 173
2 :
CBD2CE
: 2-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear


(CLR) High (C) (Q)
(TC) (CEO) 0 (CE) High
(C) Low High High Low (Q) CE
Low Q High TC High
1 CEO CE C CLR
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

1 X X 0 0 0
0 0 X 0
0 1 ↑ TC CEO
0 1 ↓ TC CEO
z = - 1
CEO = TCCE
CPLD
174 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :

UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 175
CPLD
176 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CBD2CLE
: 2-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear


(CLR) High (C)
(Q) (TC) (CEO) 0
(L) High Low High (CE)
(D) CE High Low High High
Low Q CE Low
Q High TC High
1 CEO CE CL CLR
TC CE High CEO (High) CE
TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
Low CPLD High PRLD

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 177
2 :

CLR L CE C Dz : D0 Qz : Q0 TC CEO
1 X X X X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 1 X ↓ Dn Dn TC CEO
0 0 0 X X 0
0 0 1 ↑ X TC CEO
0 0 1 ↓ X TC CEO
z = - 1
CEO = TCCE
178 http://japan.xilinx.com UG606 (v12.1) 2010 4 19
2 :
CBD2CLED
: 2-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear


(CLR) High (C)
(Q) (TC) (CEO) 0
(L) High (C) Low High (CE)
(D) CE HighUP Low Low High
High Low Q CE UP High Q
CE Low
Q UP High TC High
Q UP Low TC High
1 CEO CE CUPL CLR
TC CE High CEO (High)
CE TC n (tCE-TC)
n tCE-TC CE TC
CE CEO CE TC
CB2X1CB4X1CB8X1CB16X1
Low CPLD High PRLD

CPLD
UG606 (v12.1) 2010 4 19 http://japan.xilinx.com 179
2 :


CLR L CE C UP Dz : D0 Qz : Q0 TC CEO
1 X X X X X 0 0 0
0 1 X ↑ X Dn Dn TC CEO
0 1 X ↓ X Dn Dn TC CEO
0 0 0 X X X 0
0 0 1 ↑ 1 X TC CEO
0 0 1 ↓ 1 X TC CEO
0 0 1 ↑ 0 X TC CEO
0 0 1 &