T CHC MY TNH V HP NG

Chng 1

GII THIU

T CHC MY TNH

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Ni dung chng 1

I. Gii thiu t chc my tnh

II. Phng php nghin cu

III. Tng quan t chc my vi tnh

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I. Gii thiu t chc my tnh

1. nh ngha t chc my tnh

2. Mc tiu ca t chc my tnh

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1. nh ngha T Chc My Tnh

Cc thut ng tng ng

Kin trc my tnh Computer Architecture

Cu trc my tnh

T chc my tnh - Computer Organization

T chc my tnh:

Cu trc

My tnh in t

Hot ng

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T chc my tnh (tt)

Cu trc (structure):

Cc thnh phn kt ni to h thng

Hot ng (behavior, function):

Hot ng ca tng thnh phn

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Cu trc h thng

Computer

Main

Memory

Input

Output

Systems

Interconnection

Peripherals

Communication

lines

Central

Processing

Unit

Computer

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Cu trc CPU

Computer Arithmetic

and

Login Unit

Control

Unit

Internal CPU

Interconnection

Registers

CPU

I/O

Memory

System

Bus

CPU

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2. Mc tiu ca t chc my tnh

Thit k my tnh

nh gi hot ng my tnh

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Cc giai on thit k my tnh

Giai on 1:

Dng cc cng lun l to cc mch chc

nng, v d: mch cng, bit nh

Giai on 2:

Dng cc mch chc nng to cc thnh

phn nh b x l, b nh

Giai on 3:

Kt ni cc thnh phn thnh my tnh

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Cc cng lun l c s

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Mch cng 1 bit

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Bit nh dng mch ci D

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II. Phng php nghin cu

1. Phn loi my tnh

2. Cu trc my tnh

3. Hot ng ca my tnh

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1. Phn loi my tnh

Phn loi theo th t xut hin

Lch s my tnh

Phn loi theo kh nng hot ng

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S lc lch s my tnh

Th h my tnh

Cng ngh phn cng

Nguyn l hot ng phn mm

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S lc lch s my tnh (tt)

Th h 1 n in t (1945-1953)

Tun t; ngn ng my

Th h 2 Transistor (1954-1965)

Dng batch; ngn ng cp cao

Th h 3 Mch tch hp (IC) (1965-1980)

Dng a chng

Th h 4 Mch tch hp mt cao (1980-)

Dng a chng hin i

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Cc linh kin ch to phn cng my tnh

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Phn loi my tnh theo kh nng hot ng

My vi tnh Microcomputer

Personal Computer (PC)

My tnh nh Minicomputer

My tnh ln Mainframe

Siu my tnh Supercomputer

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Hiu sut cc b x l Intel

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Cc n v

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2. Cu trc my tnh

Cu trc my tnh dng n gin

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Cu trc my tnh Von-Neumann

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Cu trc my tnh Von-Neumann (tt)

B x l trung tm CPU

n v iu khin Control Unit

n v lun l s Arithmetic Logical Unit

B nh Memory

H thng xut nhp Input/Output (I/O)

C kh nng thc hin cc lnh tun t

theo chu k ly-gii m-thc hin lnh

(Chu k lnh)

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3. Hot ng ca my tnh

Thc hin chng trnh (program)

Chng trnh gm mt chui cc lnh/ch

th (instruction) thuc tp lnh ca CPU

Chu k nhp-x l-xut

Nhp chng trnh, d liu

Thc hin chng trnh

Xut kt qu

n v hot ng: thc hin mt lnh

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Chu k lnh

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Chu k lnh (tt)

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Hot ng ca my tnh theo cc lp lun l

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Phng php nghin cu

Kho st t chc my tnh theo

cc thnh phn cu trc

Mn hc t chc my tnh v hp ng

t chc my vi tnh v hp ng

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III. Tng quan t chc my vi tnh

1. T chc vt l

2. Tng quan v phn mm

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1. T chc vt l my vi tnh

System Unit

Power Supply

Mainboard, CPU, RAM

Expansion boards: video, network, sound,

Drives: Floppy, Hard, CD/DVD

Monitor

Keyboard, mouse

Speaker, Printer, Scanner, Modem,

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Cu trc vt l

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Cc u ni (connectors)

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Bn trong system unit

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V d 1: Mainboard

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V d 2: Mainboard Intel D875PBZ

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V d 2 (tt)

1. Pentium 4 socket

2. 875P Support chip

3. Memory sockets

4. AGP connector

5. Disk interface

6. Gigabit Ethernet

7. 5 PCI slots

8. USB 2.0 ports

9. Cooling technology

10. BIOS

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Qu trnh khi ng

Power Supply Ngun cp in

ROM BIOS

ROM extensions ROM m rng

Video Card mn hnh,

Boot Drive a khi ng

Boot record Mu tin khi ng

Operating system H iu hnh

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2. Tng quan v phn mm

Phn mm h thng

Phn mm ng dng

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Phn mm ng dng

X l vn bn Word Processor Microsoft Word, Corel WordPerfect

Bng tnh Spreadsheet Excel, Lotus 1-2-3

Qun tr c s d liu Database Access

ho Graphics Multimedia, Games, CAD (Computer-Aided Design)

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Phn mm ng dng mng

Web Browser

Internet Explorer, Netscape

Web-based Applications

E-Mail

Microsoft Outlook, Web-Mail

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Phn mm h thng

H iu hnh

(Operating System)

Chng trnh cng c, tin ch

(Tools, Utilities)

Cng c lp trnh

(Programming Tools)

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H iu Hnh

Vi ngi s dng

c np vo b nh u tin

Qun l cc chu k nhp-x l-xut

Vi chng trnh/ngi lp trnh

M rng phn cng my tnh

Qun l ti nguyn h thng

V d: Microsoft Windows, Linux, UNIX,

MAC OS, .

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Chng trnh cng c, tin ch

H tr qun l h thng

V d: Norton Commander

Norton Ghost/Antivirus

H tr s dng h thng hiu qu hn

V d: Download Accelerater

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Cng c lp trnh

Ngn ng lp trnh

Ngn ng my Machine language

dng nh phn ca tp lnh CPU

Ngn ng dng k hiu / Hp ng

Symbolic language / Assembly language

dng k hiu/gi nh ca tp lnh CPU

Ngn ng cp cao High-level language

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Thc thi chng trnh hp ng

Vit chng trnh ngun dng hp ng

Dng chng trnh dch hp ng

(Assembler) chuyn i chng trnh

ngun thnh chng trnh thc thi (trn

ngn ng my tng ng vi mt h iu

hnh).

Thc hin chng trnh trn ngn ng

my

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Thc thi chng trnh ngn ng cp cao

Vit chng trnh ngun dng ngn ng

cp cao

C hai phng php thc thi:

Bin dch

Thng dch/Phin dch

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Bin dch (compilation)

Dng chng trnh bin dch (Compiler)

chuyn chng trnh ngun thnh chng

trnh trn ngn ng my

Thc thi chng trnh trn ngn ng my

Thc thi nhanh

Cn bin dch li khi c thay i

V d: ngn ng C,C++,

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Thng dch (Interpretation)

Dng chng trnh thng dch

(Interpreter) c v thc thi tng pht

biu trn chng trnh ngun

Lun cn chng trnh ngun

Thc thi chm hn

V d: Basic, Scripting language,

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JAVA

C th thc thi trn mi mi trng

Thc thi chng trnh Java:

Qu trnh bin dch

Qu trnh thng dch trn JVM

(Java Virtual Machine)

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Mi trng lp trnh Java

II

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Thc thi chng trnh Java

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Mn hc T chc my tnh v Hp ng

Phn T CHC MY TNH

Chng 1 Gii thiu t chc my tnh

Chng 2 Bus

Chng 3 B x l

Chng 4 B nh

Chng 5 Tp lnh

Chng 6 Mt s dng kin trc my tnh

Phn HP NG

T CHC MY TNH V HP NG

Chng 2

BUS

(H THNG VN CHUYN THNG TIN)

Ni dung chng 2

I. Cc khi nim c bn

II. Cu trc my vi tnh

III. Mt s thit b ngoi vi

I. Cc khi nim c bn

1. Khi nim v Clock

2. Bus

3. Cc tiu chun bus

1. Khi nim v Clock

Cn kim sot v thi gian trn h thng:

C s tr (delay) ca tn hiu

Kim sot th t thc hin

Hai k thut c bn:

ng b - Synchronous

dng thm tn hiu clock (xung nhp)

Bt ng b - Asynchronous

dng thm cc tn hiu bt tay

Tn hiu clock

Rising Edge: Cnh ln

Falling Edge: Cnh xung

High: Mc cao

Low: Mc thp

Thng s ca clock

Tn s - Frequency: s chu k trong 1 giy

Chu k - Cycle: chiu di 1 chu k

V d:

1GHZ = 109 chu k/giy

1 chu k = 10-9 giy = 1 nano giy

Tc dng ca clock

Mi thao tc c thc hin trong thi gian

bng mt s nguyn chu k clock

V d:

Lnh cng 1 chu k

CPU c 1 t nh - 3 chu k

chu k 1: pht a ch

chu k 2: ch

chu k 3: c d liu

2.Bus

Bus: ng dn tn hiu chung gia cc

thit b

Cc thnh phn trn bus

Data bus Bus d liu

Truyn d liu

Kch thc: 8, 16, 32, 64 bit hiu sut

Address bus Bus a ch

Xc nh thit b gi, nhn d liu

Kch thc kh nng qun l b nh

Control bus Bus iu khin

Tn hiu clock

c, ghi b nh v thit b I/O

H thng my tnh vi nhiu bus

3. Cc tiu chun bus

PC bus 8 bit

ISA (Industry Standard Architecture) bus

16 bit

PCI (Peripheral Component Interconnect)

bus 32/64 bit

Thng s cc loi bus

ISA bus

Bus d liu: 16 bit

Xung nhp (Clock): 8.33 MHz

Bng thng (bandwidth) ~ 16.7 MB/sec

PCI bus

Do Intel thit k, c lp vi CPU

Bng thng rng

H tr Plug-and-Play

(thit lp cu hnh t ng)

PCI 1.0, 2.0, 2.1, 2.2

PCI bus (tt)

Bus d liu: 32 bit, 64 bit

Xung nhp: 33 MHz, 66 MHz

Bng thng (bandwidth) ~ 133MB/sec

~ 528MB/sec

PCI slots

PCI Express bus

Pht trin kin trc PCI

tng thch vi PCI

Bng thng rng

Bt u t 200 MB/sec, c th x2, ..,x32

H tr tt hn cho truyn thng,

a phng tin (audio, video)

Thm bt thit b khi my hot ng

(Hot plugging)

PCI Epress (tt)

PCI Express (tt)

PCI Epress (tt)

PCI Express slots

PCI Express slots (x4,x16,x1,x16) v PCI slot

II. Cu trc my vi tnh

1. Cu trc my vi tnh

2. Cc thao tc c s

3. Cc phng php xut nhp

1. Cu trc my vi tnh

1 CPU hay nhiu CPU

(SMP, Symmetric MultiProcessor)

B nh

Cc thit b I/O

Mch iu khin (Controller)

Thit b (Device)

Cc loi bus

Cu trc tiu biu my vi tnh Pentium

Cu trc tiu biu my vi tnh Pentium 4

Cc thnh phn chnh trn mainboard

Kt ni cc thnh phn trn mainboard

AGP (Accelerated Graphics Port)

AGP (Accelerated Graphic Port)

Do Intel thit k

Tng tc hin th hnh 3D, hnh ng

Dng 1 bus ring (AGP)

Chip AGP c th ng thi truy cp b

nh vi CPU

Bng thng 533 MB/sec

SCSI (Small Computer System Interface)

Dng I/O bus, iu khin nhiu loi thit

b: a cng, CDROM, scanner, my in ..

C th n 15 thit b/cp

Mt s thng s SCSI

IDE (Integrated Drive Electronics)

Cn gi l ATA (AT Attachment)

EIDE (Extended IDE) ATA-2

4 thit b

iu khin CDROM

H tr LBA (Logical Block Addressing)

ATA-4 Ultra ATA

ATA-33/66/100 ..: tc DMA l 33MHz/..

Serial ATA (SATA)

Tc cao, t 150 MB/sec

Ch iu khin a

D ci t

Serial ATA (tt)

USB (Universal Serial Bus)

Kt ni cc thit b t ngoi (external)

c im:

Thng nht u ni

Cp ngun

Thm bt khi my hot ng (Hot-plugging)

T ng thit lp cu hnh (Plug-and-Play)

Tc : 12 Mbps(1.0), 450 Mbps(2.0)

7 thit b, c th n 127 thit b vi Hub

V d USB hub

2. Cc thao tc c s

Tnh ton, thc thi bn trong CPU

c ghi b nh

c ghi thit b xut nhp

3. Cc phng php xut nhp

Xut nhp theo chng trnh

Programmed I/O

Xut nhp dng k thut ngt

Interrupt-driven I/O

Xut nhp dng k thut truy xut

trc tip b nh

Direct Memory Access (DMA)

a ch thit b xut nhp (a ch I/O)

Memory mapped I/O

Thit b v b nh dng chung mt khng

gian a ch

Xut nhp tng ng c ghi b nh

Khng cn lnh I/O

Isolated I/O

Dng khng gian a ch ring

Cn tn hiu iu khin I/O ring

Cn cc lnh I/O

Xut nhp theo chng trnh

CPU trc tip iu khin I/O

Kim tra trng thi thit b

Dng cc lnh c/ghi

Trao i d liu

CPU phi ch thit b hon thnh thao tc

nh k kim tra trng thi thit b

Lng ph thi gian CPU

Thng s thit b: a ch I/O

Xut nhp dng k thut ngt

c im:

CPU khng phi ch

CPU khng cn kim tra thit b hon

thnh thao tc

Thit b yu cu ngt qung khi sn sng

Xut nhp dng k thut ngt (tt)

Yu cu:

Phn cng PIC (Programmable Interrupt

Controller)

Chng trnh x l ngt qung (Interrupt

Handler):

Thuc h iu hnh

Thuc chng trnh ng dng

V d: CPU c 1 thit b dng ngt

CPU pht lnh c

Thit b ly d liu trong khi CPU thc

hin vic khc

Thit b ngt qung CPU

CPU yu cu d liu

Thit b truyn d liu

Chuyn iu khin khi c ngt

Thng s thit b dng ngt

I/O address

a ch I/O

IRQ i (Interrupt ReQuest)

Yu cu ngt

Xut nhp dng DMA

C phn cng h tr DMAC (DMA

Controller)

DMAC thay th CPU thc hin trao i

d liu gia b nh v thit b

Hot ng DMA

CPU khi ng DMAC:

a ch thit b

a ch vng nh

Chiu trao i d liu

Kch thc d liu

CPU thc hin vic khc

DMAC thc hin trao i d liu

DMAC gi tn hiu ngt khi hon thnh

Thng s thit b dng DMA

I/O address

a ch I/O

IRQ i (Interrupt ReQuest)

Yu cu ngt

DMA channel

Knh DMA

III. Mt s thit b ngoi vi

1. a t

2. CD, DVD

3. Mn hnh

4. My in

1. a t

a cng vi 4 a

Cu trc mt mt a

a t (tt)

Track, Sector, Cylinder

n v truy xut: sector

Cc bc truy xut sector:

Di chuyn h thng u t n cylinder cha sector Seek time (mili sec)

Ch sector xoay n v tr u t - Rotational latency (rpm)

Truy xut sector

Thng s tng qut: tc truy xut

(Data Transfer Rate) theo MB/sec

a t (tt)

Thng s cc loi a mm

2. Gii thiu CD v DVD

a. CDROM

b. DVD

a. CDROM

a CDROM

ng knh: 120mm

Dy: 1.2mm

Dung lng: 650MB/70pht, 700MB/80pht

Lp nha, 1 hay 2 lp kim loi, lp bo v

Thng s a CD (CD Drive):

Loi (internal/external)

Giao tip bus (IDE/SCSI)

Tc (theo n v 1x = 150 KB/sec)

Cu trc lun l a CDROM

Cu trc vt l a CDROM

a CD

Cc dng a CDROM

CDROM

CD Recordable

CD Rewritable

Cu trc a CD-Recordable

2. DVD (Digital Versatile Disk)

Hnh thc a v a DVD tng t CD

c im so vi CDROM:

Dung lng ln hn (4.7GB)

Dng loi tia laser tn s cao hn

Tc truy xut cao hn (1.4MB/sec)

Cc loi dung lng a DVD

a DVD dng hai mt, hai lp

Cc dng a DVD

DVD

DVD Recordable

DVD Rewritable

3. Mn hnh

Hai dng thng dng:

Dng n hnh CRT

Dng tinh th lng LCD

Mn hnh dng CRT (Cathod Ray Tube)

a. CRT b. Qut tia in t

Mn hnh LCD (Liquid Crystal Display)

Hot ng mn hnh LCD

Thng s mn hnh CRT

Dot pitch Kch thc im nh, v d

0.22mm

Refresh rate Tc lm ti (hz)

Resolution phn gii

Monitor screen size Kch thc mn

hnh, v d 17

Display colors S mu

Thng s mn hnh LCD

Resolution - phn gii

Theo kch thc (screen size)

Viewing angle Gc nhn

Khong 120 170

Brightness sng

Theo candelas/cm2 Khong 250 500

tng phn Contrast ratio

T s gia trng/en Khong 450 1000

Tc p ng Response rate

Tc thay i mu Theo milisec

Mt s phn gii mn hnh

Kch thc mn hnh

4. My in

Cc loi my in:

In kim Dot-matrix printer

In phun InkJet

In laser Laser printer

Thng s chnh:

phn gii dots per inch (dpi)

Tc in pages per minute (ppm)

My in phun

My in Laser

T CHC MY TNH V HP NG

Chng 3

B X L

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Ni dung chng 3

I. Cu trc b x l

II. Cc phng php nng cao kh nng

hot ng CPU

III. V d CPU INTEL 32 bit

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I. Cu trc b x l

1. Cu trc b x l

2. Thanh ghi

3. n v x l

4. n v iu khin

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1. Cu trc b x l

Cc thanh ghi

n v x l

n v iu khin

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CPU v system bus

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Cu trc trong CPU

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V d: Ly lnh

Thanh ghi PC cha a ch lnh tip theo

a ch chuyn vo thanh ghi MAR

a ch a ln bus a ch

n v iu khin yu cu c b nh

Kt qu a ln data bus, sao chp vo

thanh ghi MBR, a vo thanh ghi IR

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Dng d liu ca giai on ly lnh

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2. Thanh ghi (registers)

Thanh ghi = nh bn trong CPU

Ni lm vic trong CPU

Hai dng thanh ghi:

User visible registers: s dng bi phn

mm

Control and status registers: s dng bn

trong CPU

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User visible registers

a nng (General Purpose, GP)

D liu (Data)

a ch (Address)

M iu kin (Condition codes)

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Control and Status registers

Program Counter (PC)

B m chng trnh

Instruction Decoding Register

Thanh ghi lnh

Memory Address Register

Lu a ch khi truy xut b nh

Memory Buffer Register

Lu gi tr t nh

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V d thanh ghi

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3. n v x l

Thc hin cc thao tc x l c s

ALU - Arithmetic Logical Unit

(n v s hc lun l)

Thao tc s hc: cng, tr, nhn, chia

Thao tc lun l: NOT, AND, OR, XOR

Integer Execution Unit

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Cc dng n v x l

Floating-Point Execution Unit (FPU)

Thc hin x l trn s du chm ng

MMX Execution Unit

Thc hin x l trn d liu MMX

Multimedia Unit

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4. n v iu khin

Thc hin ly lnh, gii m lnh

To cc tn hiu iu khin bus

iu khin n v x l

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Hai phng php iu khin n v x l

Tn hiu (hard-wired control)

Chng trnh (microprogrammed control)

chng trnh bn trong n v iu khin

vi chng trnh (microprogram)

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Hard-wired control unit

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Microprogrammed control

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Thng dch lnh bng vi chng trnh

B nh B nh

iu khin

Lnh i Vi

chng trnh Thng dch

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Vi lnh

Vi chng trnh bao gm cc vi lnh

(MicroInstruction)

Mt vi lnh gm cc bit tng ng vi

mt nhm tn hiu

Kin trc trong ca CPU: vi kin trc

(MicroArchitecture)

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Dng

tn hiu

Dng

vi chng trnh

Tc thc thi mt lnh Nhanh hn Chm hn

S lng lnh t hn Nhiu hn

Chng trnh bin dch Phc tp hn n gin hn

V d SPARC, PowerPC Intel CPU

Dng kin trc my tnh RISC CISC

So snh hai dng thc hin n v x l

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II. Cc phng php nng cao

kh nng hot ng CPU

1. Tc ng clock bn trong CPU

2. Thc hin lnh song song

3. C ch ng ng

4. Cache

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1. Tc ng clock bn trong CPU

Tng tn s clock trong CPU (internal

clock / clock subcycle) tng tc thc hin lnh

Clock bn trong CPU c iu khin

bi clock trn mainboard (external clock)

Tn s internal clock l bi s ca tn s

external clock

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2. Thc hin lnh song song

Phn loi Flynn

Thc hin lnh song song trn b vi x l

My vi tnh nhiu b x l

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Phn loi kin trc my tnh theo Flynn

SISD Single Intruction stream

Single Data stream

SIMD Single Intruction stream

Multiple Data stream

MISD Multiple Intruction stream

Single Data stream

MIMD Multiple Intruction stream

Multiple Data stream

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Thc hin lnh song song trn b vi x l

Thc hin nhiu lnh trong mt chu k

clock

CPU Intel:

Lnh SIMD

Cu trc superscalar

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V d: superscalar processor

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My tnh nhiu b x l

Kin trc SMP (Symmetric MultiProcessor)

Nhiu b x l

Dng chung b nh

Truyn thng qua b nh

Kin trc MMP (Massively Parallel Processors)

Nhiu b x l

B nh phn tn

Truyn thng qua mng

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3. C ch ng ng (Pipelining)

B x l gm cc phn t x l c lp

Processing Elements/Stage

Hot ng nh dy chuyn sn xut

Ti mt thi im:

Si thc hin lnh j, a kt qu cho Si+1

Si-1 thc hin lnh j+1, a kt qu cho Si

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V d c ch ng ng

a. B x l c 5 stage

b. Trng thi cc stage trong 9 clock v 9 lnh

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V d c ch ng ng (tt)

Mi lnh phi thc hin trong 5 clock qua

5 stage

T lnh 2 coi nh ch cn 1 clock thc

hin 1 lnh

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M rng c ch ng ng

Hai ng ng vi 5 phn t

dng chung phn t ly lnh

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Lnh r nhnh (Branch instruction)

if (i= =0) CMP i,0 ; so snh i, 0

k = 1; BNE Else ; r n Else nu i 0

else Then: MOV k,1 ; gn k = 1 nu i = 0

k = 2; BR Next ; r khng iu kin

Else: MOV k,2 ; gn k = 2

Next:

(a) (b)

Mt dng r nhnh: pht biu IF

Dng hp ng tng ng

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Lnh r nhnh (tt)

Khi c lnh r nhnh th c ch ng

ng b mt tc dng

Cc dng r nhnh

C iu kin: IF, Loop

Khng iu kin

T l lnh r nhnh: 20 30 %

X l: D on r nhnh

(Branch Prediction)

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4. Cache

a. Khi nim

b. Hot ng

c. Phn loi

d. Thay th phn t

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a. Khi nim cache

B nh dung lng nh, tc cao

Gip CPU truy xut b nh nhanh hn

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b. Hot ng cache

Gi s CPU c 1 khi nh k ln

Nu khng c cache:

CPU c khi trn b nh k ln

Nu c cache:

Ln 1: CPU c khi trn b nh v ghi

khi vo cache

k-1ln cn li: CPU c khi trn cache

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T s thnh cng (hit ratio, h)

Xt k:

k >> 1: h 1, ch truy xut trn cache

k = 1: cache l c hi

Truy xut trn cache: cache hit

Khng truy xut c trn cache: cache miss

S ln truy xut thnh cng trn cache k -1

Tng s ln truy xut k

h =

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Hot ng khi c cache

Khi CPU cn truy xut 1 khi nh, CPU

tm khi trn cache.

Nu khi c trn cache:

CPU truy xut khi trn cache

Nu khi cha c trn cache:

CPU truy xut khi trn b nh

CPU ghi khi vo cache

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c. Phn loi cache

Cache cp 1 First level cache (L1)

trong CPU

Kch thc nh (vi chc KB)

Cache cp 2 Second level cache (L2)

ngoi CPU

Kch thc ln (vi trm KB)

41

Cc loi cache

42

Disk cache

M rng khi nim cache: gip CPU truy

xut cc loi a nhanh hn

Dng phn cng: linh kin nh trn cc

a cng, CD

Dng phn mm: dng mt phn b nh

trong lm disk cache

43

d. Thay th phn t trn cache

Khi cache y m cn ghi thm vo cache

th phi thay th mt phn t trn cache

Nu phn t b thay th c thay i ni dung

thi phi ghi tr li b nh

C cc phng php chn phn t thay

th: Optimal, FIFO, LRU (thng dng)

Least Recently Used (LRU): chn phn

t tn ti trn cache trong khong thi

gian ln nht m khng c s dng

44

III. V d CPU INTEL 32 bit

1. Gii thiu

2. Cc ch hot ng

3. K thut siu phn lung

(Hyper-Threading)

4. K thut a li (multi-core)

5. Cc CPU Intel 32 bit

6. Cu trc trong Pentium 4

45

1. Gii thiu

Intel Architecture 32 IA32

Cc thanh ghi 32 bit

Cc n v x l kch thc 32 bit

Intel 64 Architecture

Cc thanh ghi 64 bit

C thm ch hot ng 32 bit m rng

(IA-32e)

46

Cc CPU 32 bit

80386/80486

Pentium (1993)

P6 family (1995-1999)

Pentium Pro, Pentium II, Celeron, Pentium III, Pentium III Xeon

Pentium 4 (2000-2006)

Xeon (2001-2006)

Pentium M (2003-x)

Pentium Processor Extreme Edition (2005-2007)

Core Duo v Core Solo (2006-x)

47

Gii thiu (tt)

Xeon

Cache L2 ln hn

Tc cao hn

Dng cho server

Celeron

Cache cp 2 nh hn

Dng PPGA (Plastic Pin Grid Array)

Gim gi thnh

48

2. Cc ch hot ng

Protected mode Ch bo v

Trng thi chnh ca CPU

Thc hin mi lnh vi hiu sut cao nht

C th thc hin cc phn mm vit trn ch

thc trong Virtual-8086 mode

Real-address mode Ch thc

Mi trng lp trnh nh 8086 c thm vi

m rng

CPU ch thc khi cp in hay reset

49

Cc ch hot ng (tt)

System Management Mode (SMM)

Ch qun tr h thng

Chuyn sang mt khng gian a ch khc

v gi nguyn trng thi CPU

phc v cho cc h iu hnh thc hin standby, power management, security

Khi tr v t SMM, CPU phc hi li trng

thi trc

50

3. K thut siu phn lung

Tng hiu sut cc CPU Intel 32 bit khi

thc thi ng dng v h iu hnh a

lung (multi-threaded) hay ng dng n

lung (single-threaded) trong mi trng

a chng

Cho php mt CPU vt l thc hin nhiu

lung (thread) ng thi

51

Kin trc siu phn lung

Mt CPU vt l bao gm 2 hay nhiu

CPU lun l vi cc trng thi kin trc

IA-32

Cc CPU lun l dng chung phn nhn

ca CPU vt l l phn giao tip bus v

phn thc hin lnh

52

So snh siu phn lung v a x l

53

Yu cu hin thc siu phn lung

CPU h tr siu phn lung

BIOS v Chipset h tr siu phn lung

H iu hnh tn dng k thut siu phn

lung

54

4. K thut a li (multi-core)

Tng kh nng phn cng siu phn

lung bng cch s dng hai hay nhiu

li thc thi (execution core) trong mt

CPU vt l (physical package)

Cc CPU a li:

Pentium Processor Extreme Edition

Pentium D

Intel Core

Intel Core 2

55

Kin trc a li

56

Kin trc a li (tt)

57

5. Cc CPU Intel 32 bit

58

CPU Intel 32 bit (tt)

59

CPU Intel 32 bit (tt)

60

CPU Intel 32 bit (tt)

61

CPU Intel 32 bit (tt)

62

Cc loi CPU Intel

63

Mt s loi CPU Core 2 Duo

64

Mt s loi CPU Pentium D

65

6. Cu trc trong Pentium 4

Pentium 4 dng vi kin trc NetBurst:

Thc hin lnh nhanh:

ALU nhanh gp hai tn s CPU

Thao tc s nguyn c bn thc hin trong clock

C ch ng ng:

C th n 126 lnh

Cache L1 c cc loi:

D-Cache: dng cho d liu

Ececution Trace Cache lu cc lnh c gii

m (decoded instrutions)

66

Cu trc CPU Pentium 4

67

Hot ng c bn

C ch ng ng vi 3 n v x l:

Front end: ly v gii m lnh

Execution: thc thi cc vi lnh

Out of order control: h tr x l ng

thi cc vi lnh, lu tr kt qu

Cc n v phi hp hot ng theo ROB

(ReOder Buffer)

68

Hot ng c bn (tt)

Front end: ly lnh, chia thnh cc vi lnh v

lu trn ROB

Execution : ly cc vi lnh t ROB v thc thi.

Out of order control :hon tt cc vi lnh, lu kt qu ln cc thanh ghi

Cc vi lnh n ROB theo th t, thc thi khng

cn ng th t, kt qu lu theo th t.

69

CPU Pentium 4 PGA 775 v Pentium 4 M

T CHC MY TNH V HP NG

Chng 4

B NH

2

Ni dung chng 4

1. T chc th bc ca b nh

2. B nh trong

3. Gii thiu b nh o

3

I. T chc th bc ca b nh

4

S thay i tnh cht theo th bc

Gi thnh gim

Dung lng tng

Thi gian truy xut tng

B x l gim truy xut

5

Nguyn l a phng

C 3 dng truy xut a phng:

Phn t truy xut trong qu kh gn

thng c truy xut trong tng lai gn

Vic truy xut thng c thc hin

trn mt vng nh lin tc

Cc lnh thng c truy xut tun t

6

Nguyn l i phng

v t chc th bc b nh

Khi cn truy xut CPU tm d liu trn

vng nh cp trn

Nu khng c (miss) th chuyn mt

vng nh bao gm d liu cn truy xut

t vng nh cp thp hn

7

II. B nh trong

1. Bit nh

2. T chc b nh

3. Phn loi linh kin nh

4. Tnh cht b nh

8

1. Bit nh

Bit nh dng mch ci D

Trng thi ghi:

CK = 1 Q = D

Trng thi c:

CK = 0 Q khng i gi tr

9

Bit nh (tt)

L n v cu to b nh

C kh nng nh 1 bit

D liu thay i khi c ghi d liu khc

10

2. Thanh ghi

a. Thanh ghi 4 bit b. S khi

11

Thanh ghi (tt)

Thanh ghi l nh t trong CPU

Lu cc gi tr trung gian, thng tin iu

khin

12

3. T chc b nh

B nh gm cc nh

Mi nh c mt a ch

nh l n v hot ng ca b nh

Hai trng thi hot ng:

c

Ghi

13

Yu cu t chc b nh

S tn hiu khng tng tuyn tnh theo

dung lng b nh

C th ghp cc vi mch nh to b nh

ln hn

14

V d

Vi mch nh 512KB

15

Cc nhm tn hiu

a ch

c 19 tn hiu v c 512K = 219

nh

c n tn hiu a ch nu c 2n nh

l ng vo

D liu

c 8 tn hiu v nh c 8 bit

c m tn hiu nu nh c m bit

l ng vo (trng thi ghi),

l ng ra (trng thi c)

16

Cc nhm tn hiu (tt)

iu khin

CS (Chip select): chn vi mch

WE (Write Enable): phn bit c v ghi

OE (Output Enable): cho php ng ra

17

4. Phn loi linh kin nh

ROM (Read Only Memory)

RAM (Random Access Memory)

18

ROM

B nh ch c (d liu c)

Khng mt d liu khi khng cp in

Dng cho ROM BIOS, ROM Extensions,

vi chng trnh

Phn loi theo cch ghi d liu

FIRMWARE = Hard software

19

Cc loi ROM

ROM Read Only Memory

Nh sn xut ghi

PROM Programmable ROM

Ngi s dng ghi 1 ln

Dng WORM (Write-Once-Read-Many)

EPROM Erasable PROM

Ngi s dng c th xo ton b d liu vi thit b xo dng tia cc tm

EEPROM Electrically EPROM

Ngi s dng c th xo tng byte d liu bng in, khng cn thit b xo

20

Cc loi ROM (tt)

Flash memory

l dng EEPROM

c th ghi, xo theo khi d liu

nhanh hn EEPROM

21

RAM

B nh c th c, ghi

Mt d liu khi khng cp in

C 2 dng chnh

SRAM Static RAM: RAM tnh

DRAM Dynamic RAM: RAM ng

22

RAM tnh

Cu to t cc bit nh dng tng t

mch ci D

So snh vi RAM ng:

Truy xut nhanh hn

Gi thnh cao hn

Tiu th nhiu nng lng hn

Mt tch hp (s bits/chip) t hn

Dng lm cache

23

RAM ng

Cu to t mch dng t in

Mt d liu sau mt khong thi gian xc

nh d vn c cp in

cn phi ghi li d liu ang lu tr

dng mch lm ti (refresh) trn

vi mch nh

Dng lm b nh chnh (main memory),

b nh mn hnh (video memory)

24

RAM ng

25

Phn loi RAM ng

Theo hnh thc

SIMM (Single Inline Memory Module)

DIMM (Dual Inline Memory Module)

RIMM (Rambus Inline Memory Module)

Theo hot ng

RAM DAC

SDRAM

DDR-SDRAM

RDRAM

26

SIMM v DIMM

SIMM DIMM

72 tn hiu 168 tn hiu

27

SIMM, DIMM v SO (Small Outline) DIMM

28

RIMM

RIMM 184 tn hiu

29

Cc loi RAM ng

RAMDAC (RAM Digital-Analog Converter)

Dng cho video RAM

SDRAM (Synchronous DRAM)

ng b vi system clock

Truyn d liu theo khi

DDR-SDRAM (Double Data Rate-SDRAM)

Gi d liu 2 ln trong 1 chu k clock

DDR2 Dual-Channel DDR

Dng hai knh b nh

30

Cc loi RAM ng (tt)

RDRAM (Rambus DRAM)

Dng vi Pentium-4, Itanium

Tc clock cao, t 400 Mhz

SLDRAM (Synchronous-Link DRAM)

64 bit d liu

Gi d liu 2 ln trong 1 chu k

31

Memory Controller (thuc v ChipSet)

32

Dual-Channel memory (DDR2)

33

Dual-Channel memory (DDR2) (tt)

34

Bng thng

35

5. Tnh cht b nh

Dung lng b nh l ly tha ca 2

Thng s chnh:

Thi gian truy xut (access time)

Thi gian t khi c a ch n khi d liu

n nh

Tc truy xut (transfer rate)

Tnh theo bytes/giy

36

III. Gii thiu b nh o

1. Khi nim b nh o

2. B nh o dng phn trang

3. B nh o dng phn on

4. B nh o dng phn on c phn

trang

37

1. Khi nim b nh o

B nh o (virtual memory):

K thut do h iu hnh, c h tr ca

phn cng

Cho php thc hin chng trnh ln hn

b nh trong bng cch s dng b nh

ngoi

Hot ng dng overlay t ng

B nh o = b nh trn a

38

Hot ng b nh o

Chng trnh c vit trn khng gian

a ch o, l thng s ca CPU v h

iu hnh

Khi thc thi, h iu hnh:

np chng trnh vo b nh

chuyn i a ch o thnh a ch vt l

truy xut trn b nh vt l

39

Cc dng b nh o

Dng phn trang (paging)

Dng phn on (segmentation)

Dng phn on c phn trang

(Paged segmentation /

Segmentation with paging)

40

2. B nh o dng phn trang

a. T chc phn trang

b. Chuyn i a ch

c. Np trang

d. Thay th trang

41

a. T chc phn trang

Khng gian a ch o chia thnh cc

trang (page)

B nh c chia thnh cc khung trang

(page frame), cha c mt trang

Cc trang ca mt chng trnh khi trn

b nh khng cn cc v tr lin tc

S trang >> s khung

C bng trang (page table) qun l cc

trang

42

Bng trang

C N dng, vi N l s trang

mi dng tng ng vi 1 trang

Cu trc 1 dng:

Valid bit

Valid = 0 nu trang cha c trn b nh

Valid = 1 nu trang ang c trn b nh

Frame Number (Frame #)

S th t khung trang ang cha trang

43

V d

B nh o c 8 trang, b nh vt l c 4 khung

Bng trang c 8 phn t

44

b. Chuyn i a ch

a ch o theo phn trang

Page Number: s th t trang

Offset: a ch trong trang

a ch vt l

Page Number: s th t khung trang

Offset: a ch trong khung trang

Offset Page Number

Offset Frame Number

45

S chuyn i a ch

46

Truy xut d liu theo a ch o

Tch page # v offset t a ch o

Chuyn page # thnh frame # bng cch

truy xut bng trang

A. Tm phn t qun l trang

B. Kim tra valid bit

1. Valid = 1

a. Thay page # bng frame #

b. Truy xut d liu trn khung vi v tr offset

47

Truy xut d liu theo a ch o (tt)

2. Valid = 0 li trang

a. Tm trang trn a

b. Tm mt khung trng (c th phi thay th

trang nu cc khung y)

c. Sao chp trang vo khung trng

d. Cp nht bng trang (valid = 1, frame # mi)

e. Thc hin truy xut nh bc 1

48

Phn cng h tr chuyn i a ch o

TLB (Translation Look-aside Buffer)

trong CPU

Cache cc phn t trn bng trang

Khi chuyn i a ch, tm phn t qun

l trang trn TLB trc, nu khng c th

tm trn bng trang

49

S chuyn i a ch vi TLB

50

c. Np trang

C 2 phng php:

Np theo yu cu

Np trang khi c li trang

Np trc

Np trc cc trang theo cc iu kin xc

nh

51

d. Thay th trang

Khi cc khung y m cn np thm trang th phi thay th mt trang ang c trn khung

Nu trang b thay th c thay i ni dung th phi a ra a

C cc phng php chn phn t thay th: Optimal, FIFO, LRU (thng dng)

Least Recently Used (LRU): chn trang khng c truy xut trong khong thi gian ln nht

52

3. B nh o dng phn on

T chc phn on

B nh o bao gm cc on (segment)

c kch thuc khng c nh

Khi np on vo b nh th h iu hnh

tm khong trng np on

C bng on qun l cc on

53

Nhn xt v phn trang, phn on

Trang trong sut i vi ngi lp trnh

Phn trang trnh c phn mnh bn

ngoi

Ngi lp trnh s dng c on

Phn on ph hp vi lp trnh theo

khi, cu trc d liu thay i, dng

chung v bo v b nh

54

4. B nh o dng phn on c phn trang

Kt hp cc u im ca phn on v

phn trang

T chc:

B nh o bao gm cc on

Trong mi on thc hin phn trang

55

V d: b nh o trn Pentium

n v qun l b nh

(Memory Management Unit, MMU)

n v phn on, (on n 232 bytes)

n v phn trang

Cc m hnh b nh

Khng phn on, khng phn trang

Khng phn on, c phn trang

C phn on, khng phn trang

C phn on, c phn trang

56

Chuyn i a ch

a ch o dng phn on:

Selector 16 bit

Offset 32 bit

a ch tuyn tnh (linear address)

a ch vt l

57

Cu trc selector

GDT (Global Descriptor Table): dng cho HDH

LDT (Local Descriptor Table): dng cho cc chng trnh

Privilege level: mc c quyn

58

Chuyn i a ch on a ch tuyn tnh

59

Chuyn i a ch tuyn tnh a ch vt l

60

ng dng mc c quyn

T CHC MY TNH V HP NG

Chng 5

TP LNH

2

Ni dung chng 5

I. Khi nim v tp lnh

II. Cc dng d liu

III. Tp lnh

IV. nh v a ch

V. Dng iu khin

VI. Gii thiu k thut lp trnh hp ng

3

I. Khi nim v tp lnh

1. Cc hnh thc ca tp lnh

2. Cc ch tiu thit k tp lnh

4

1. Cc hnh thc ca tp lnh

Tp lnh: tp hp cc lnh ca CPU

ngn ng my

C 2 hnh thc:

Dng nh phn

bit pattern

Dng k hiu

symbolic language

assembly language

5

2. Cc ch tiu thit k tp lnh

y

Hiu qu

D nh, d s dng

Tng thch

6

II. Cc dng d liu

1. Biu din s nguyn

2. Biu din s thc

3. S dng SIMD

4. Biu din k t

7

1. Biu din s nguyn

S nguyn khng du

Biu din nh phn

S nguyn c du

M b 2

S BCD (Binary-Coded Decimal)

S thp phn m ho nh phn

1 ch s thp phn biu din trn 4 bit

8

Khun dng s BCD

9

2. Biu din s thc

Dng tiu chun IEEE 754

X = S.2E

10

V d

11

3. S dng SIMD

S dng trn CPU IA-32

Nn cc d liu nguyn, s du chm

ng trong d liu 64 bit, 128 bit

Thc hin x l dng SIMD

Single Instruction stream

Multiple Data stream

12

V d d liu SIMD 64 bit

13

V d d liu SIMD 128 bit

14

4. Biu din k t

Dng cc bng m (coding schemes)

ASCII 7 bit, 8 bit, t 1967

American Standard Code for Information Interchange

Unicode 16 bit, t 1991

Dng dng sn (pre-compound)

Dng t hp (compound)

15

Khng gian m Unicode

16

III. Tp lnh

1. Cc loi lnh

2. Khun dng lnh

17

1. Cc loi lnh

Cc lnh a nng

Phi c trn cc tp lnh

Cc lnh c bit

c tnh ring ca tng CPU

18

Cc loi lnh a nng

Cc lnh di chuyn d liu

Thanh ghi, b nh, thit b I/O

Cc lnh x l d liu

Dng 1 ton hng: NOT, NEG, SHIFT,

Dng 2 ton hng: ADD, , AND,

iu khin chng trnh

Gi th tc

Lp, R nhnh

iu khin h thng

19

Cc loi lnh c bit trn IA-32

Cc lnh dng SIMD

MMX

Streaming SIMD Extensions (SSE)

SSE, SSE2, SSE3

Prescott New Instructions (PNI)

20

Cc loi lnh trn CPU Intel

21

Cc loi lnh trn CPU Intel (tt)

22

2. Khun dng lnh

Mi lnh c vng m lnh (opcode)

xc nh thao tc thc hin

Mi lnh c th c cc vng a ch

(address/reference)

xc nh ton hng ca lnh

23

V d

Khun dng lnh n gin

24

Nhc li chu k lnh

25

V d: Khun dng lnh CPU Pentium 4

26

IV. nh v a ch

1. Khi nim

2. Cc dng nh v a ch c s

27

1. Khi nim

Addressing nh v a ch

Xc nh ton hng ca lnh t cc vng

a ch trn lnh

Ton hng c th:

Hng s

D liu trn thanh ghi, b nh, thit b I/O

C cc dng nh v a ch phc tp

phc v yu cu phn mm

28

2. Cc dng nh v a ch c s

a. Tc thi (Immediate)

b. Trc tip (Direct)

c. Gin tip (Indirect)

d. Thanh ghi (Register)

e. Gin tip thanh ghi (Register Indirect)

f. Ch s (Indexed/Displacement)

g. Stack

29

a. nh v a ch tc thi

Ton hng trn lnh, trong vng a ch

Khng cn truy xut b nh ly ton

hng

Tc nhanh

Kch thc ton hng b gii hn

Operand Opcode

Instruction

30

b. nh v a ch trc tip

Vng a ch cha a ch ton hng

Cn truy xut b nh thm 1 ln c

ton hng

Khng cn tnh ton a ch ton hng

Khng gian a ch b gii hn

31

S nh v a ch trc tip

Address A Opcode

Instruction

Memory

Operand

32

c. nh v a ch gin tip

Vng a ch cha a ch nh lu a

ch ton hng

Cn truy xut thm b nh 2 ln:

Ln 1: c a ch ton hng (pointer)

Ln 2: c gi tr ton hng

C th gin tip nhiu cp

Tc chm

33

S nh v a ch gin tip

Address A Opcode

Instruction

Memory

Operand

Pointer to operand

34

d. nh v a ch thanh ghi

Vng a ch cha tn thanh ghi lu ton hng

Cn truy xut thanh ghi c ton hng

Vng a ch nh

Lnh ngn hn

Ly lnh nhanh hn

Tc nhanh

S lng thanh ghi gii hn

Tng t nh v a ch trc tip

35

S nh v a ch thanh ghi

Register Address R Opcode

Instruction

Registers

Operand

36

e. nh v a ch gin tip thanh ghi

Tng t nh v a ch gin tip

Vng a ch cha tn thanh ghi, gi tr

thanh ghi l a ch nh lu ton hng

Cn truy xut thanh ghi c a ch ton

hng v truy xut b nh c ton hng

37

S nh v a ch gin tip thanh ghi

Register Address R Opcode

Instruction

Memory

Operand Pointer to Operand

Registers

38

f. nh v a ch ch s

Vng a ch cha 2 gi tr:

Hng s D

Thanh ghi R

a ch ton hng l (R) + D

Dng truy xut vng nh lin tc

dng (Base + Displacement)

39

S nh v a ch ch s

Register R Opcode

Instruction

Memory

Operand Pointer to Operand

Registers

Address A

+

40

Cc dng tng t, m rng

ca nh v a ch ch s

Base-register addressing

a ch ton hng: (B) + D

B: base-register

Base-Index addressing

a ch ton hng: (B + I) + D

B: base-register

I: index-register

41

f. nh v a ch trn stack

Ton hng c hiu ngm ti v tr nh

stack

C hai loi lnh truy xut nh stack:

PUSH a d liu vo nh stack

POP ly d liu t nh stack

42

V d stack

nh stack: Stack Pointer (SP)

SP SP

SP SP

SP

SP

43

V. Dng iu khin

1. Khi nim dng iu khin

2. Cc loi dng iu khin c bn

44

1. Khi nim dng iu khin

Dng iu khin: th t thc hin cc lnh trong chng trnh

Th t vt l: th t cc lnh trn b nh

n gin, dng iu khin trng vi th t vt l

Cc dng iu khin khc th t vt l:

R nhnh

Gi th tc

By

Ngt qung

45

2. Cc loi dng iu khin c bn

a. Tun t

b. R nhnh

c. Th tc

d. By

e. Ngt qung

46

a. Tun t

Dng iu khin tun t trng vi th t

vt l

Lnh tip theo nh tip theo

47

b. R nhnh

Khi c lnh r nhnh (branch), dng iu

khin khc vi th t vt l

Hai dng r nhnh:

C iu kin, v d: dng If-Else, vng lp

Khng iu kin, v d: goto

48

c. Th tc

Th tc (procedure): k thut quan trng

nht ca lp trnh cu trc

Khi c lnh gi th tc (lnh CALL)

dng iu khin chuyn n th tc

Khi kt thc th tc, dng iu khin tr

v lnh tip theo lnh gi th tc

Nu coi lnh gi th tc v th tc l mt lnh th dng iu khin l tun t

49

M hnh gi th tc

50

Cc giai on gi th tc

C mt vng trn stack (stack frame) c to khi gi th tc

Cc giai on thc hin khi gi th tc:

Truyn tham s

Lu a ch tr v

Cp pht b nh cho cc bin a phng

Khi kt thc th tc:

Xo stack frame

Tr v lnh tip theo lnh gi

51

Mt s tnh cht

Cc th tc c th gi lng nhau

C th c nhiu stack frame ng thi

C th c li trn stack (stack overflow)

Do c qu nhiu stack frame

Do bin a phng, tham s qu ln

52

V d stack frame

53

d. By

By l lnh gi th tc t ng do

chng trnh ang thc hin to ra v cc

iu kin xc nh, thng l bo li

V d: by do chia cho 0

Khi c lnh chia cho 0:

Chng trnh ang thc hin dng li

Dng iu khin chuyn n chng trnh

x l by (trap handler)

Thng bo li divide by zero

54

By (tt)

By do phn cng pht hin, h iu hnh x l

Mt s iu kin dng to by:

Chia cho 0

Trn stack

Trn s nguyn, trn s thc

M lnh khng xc nh

Vi phm c ch bo v

55

e. Ngt qung

Ngt qung lm thay i dng iu khin

khng phi do chng trnh ang thc

hin to ra, m do mt nguyn nhn khc

thng lin quan n xut nhp

Chng trnh x l ngt qung:

Trn ROM BIOS

Thuc h iu hnh

Thuc chng trnh ng dng

56

V d: ngt qung bn phm

Khi c phm n:

Chng trnh ang thc hin dng li

Dng iu khin chuyn n chng trnh

x l ngt qung bn phm

Kt thc chng trnh x l ngt qung,

dng iu khin tr v lnh tip theo

57

Chuyn iu khin khi c ngt qung

58

Chu k lnh vi ngt qung

T CHC MY TNH V HP NG

Chng 6

MT S DNG

KIN TRC MY TNH

2

Ni dung chng 6

I. Kin trc my tnh song song

II. SMP (Symmetric MultiProcessor)

3

I. Kin trc my tnh song song

1. Khi nim

2. Cc m hnh kin trc song song

3. Gii thut song song

4

1. Khi nim

Kin trc my tnh tun t (kin trc

Von-Neumann) tin n gii hn tc

Cn cc kin trc song song

SISD, SIMD, MISD, MIMD

CPU Intel:

SIMD

Pipelining vi branch prediction

5

My tnh dng SIMD v MIMD

SIMD

Vector computer

MIMD kin trc song song

MultiProcessor Parallel Computer

Multicomputer Distributed system

6

Phn loi kin trc my tnh song song

7

2. Cc m hnh kin trc song song

Cc thnh phn:

Cc b x l

Cc b nh

Cc thit b I/O

H thng kt ni

8

Cc cp kin trc my tnh song song

(a) On-chip parallelism (b) Coprocessor (c) Multiprocessor

(d) Multicomputer (e) Grid

9

V d: siu phn lung trn Pentium 4

10

NUMA multiprocessor

My tnh NUMA da trn hai cp bus

11

V d: Multiprocessor

a. Multiprocessor vi 16 CPU dng chung 1 b nh

b. Mt hnh nh c chia thnh 16 phn cho 16 CPU x l

12

V d: Multicomputer

a. Multicomputer vi 16 CPU, mi CPU c b nh ring

b. Mt hnh nh c chia thnh 16 phn trn 16 b nh

13

Kin trc Cluster

14

Cc s kt ni tnh

II

15

Kt ni ng dng switches

16

B nh dng chung (shared memory)

17

B nh dng chung (tt)

18

Distributed system

19

3. Gii thut song song

c thit k qua 4 giai on:

Phn chia

Truyn thng

Tch t

nh x

20

II. SMP

1. c im

2. V d

3. Hot ng

21

1. c im

Tng hiu sut my vi tnh dng CPU

Intel

Tng thch vi my AT

Hot ng nh my 1 CPU vi h iu hnh

1 CPU

Dng cho cc CPU Intel t 80486

CPU c h tr multiprocessor

Cc CPU hon ton tng ng

Cu hnh mc nh: 2 CPU, ti a 16 CPU

22

c im (tt)

Cc CPU dng chung b nh:

Cc CPU dng chung mt khng gian a

ch

Ch c 1 bn h iu hnh trn b nh

Chng trnh c th thc hin trn mi CPU

Cc CPU dng chung h thng I/O

Hot ng vi cc tiu chun bus ISA, PCI

23

2. V d

24

V d (tt)

BSP Bootstrap Processor

AP Application Processor

APIC Advanced

Programmable Interrupt Controller

ICC Interrupt Controller Communication

25

BSP v AP

BIOS chn 1 CPU (BSP) khi ng h

iu hnh

Cc CPU cn li l AP, b treo khi khi

ng

AP ch hot ng khi h iu hnh

hot ng

BSP hot ng nh AP

26

3. Hot ng

27

MP BIOS

Kim tra cc thnh phn h thng

To cc configuration tables dng cho h

iu hnh

Khi ng cc processor

Cung cp cc dch v khi thc thi

28

Lp trnh trn kin trc SMP

Dng shared everything

Dng thread

Cn cc th vin h tr cc bin mutex,

semaphore

Loi tr tng h

ng b cc thread

29

V d