Construction of a Low-Noise Amplifier Chain With ...714179/FULLTEXT01.pdf · Title: Construction of...

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Construction of a Low-NoiseAmplifier Chain With

Programmable Gain and Offset

Master Thesis Performed in ISYby Jonas Tallhage

Author: Jonas Tallhage

Report Number: LiTH-ISY-EX--13/4700--SE

Linköping, 13th August 2013

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Title:

Construction of a Low-NoiseAmplifier Chain With

Programmable Gain and Offset

Master Thesis in ISYby

Jonas Tallhage

Report Number: LiTH-ISY-EX--13/4700--SE

Supervisor: Prakash Harikumar

Examiner: J Jacob Wikner

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Presentation Date: 2013-09-11

Publishing Date (Electronic Version): 2014-04-25

Department and Division: Department of Electrical Engineering, ISY

Language: English

Number of Pages: 126

Type of Publication: Degree Thesis

ISRN: LiTH-ISY-EX--13/4700--SE

URL, Electronic Version: http://www.ep.liu.se

Publication Title: Construction of a Low-Noise Amplier Chain With Program-mable Gain and Oset

Author: Jonas Tallhage

Abstract: A low-noise, variable gain amplier chain was constructed for interfa-cing a sensor to an ADC. During the course of the work two dierent methods -switched-capacitor circuits and chopping circuits - for dealing with 1/f noise wereinvestigated during the course of the work. The resulting circuit did not quitemeet the performance required by the specication, some possible improvementsare suggested.

Keywords: VGA, ADC, low-noise amplier, sensor, switched-capacitor, chop-ping amplier

http://www.ep.liu.se

Jonas Tallhage Master's Thesis Report

Contents

1 Introduction 81.1 The Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.2 System Specications, Requirements and Desiderata . . . . . . . . . 91.3 Signal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.4 The Zooming ADC Concept . . . . . . . . . . . . . . . . . . . . . . 111.5 Allowable Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 General Design Theory 132.1 Transistor Characteristics . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.1 gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1.2 gm-Id and V* . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 Switching Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.2.1 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.2.2 Analog MUXes and DEMUXes . . . . . . . . . . . . . . . . 182.2.3 Bypasses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.2.4 Passive Mixers . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3 Programmable Components . . . . . . . . . . . . . . . . . . . . . . 202.3.1 Programmable Resistors . . . . . . . . . . . . . . . . . . . . 202.3.2 Programmable Capacitors . . . . . . . . . . . . . . . . . . . 212.3.3 Programmable Current Sources and Sinks . . . . . . . . . . 22

2.4 Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.4.1 Binary-to-Thermometer Decoding . . . . . . . . . . . . . . . 23

2.5 Enable Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.6 Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.6.1 Sallen-Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.6.2 Multiple Feedback (MFB) . . . . . . . . . . . . . . . . . . . 282.6.3 Gm-C Filters . . . . . . . . . . . . . . . . . . . . . . . . . . 282.6.4 Switched-Capacitor Filters . . . . . . . . . . . . . . . . . . . 31

3 Design of Operational Ampliers 313.1 Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.2 Swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.3 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.3.1 Noise Power Spectral Density Functions and Total Noise . . 333.3.2 Summing of Noise Sources . . . . . . . . . . . . . . . . . . . 343.3.3 Noise In Cascaded Amplier Structures . . . . . . . . . . . . 353.3.4 MOSFET Noise . . . . . . . . . . . . . . . . . . . . . . . . . 363.3.5 Choice of Architecture . . . . . . . . . . . . . . . . . . . . . 393.3.6 Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 403.3.7 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.4 Closed-Loop Techniques For Reducing Low-Frequency Noise . . . . 41

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3.4.1 Correlated Double Sampling (CDS) . . . . . . . . . . . . . . 423.4.2 Correlated Double Sampling and Noise Spectrum . . . . . . 453.4.3 Chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493.4.4 Digital Techniques . . . . . . . . . . . . . . . . . . . . . . . 513.4.5 Op-Amp Design Considerations When Correlated Double

Sampling or Chopping is Used . . . . . . . . . . . . . . . . . 533.5 Driving a Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.5.1 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . 543.5.2 Capacitive Loads (Slew Rate) . . . . . . . . . . . . . . . . . 55

3.6 Stability, Settling Time and Compensation . . . . . . . . . . . . . . 573.6.1 Selecting a Suitable Phase Margin . . . . . . . . . . . . . . . 573.6.2 Basic Stability Behaviour of Op-Amps . . . . . . . . . . . . 583.6.3 Compensation of Two-Stage Op-Amps . . . . . . . . . . . . 59

3.7 Common-Mode Feedback (CMFB) . . . . . . . . . . . . . . . . . . 633.7.1 Error Amplier . . . . . . . . . . . . . . . . . . . . . . . . . 643.7.2 Resistive Sensing . . . . . . . . . . . . . . . . . . . . . . . . 663.7.3 Buered Resistive Sensing . . . . . . . . . . . . . . . . . . . 673.7.4 Transistor Sensing . . . . . . . . . . . . . . . . . . . . . . . 673.7.5 Switched-Capacitor CMFB . . . . . . . . . . . . . . . . . . . 68

3.8 Design Heuristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703.8.1 Choice of Architecture . . . . . . . . . . . . . . . . . . . . . 703.8.2 Creating a Schematic and Performing Initial Sizing . . . . . 723.8.3 Folded-Cascode Op-Amps . . . . . . . . . . . . . . . . . . . 743.8.4 Folded-Cascode Op-Amps With Class-AB Outputs . . . . . 783.8.5 GA-GA Op-Amps . . . . . . . . . . . . . . . . . . . . . . . . 80

3.9 Design of Instrumentation Ampliers . . . . . . . . . . . . . . . . . 83

4 Design Details 884.1 Initial System Planning . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.1.1 Gain Partitioning . . . . . . . . . . . . . . . . . . . . . . . . 884.1.2 Oset and Low-Frequency Noise Removal . . . . . . . . . . 884.1.3 Anti-Aliasing and Limiting the Noise Bandwidth . . . . . . 89

4.2 Stage Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 894.2.1 First Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894.2.2 Second Stage . . . . . . . . . . . . . . . . . . . . . . . . . . 904.2.3 Third Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.3 Bypasses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904.4 Input MUXing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5 Results 935.1 Overall Circuit Performance . . . . . . . . . . . . . . . . . . . . . . 935.2 Op-Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.2.1 Open-Loop Measurements . . . . . . . . . . . . . . . . . . . 97

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5.2.2 Closed-Loop Measurements With Mismatch and Process Vari-ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.3 Instrumentation Amp . . . . . . . . . . . . . . . . . . . . . . . . . . 1035.3.1 Open-Loop Measurements . . . . . . . . . . . . . . . . . . . 1035.3.2 Closed-Loop Measurements With Mismatch and Process Vari-

ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035.4 Programmable Current Source . . . . . . . . . . . . . . . . . . . . . 108

6 Discussion 1116.1 Thoughts on Workow . . . . . . . . . . . . . . . . . . . . . . . . . 111

7 Future Work 1127.1 Remaining Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

7.1.1 Noise Performance . . . . . . . . . . . . . . . . . . . . . . . 1127.1.2 Oset Current Source Robustness . . . . . . . . . . . . . . . 1137.1.3 Lack of Proper Testing . . . . . . . . . . . . . . . . . . . . . 1137.1.4 Compensation For MUX Switch Resistances . . . . . . . . . 1137.1.5 CMFB Reference Voltage . . . . . . . . . . . . . . . . . . . 1147.1.6 Segment Values in the Programmable Passive Components . 1147.1.7 Power Supply Disturbances . . . . . . . . . . . . . . . . . . 115

7.2 Potential Improvements . . . . . . . . . . . . . . . . . . . . . . . . 1167.2.1 Elimination of MUXes . . . . . . . . . . . . . . . . . . . . . 1167.2.2 Improving the Gain Precision of Stage One . . . . . . . . . . 1167.2.3 Usage of Chopping For Low-Frequency Noise Removal . . . 1167.2.4 Optimisation of Op-Amps . . . . . . . . . . . . . . . . . . . 117

Appendices 118

A Derivations of Wheatstone Bridge Equations 118

B Noise-Reduction in the Digital Domain 119

C Performing Measurements in Cadence 120C.1 Noise In Switched-Capacitor Circuits . . . . . . . . . . . . . . . . . 121

C.1.1 Setting Up a PSS Simulation . . . . . . . . . . . . . . . . . 121C.1.2 Open-Loop Noise . . . . . . . . . . . . . . . . . . . . . . . . 122C.1.3 Closed-Loop Noise . . . . . . . . . . . . . . . . . . . . . . . 122

C.2 Operating Point Information . . . . . . . . . . . . . . . . . . . . . . 122C.2.1 Saving Operating Point Information During a DC Sweep . . 123C.2.2 Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123C.2.3 gm/Id and V* . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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D Code 124D.1 Sage-Code to Calculate Proper Resistance-Segment Sizings For Pro-

grammable Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . 124

List of Figures

1 Usage illustration of the system to be designed. . . . . . . . . . . . 82 Using a Wheatstone bridge to measure the resistance of a resistor

Rx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Illustration of using the signal-conditioning circuitry to zoom into

a particular area of the input range. . . . . . . . . . . . . . . . . . . 124 Finding a value of V ∗ that is optimal in terms of its tradeo between

gm/Id and ft. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 A typical CMOS implementation of a switch. . . . . . . . . . . . . . 176 Principle of analog MUXes and DEMUXes. . . . . . . . . . . . . . . 187 Bypass mechanism using a DEMUX together with a MUX. . . . . . 188 Schematic of a passive mixer. . . . . . . . . . . . . . . . . . . . . . 199 Implementation of an N -segment programmable resistor. . . . . . . 2010 A programmable, N -segment capacitor. . . . . . . . . . . . . . . . . 2111 A 3-bit programmable, binary-weighted current source. . . . . . . . 2212 A current-mirror with an enable-control transistors added. . . . . . 2513 A generalised Sallen-Key lter, adapted from a gure in [13, p. 162].

To obtain a low-pass lter Z1 and Z2 should be resistive while Ziand Zii should be capacitive, Ra and Rb are used to set the ampliergain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

14 Single-ended and fully dierential implementations of Sallen-Keylters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

15 A generalised fully dierential MFB lter, to obtain a low-passstructure Z1, Z2 and Z3 should be resistive while Zi and Zii shouldbe capacitive. Adapted from a gure in [3, p. 5] . . . . . . . . . . . 28

16 A single-ended, rst-order Gm-C lter (adapted from [5]) . . . . . . 2917 A fully dierential, rst-order Gm-C lter (adapted from [9]). . . . 3018 Using two parallel input pairs to extend the input range. . . . . . . 3219 Summing of noise sources. . . . . . . . . . . . . . . . . . . . . . . . 3420 Summing ofK noise sources aected by transfer functions, the noise

signals Nn represent generalised signals that may be either voltagesor currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

21 Schematic model of a MOSFET with 1/f noise (adapted from agure in [9, p. 199]). . . . . . . . . . . . . . . . . . . . . . . . . . . 36

22 Model of the channel noise current due to a CMOS device. . . . . . 3723 Model of the input-referred channel noise due to a CMOS device. . 37

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24 A CS stage with a current-source load, for such a stage the channelnoise due to the load is input-referred by dividing its noise currentwith the gm of the amplifying transistor. . . . . . . . . . . . . . . . 38

25 The right half of a folded-cascode op-amp. . . . . . . . . . . . . . . 3926 Illustration of output oset cancellation (adapted from a gure in

[1, lecture 22]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4227 Resettable switched-capacitor gain circuit with input oset cancel-

lation [9, p. 429]. The version shown here is the single-ended onepresented in the reference, a fully dierential circuit may be ob-tained by substituting the op-amp for a fully dierential one andmirroring the passive network across the amplier. . . . . . . . . . 43

28 Typical output signal from the switched-capacitor amplier presen-ted in Figure 27 when used with a gain of 1. In the sampling phasethe output goes to the oset voltage which is 0.2V for the systemillustrated in the gure. . . . . . . . . . . . . . . . . . . . . . . . . 45

29 Improved resettable switched-capacitor gain circuit with input o-set cancellation [9, p. 431]. The version shown here is the single-ended one presented in the reference, a fully dierential circuit maybe obtained by substituting the op-amp for a fully dierential oneand mirroring the passive network across the amplier. . . . . . . 46

30 Typical output signal from the improved switched-capacitor amp-lier presented in Figure 29 when used with a gain of 1. . . . . . . . 47

31 Illustration of the eects of CDS on the noise performance of asystem. Hn is the noise transfer function as expressed in (24) (forfs = 1kHz) and Vn is an imagined noise vs. frequency function usedfor illustrative purposes. The y-axis has been left unlabeled due tothe diering units used there. . . . . . . . . . . . . . . . . . . . . . 48

32 Block-level illustration of a basic chopping amplier. . . . . . . . . 4933 Eect of chopping on low-frequency noise. . . . . . . . . . . . . . . 5034 Block-level illustration of a chopper-stabilised amplier with feed-

back being used to control the gain, adapted from a gure in [15].The parts within the dotted lines show the amplier itself while theparts outside of this shows the feedback path. . . . . . . . . . . . . 51

35 A possible implementation of the amplier shown in Figure 34,adapted from a gure in [7, p. 367]. The feedback circuitry is notshown in this gure, hence what is illustrated here corresponds tothe parts within the dotted lines in Figure 34. . . . . . . . . . . . . 52

36 A CS stage driving a resistive load. . . . . . . . . . . . . . . . . . . 5437 A voltage-follower driving a capacitive load. . . . . . . . . . . . . . 5538 Using an extra capacitor in parallel with the load to to limit the

bandwidth of a transconductor, adapted from a gure in [7, p. 166]. 60

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39 Using a Miller-capacitor in parallel with the output stage transcon-ductor to limit the bandwidth of the input stage, adapted from agure in [7, p. 170]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

40 Typical error amplier used in a CMFB network. The PMOS-inputversion shown here should be used if the return point transistorsare of the NMOS type, if these are instead of the PMOS type theNMOS-input equivalent should be used instead. . . . . . . . . . . . 65

41 Resistive CMFB sensing. . . . . . . . . . . . . . . . . . . . . . . . . 6642 Buered resistive CMFB sensing (gure adapted from one found in

[9, p. 290]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6743 Transistor CMFB sensing (gure adapted from one found in [9, p.

288]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6844 Switched-capacitor CMFB sensing (gure adapted from one found

in [9, p. 291]). The version shown here should be used if theCMFB return point is implemented by an NMOS transistor, if aPMOS transistor is used the circuit would need to be adapted toreect this. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

45 Schematic of a typical folded-cascode op-amp with PMOS inputtransistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

46 Addition of an extra stage and biasing circuitry to provide a folded-cascode op-amp with a class-AB output. . . . . . . . . . . . . . . . 79

47 Schematic of a typical GA-GA op-amp. The CMFB error voltageshould be connected either to verror,s1 or to verror,s2. In the formercase the output stage load transistors should be constant-currentsources and verror,s2 should thus be tied to Vbias. In the latter casethe inner CMFB loop shown in Figure 48 should be used. . . . . . . 80

48 Inner CMFB loop used to control the CM level of the input stageif the main CMFB network error voltage is fed to the output stages. 82

49 A common instrumentation amplier structure (adapted from a g-ure in [7, p. 320]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

50 Principle of feedback-controlled ampliers. . . . . . . . . . . . . . . 8451 A dierent implementation of the block diagram in Figure 50a. . . . 8552 A possible transistor-level implementation of the structure shown

in Figure 51, based on a GA-GA op-amp. . . . . . . . . . . . . . . . 8653 Source-degenerated gm-cell. . . . . . . . . . . . . . . . . . . . . . . 8754 Overview of the system as originally conceived. . . . . . . . . . . . 8855 Overall system with input MUXing being used only for the ADC.

Compare to the originally conceived system shown in Figure 54where only a single, MUXed amplier chain is being used. . . . . . 91

56 System disturbance gains plotted versus frequency for Av,tot = 1000.The worst cases has been choosen among 98 Monte Carlo runs (100Monte Carlo runs with outliers removed). . . . . . . . . . . . . . . . 96

57 Bode plots for the open-loop op-amp. . . . . . . . . . . . . . . . . . 98

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58 Bode plots for the op-amp congured in a closed loop with a gainof 1, the curves here illustrate the loop gain and phase (obtained bybreaking the loop using the iprobe component from analogLib) underthe given feedback conditions rather than the closed-loop behaviourunder the same conditions. . . . . . . . . . . . . . . . . . . . . . . . 99

59 Bode plots for the op-amp congured in a closed loop with a gain of10, the curves here illustrate the loop gain and phase (obtained bybreaking the loop using the iprobe component from analogLib) underthe given feedback conditions rather than the closed-loop behaviourunder the same conditions. . . . . . . . . . . . . . . . . . . . . . . . 100

60 Op-amp disturbance gains plotted versus frequency for Av,cl = 10. . 10261 Bode plots for the open-loop instrumentation amplier. . . . . . . . 10462 Bode plots for the instrumentation amplier congured in a closed

loop with a gain of 1, the curves here illustrate the loop gain andphase (obtained by breaking the loop using the iprobe componentfrom analogLib) under the given feedback conditions closed-loop be-haviour under the same conditions. . . . . . . . . . . . . . . . . . . 106

63 Bode plots for the instrumentation amplier congured in a closedloop with a gain of 10, the curves here illustrate the loop gain andphase (obtained by breaking the loop using the iprobe componentfrom analogLib) under the given feedback conditions rather than theclosed-loop behaviour under the same conditions. . . . . . . . . . . 107

64 Instrumentation amplier disturbance gains plotted versus frequencyfor Av,cl = 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

65 Output from the programmable current source when sweeping theinput value from 0 to 31. . . . . . . . . . . . . . . . . . . . . . . . . 110

66 CMFB gain and single-ended power-supply disturbance gain. . . . . 11567 Using a Wheatstone bridge to measure the resistance of a resistor

Rx, this schematic was shown previously in Figure 2 but is repro-duced here for convenience. . . . . . . . . . . . . . . . . . . . . . . 118

68 Block diagram of an averaging function that produces one outputsample for every 4 input samples. . . . . . . . . . . . . . . . . . . . 120

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1 Introduction

This thesis has been carried out at IMST GmbH, Germany as part of a MastersProgramme taken at Linköping University, Sweden. The thesis has primarilyconcerned the design of analog integrated circuits but has also involved somemixed-signal design and additionally some digital design in order to design suitablecontrol logic for the main circuit.

The thesis work has been carried out as part of a research-oriented projectthat aims to construct cheap, small and power-ecient sensor units for use inindustrial applications. Each such sensor would - in addition to the sensor itself- need to provide an ADC with associated signal-conditioning circuitry as well asradio circuitry for wirelessly communicating the measurement results.

1.1 The Task

vsig,0 vsig,1 vsig,2 S

vin,0

voutvin,1

vin,2

Gain Control

Offset Control

ADCAmplifier

Chain

Figure 1: Usage illustration of the system to be designed.

The task in this thesis has concerned the analog signal-conditioning circuitry asso-ciated with the ADC. The input signals are to be provided by sensors. A conceptof zooming is to be employed in the ADC, in which the signal-conditioning cir-cuitry takes an active part in the conversion process and must provide variablegain and oset to allow the converter to be zoomed to a particular area of theinput range. This was inspired by a previously existing design - described in [4] -that was also used as a reference point during the design work to provide a roughguide to what kind of performance might potentially be achievable.

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1.2 System Specications, Requirements and Desiderata

Parameter Symbol Min Typ Max Unit Notes

ProgrammableGain

Av 1 1000 V/V

Programmableoset

Voff −x 0 y V

Number ofinputs

3 3 3

MUXing of Ninputs

1 3

Resolution 12 16 Bits

Currentconsumption

1 mA

Bridge factor B 1 2

Strain guagesensitivity

k 2

Strain ε 0 0.02

Nominal bridgeresistor value

Ri 0.999 1 1.001 kΩ

Signal strength vin 0 60 mV

Allowable noise vn 0 14.6 µV

Bridge resistortolerance

Rtol 0.1 %

Analog powersupply

VDD,A 3 3.3 3.6 V

Digital powersupply

VDD,D 1 1.2 1.4 V

Analog supplyline disturbances

Vn,V DD −500 0 500 mV

Enable function Required

Table 1: System specications, requirements and desiderata.

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The basic requirements of the system were programmable gain ranging from 1 to1000 and programmable oset to enable compensation of any oset in the signalsource. A nal resolution of 16 bits was desired from the complete system but dueto the research-oriented nature of the project it was not known from the outsetwhether achieving such a resolution was feasible and hence this resolution wastreated as a target rather than a requirement.

The system was required to provide three inputs to allow for the outputs fromthree dierent sensors to be read simultaneously. In order to conserve chip areaand power a desideratum was that only a single amplication chain and ADC beused with a MUXing system included to allow all three sensors to be read in around-robin fashion.

1.3 Signal Sources

The usage scenarios describe a variety of signal sources, of these the most dicultone to deal with are the sensors. These thus provide a worst-case scenario againstwhich the circuit performance needs to be checked. The particular type of sensorsto be used are strain guages, this is a resistive type of sensor which changes itsresistance in response to mechanical strain. Such sensors can thus be used tomeasure the physical stress experienced by various structures.

vdf

R1 R2

R3 R4

VDD

Figure 2: Using a Wheatstone bridge to measure the resistance of a resistor Rx.

Strain guages can be manufactured with a variety of nominal resistances inthe unstrained state but no matter the nominal value the variations in resistanceexhibited when strained tend to be quite small, in order to measure such smallvariations this type of sensor is therefore generally used in a Wheatstone bridge[14]. Such a bridge is shown in Figure 2 where it is readily seen that if all resistancesare equal then the dierential voltage vdf will be 0, in such a state the bridge issaid to be balanced. If the bridge is unbalanced by allowing some of the resistorsto vary then the voltage at the output nodes will change, producing a dierential

10


output voltage that may be measured and used to calculate the strain put on thestrain guage. The signal strength depends on how many resistors are made tovary and can be expressed as

vdf =B

4· ∆R

R(1)

where B = 1 for a quarter-bridge (one resistor being allowed to vary), B = 2 fora half-bridge (two resistors being allowed to vary) and B = 4 for a quarter-bridge(all resistors being allowed to vary).

For a strain guage ∆R/R = kε. Using the values listed in Table 1 we cancalculate the maximum obtainable input signal which is obtained for the half-bridge case

|vin,max| =Bmax

4· k|εmax|Vdd =

2

4· 2 · | ± 0.02| · 3V = 60mV (2)

In the quarter bridge case vin,max = 30mV, i.e. we lose an SNR corresponding toone bit of resolution.

The maximum oset due to the bridge resistor tolerances can be calculated to

voffset,max = 0.01 ·Rtol · Vdd V = 3.3mV (3)

Using resistors with a nominal resistance of 1kΩ puts 500W of resistance in eachbranch, for a total dierential output resistance of 1kΩ.

A more detailed account of the calculations involved in obtaining the resultsabove can be found in Appendix A.

1.4 The Zooming ADC Concept

The basic idea behind the zooming ADC concept is to use the signal-conditioningcircuitry to zoom into a particular area of the input range. This is illustrated inFigure 3 where the signal at the input of the conditioning circuitry varies arounda xed oset that is large compared to the signal itself. Programmable oset andgain in the conditioning circuity is used to remove the signal oset and amplifyby an appropriate amount so that the converter always utilises its full range. Toensure that a good operating point is always obtained the system is planned toinclude a startup calibration routine that will zero (approximately, subject to thenite resolution of the oset cancellation mechanism) the oset each time thesystem is started.

1.5 Allowable Noise

To obtain a resolution of M bits the total noise voltage must not be allowed toexceed half an LSB step. In a dierential system the eective range is twice the

11


Foffset

VoffsetVsignal

Foffset

Vout

Fin

(a) Input to the conditioning circuitry, asmall signal varying around a xed oset.

Foffset

Vsignal

Fsignal

Vout

Fin

(b) Input to the converter, the oset has beenremoved and the signal amplied to providea full-scale input.

Figure 3: Illustration of using the signal-conditioning circuitry to zoom into a particulararea of the input range.

12


reference voltage, thus vn,max = Vref/2M . If we input-refer the noise and assume

that the maximum input signal should cause a full-scale input to the ADC weobtain

vn,max =60mV

212≈ 14.6µV (4)

Careful reading of the reference design datasheet [4] reveals that the rst amp-lication stage in this design has a best-case input-referred total noise of 20.5µV,1

even so 16 bits of resolution is claimed. As the datasheet also mentions averagingof samples as a way of increasing noise performance it appears likely that this isused to achieve the claimed resolution. Thus in case this specication cannot befullled one option would be to use averaging to lower the noise further. If foursamples are averaged the noise is reduced by half (n.b.: this assumes that thenoise in the samples is uncorrelated and is thus not valid for low-frequency noise),leading to a relaxed noise specication of

vn,max ≈ 29.3µV. (5)

However, while averaging is simple it probably should not be used as one canlikely obtain a larger improvement from using four input samples to produce oneoutput sample. A more detailed discussion about such matters may be found inAppendix B.

2 General Design Theory

2.1 Transistor Characteristics

2.1.1 gm

The gm of a transistor is formally dened as the rate at which its drain currentchanges for a change in its gate-source voltage. I.e. it is the voltage-to-currentgain of the transistor and is therefore sometimes referred to as its transconduct-ance gain or simply transconductance. The transconductance is dependent on theoperating point of the transistor and in some situations one may therefore ndgraphs depicting the gm as a function of some other parameter useful. In moremathemetical terms we may use the following denition taken from [12, p. 21]:

gm :=∂Id∂Vgs

∣∣∣∣Vds constant

(6)

1In the specications found on p. 6 of the datasheet 205µV of output noise is claimed forthe rst stage, note 4 states that this gure is independent of gain and sampling frequency.The best-case input-referred noise occurs for the maximum stage gain of 10 (also found in thespecication table).

13


In [12, p. 21] three possible expressions which can be derived2 from this den-ition are stated:

gm = µnCoxW

LVov (7a)

gm =

√2µnCox

W

LId (7b)

gm =2IdVov

(7c)

Here Vov = Vgs − Vt is the overdrive voltage of the transistor (in [12] the fullexpression rather than Vov is used). These three dierent ways of expressing gmare useful under dierent circumstances depending on which parameters are xedand which may be varied freely. (7a) is useful when Id is xed but Vgs (andtherefore Vov) and W/L may be varied. (7b) can be employed when Vgs is xedbut Id and W/L can be varied at will. Finally, (7c) nds its use when W/L isxed but Vov and Id can be can be set freely.

The equations presented in this section have all been derived using long-channeltheory (see [12] for the details of their derivation) and are hence only valid forlong-channel devices. In short-channel devices - which practically all transistorsencountered in a modern process are - there is a large range of second-order eectsthat will cause the actual behaviour of the devices to dier from what these equa-tions would predict. Nevertheless these equations are useful to provide insightinto the basic tradeos that must be made during the design procedure, whileit is most certainly possible to construct more accurate models for short-channeldevices such models tend to become very cumbersome and would thus be unlikelyto oer much in the way of such insight (see for example [1, lecture 3] for somediscussion about this).

2.1.2 gm/Id and V*

Descriptions of the gm/Id concept can be found in many places in the literature,for example [1, lecture 4]. The underlying idea behind this gure-of-merit is thatdividing the gm of a transconductor by its bias current provides us with someinsight into how energy-ecient the transconductor is since the resulting guretells us how much transconductance is obtained per unit of bias current spent.Since many of the amplier characteristics that we are ultimately interested in(e.g. gain and bandwidth) depend on gm this translates into better insight in howmuch of these performance gures is gained per unit of bias current.

2(7a) follows directly from the denition presented in (6) by substituting Id =12µnCox

WL V

2ov =

12µnCox

WL (Vgs − Vt)2 and calculating the derivative. (7b) follows by recognising that (7a) im-

plies g2m =(µnCox

WL

)2V 2ov =

(2µnCox

WL

) (12µnCox

WL

)V 2ov = 2µnCox

WL Id. (7c) follows by

recognising that (7a) implies gm = 2Vov· 12µnCox

WL V

2ov =

2Vov· Id

14


V ∗ is a related concept that has been introduced in [1, lecture 4], most of thediscussion presented here follows the discussion available in this source. V ∗ isdened as

V ∗ :=2Idgm

(8)

and is thus closely related to Vov. Equation (7c) may be rearranged to obtain

Vov =2Idgm

, (9)

from this we may be led to believe that V ∗ and Vov are one and the same concept.However - as was pointed out in Section 2.1.1 - the relationship expressed in (9) isonly valid in the long-channel case, the relationship expressed in (8) on the otherhand is true by denition and therefore always holds. Thus for the long-channelcase V ∗ = Vov but as channel lengths grow shorter the two concepts diverge.

Still, it is not by chance that the two concepts are so similar. Due to theircloseness V ∗ preserves the intuitions that one may have regarding Vov since any-thing that causes Vov to increase will also cause V ∗ to increase and vice versa.In contrast, gm/Id - while useful as a gure-of-merit - may be hard to use insuch an intuitive manner because it does not correspond so closely to any concepttraditionally used when basic long-channel principles are taught.

It is interesting to note that V ∗ is in fact more well-dened than Vov. Bydenition Vov := Vgs − Vt which may at rst glance seem precise enough, howeverVt is dened in terms of a knee in the Id-Vgs curve of the device and the preciselocation of this knee is somewhat arbitrary (in addition there is no single Id-Vgscurve but rather a family of curves for dierent Vds values). This is especiallytrue for short-channel devices where the transition between the ohmic and thesaturation region of operation is much more gradual than for their long-channelcounterparts. [1]

One practical use of this concept is in providing a method for initial transistorsizing when designing op-amps. For any transistor it is possible to nd a V ∗ thatis optimal in the sense that it maximises ft · gm/Id. This composite gure ofmerit provides information about how a transistor trades o between bandwidtheciency as expressed by the transit frequency ft and power eciency as expressedby gm/Id. For any technology one can construct curves such as the one shownin Figure 4 and then refer to these when setting the V ∗ of a transistor (whenconstructing such curves it should be noted that they vary with transistor length,thus a family of curves for dierent lengths should be constructed). If such curvesare not available setting V ∗ to 200mV may be used as a rule-of-thumb. Moredetails on nding an optimal V ∗ can be found in [1] where some hints may alsobe found regarding how to use a simulator to obtain the curves.

gm/Id is available as simulator output in many simulators intended for ICdesign (see Section C.2.3 for information on how to access this output in Cadence).

15


0 0.5 1 1.50

10

20

30

40

50

60

70

V ∗ (V)

gm/Id (1/V)ft (GHz)ft · gm/Id (GHz/V)

Figure 4: Finding a value of V ∗ that is optimal in terms of its tradeo between gm/Idand ft.

(8) may be rewritten on the form

V ∗ :=2

gm/Id, (10)

hence in any simulator where gm/Id is available as a simulator output V ∗ is alsoeasy to access.

2.2 Switching Circuits

2.2.1 Switches

An ideal switch would exhibit innite resistance when o and zero resistance whenon, in addition it would have innitely fast turn-on and turn-o times and wouldcause no other artifacts such as the injection of charge into other parts of thecircuit at turn-o. Such a switch can obviously not be realised in practice oreven be used in simulation since simulators generally cannot work with innitequantities. Even an approximation of an ideal switch that uses very large or verysmall values in place of innite or zero ones can be problematic for a simulator.Suppose that a 1V DC source is connected to ground through a switch with anon-resistance of 1µW and an o-resistance of 1TW. This would cause the currentowing through the switch to change between 1MA in its on-state and 1pA itso-state, a dierence of 18 orders of magnitude. Such large dierences in current

16


size would force the simulator to use very long representations in order to conserveprecision, increasing the computational load and therefore increasing simulationtimes. Similarly using very small turn-on and turn-o times may force the simu-altor to reduce its minimum time-step, also prolonging simulation times. For thesereasons it is generally recommandable to make switches less ideal (unless a highlevel of ideality is actually needed) in order to reduce simulation times.

Mswitch,N

Mswitch,P

Mdummy,N1 Mdummy,N2

Mdummy,P1 Mdummy,P2

v1 v2

vcontrolvcontrol vcontrol

vcontrolvcontrol vcontrol

Figure 5: A typical CMOS implementation of a switch.

In a CMOS process switches may be implemented as shown in Figure 5 whereMswitch,N and Mswitch,P are the main devices implementing the switch. Whenthe switch is turned on charge carriers (electrons for N-devices and holes for P-devices) will be accumulated in the channels of the main switch transistors. Whenthe switch is turned o this charge will exit the channels through the source anddrain connections and will thus end up in other parts of the circuit, something thatcould potentially cause troubles since it may for example inject spurious charge tosome capacitors in a switched-capacitor circuit and thereby degrade the accuracyof the circuit. The dummy transistors are included for this reason, if properlysized they should absorb most if the charge from the main transistors into theirown channels when the switch turns o.

CMOS switches tend to have high o-resistances and thus generally providegood approximations of ideal swithes in their o-states, should the o-resistanceeven so be found to be too low it can be increased by increasing the channellength of the transistors. The resistances in the on-state on the other hand arefar from the ideal and can easily reach values in the kΩ-range. The on-resistancecan be decreased by increasing the transistor channel width, unfortunately doingso will also degrade the switch o-resistance. In addition, any increase in widthor length will increase the transistor area and therefore cause the switch to addmore parasitic capacitance and to inject more spurious charge at turn-o.

A further problem with the switch resistance in CMOS switches is that itis signal-dependent and thus varies depending on the terminal voltages. Thisproblem can be alleviated by proper sizing of the ratio between the P-devicewidths and the N-device widths.

17


2.2.2 Analog MUXes and DEMUXes

vin vout,1

vb0

vb0

vout,2

(a) Principle of a 2-output analogMUX.

vin,1

vb0

vb0vin,2

vout

(b) Principle of a 2-input analogDEMUX.

Figure 6: Principle of analog MUXes and DEMUXes.

The principle of simple analog MUXes and DEMUXes is illustrated in Figure6. When only two inputs/outputs are used the control is simple and no decodingof the digital control input needs to be done whereas if more inputs/outputs areused a control input decoded would need to be added. The switches shown in thegure can be implemented using e.g. the switches described in Section 2.2.1, inthis case an inverted version of the digital control input would need to be madeavailable.

2.2.3 Bypasses

S

vin

vout,1

vout,0

S

vin,0

vin,1

vout

H(s)

Vs

Rs

vout

RH Req

VBP

Figure 7: Bypass mechanism using a DEMUX together with a MUX.

A bypass circuit can be implemented using a 1:2 DEMUX at the input and a2:1 MUX at the output of each stage, as shown in Figure 7. As has been noted inSection 2.2.1 each of these will in practice be implemented by a transistor switchwith nite resistance, hence the bypassing circuitry will add some resistance. Aparticularly problematic aspect of this added resistance is that it may not beconstant, from the gure it should be clear that what resistance will be seen when

18


looking in from the output is dependent on whether the processing block H isbypassed or not.

A possible way to compensate for this is suggested in the gure and is done byadding extra resistive elements in between the rst processing block and the MUX,sized such that their total value equals that of one switch plus the source resistance.The next stage would then always see an extra resistace due to either one switchand the source resistance or to an added resistance that closely approximates thisvalue. Because one will in this case be attempting to match the resistance of otherelements the added resistance should in this case be realised in the same manneras the imitated resistance, i.e. the part that matches the switch resistance shouldbe implemented by an equally sized and biased transistor switch and the sourceresistance part should be matched by some element with similar characteristics (interms of such things as temperature constants and sensitivity to supply voltagevariations) to the elements that make up the source resistance.

If several stages with a bypass function are cascaded (as for example in thepresent design) and all of them need to exhibit a constant output resistance thenone may repeat the procedure described above, using the source (i.e. the combin-ation of Vs and Rs) to model the eects of the previous stage. Since the resistanceseen from the output terminal of the previous stage should now be constant sucha model should provide reasonable accuracy. The remarks previously made aboutthe way that the equalising resistance should be implemented applies here as well,hence for a two-section cascade the equalising resistance in the second stage maybe implemented by copying the equalising resistance used in the rst stage andadding one switch resistance implemented using a properly biased and sized tran-sistor switch.

2.2.4 Passive Mixers

vclk

vclk

vclk

vclk

voutvin

Figure 8: Schematic of a passive mixer.

A passive mixer periodically inverts the polarity of the signal and mey hence

19


be constructed as shown in Figure . As in the case of MUXes and DEMUXes theswitches can be implemented as described in Section 2.2.1, in that case an invertedversion of the clock signal must be made available.

2.3 Programmable Components

In systems employing ampliers where the gain is set using feedback loops in-volving ratios of passive components there may be a need of passive componentswith programmable values in order to achieve programmable gain. Such compon-ents can be realised using a system of programmable switches that are used toswitch passive elements in and out of the circuit or to bypass them. Since idealswitches cannot be implemented in practice the non-idealities of the switches mustthen be taken into consideration as they may aect the precision of the implemen-ted programmable component.

2.3.1 Programmable Resistors

v2

vc,1 vc,2 vc,N

R1 R2 RN

v1

R0

Figure 9: Implementation of an N -segment programmable resistor.

A programmable resistor can be implemented as shown in Figure 9 where theswitches can be used to bypass unwanted resistor segments. The resistor segmentsare sized such that the smallest desired resistance is obtained with all the switchesbeing on, the next smallest value with the switch controlled by vc,1 being o andso on. The switches should thus be controlled by a thermometer-coded value,generally making it necessary to include control logic that can perform binary-to-thermometer code conversion. A description of how such a decoder can beimplemented is found in Section 2.4.1.

Programmable resistors are unfortunately hard to implement with good pre-cision. This is partly due to the usage of resistors in and of itself since resistorgenerally cannot be sized very precisely in IC technologies. Another source ofinaccuracies is the switches, since any real switch will exhibit nite resistance theswitches will aect the total resistance obtained. Due to their high o-resistancetheir contribution will usually be minimal when a resistor is switched in but in theon-state when the switch is used to bypass a resistor segment it will contributea usually non-negligible resistance which should be compensated for in the sizingof all previous resistors. To make matters even worse the resistance of a resistor

20


segment may be low enough to have a non-negligible impact on the total resistanceobtained from a bypassed segment.

Taken together, these imperfections makes it non-trivial to calculate segmentresistance values that will yield the desired resistances between the terminals ofthe programmable resistor. It is possible to set up equation systems that may beused to calculate suitable values but these tend to be cumbersome and tedious tosolve, hence it probably preferable to use some CAS (Computer Algebra System)software such as Sage for performing this task. Sage code for a 3-segment casemay be found in Section D.1, this code should be fairly straightforward to adaptto other cases. While the solutions yielded using such a method provide a goodstarting point some iteration using the simulator may still be needed.

However, even if resistance values can be found that yield nal values for theprogrammable resistor which are close to the desired ones it is unlikely that theimplemented resistor will be very precise. The precision problems connected withresistances in IC processes will still be present as will the imprecision in the sizingand characteristics of transistors. The involvement of transistor resistances alsomakes matching problematic since there are now two dierent types of elementsetting the resistances. Furthermore the sizing procedure outlined above tends toproduce resistances which would be hard to realise using unit-elements. Henceone can never expect too much in the way of absolute or matching precision fromprogrammable resistors.

2.3.2 Programmable Capacitors

vc,1

C1

vc,2

C2

vc,N

CNC0

v1

v2

Figure 10: A programmable, N -segment capacitor.

The principle of implementing a programmable capacitor is illustrated in Fig-ure 10. As in the case of programmable resistances the switches will exhibit niteresistance but as long sucient time is available for charging the capacitors thiswill not aect the precision of the capacitor if it is to be matched to another ca-pacitance. The switches will however also contribute some capacitance which maybecome problematic, hence a tradeo exists between the precision and the min-imum time needed for charging since making the transistors wider will decreasethe time needed for charging but increase the amount of parasitic capacitancedue to the switches. Leakage current in the o-state may also be a problem and

21


introduces another tradeo since the leakage current grows smaller if the switchtransistors are made longer but doing so will also increase the amount of parasiticcapacitance added by the switches.

2.3.3 Programmable Current Sources and Sinks

(W/L)ref

Iref

½(W/L)ref 1(W/L)ref2(W/L)ref

½Iref 1Iref

vb0

vb0

Vbias

vb1

vb1

Vbias

vb2

vb2

Vbias

2Iref

Iout

Mc,0 Mc,1 Mc,2

Figure 11: A 3-bit programmable, binary-weighted current source.

A digitally programmable current source is shown in Figure 11. It is implemen-ted using a number of current mirrors with a common control-voltage-generatingdiode, sizing the outputs of the current mirrors in a binary-weighted fashion makesit simple to set the output current using a digital control word. In eect this meansthat a current-mode DAC has been produced. The source shown in the gure in-cludes cascodes Mc,i which additionally function as switches by having their gatesconnectible to either the cascode biasing voltage or to ground. It would also bepossible to use separate transistors for the switches but doing so would cause anadditional Vgs-drop which would decrease the permissible voltage range at theoutput.

While the number of transistors grow in a linear fashion as the number ofcontrol bits increase the size of each added transistor grows exponentially, asidefrom a rapidly increasing area as more control bits are used this also means thatthe spread in transistor sizing grows exponentially. For these reasons using a largeamount of control bits would be problematic as the area would grow prohibitivelylarge and because the element spread would quickly make it likely that the ADCis not monotonous.

In many cases a two-sided current sources including both a source and a sinkmay be desired. A corresponding current sink can be implemented by constructingthe structure shown in the gure using NMOS- rather than PMOS-transistors.Another possibility is to use current mirrors to copy the output current such thata source and a sink is obtained.

22


If a two-sided current source is used it may further be desirable to include asign-bit so that the polarity of the currents can be reversed. The passive mixerdescribed in Section 2.2.4 performs precisely this function and can thus be usedto control the output polarity by connecting it at the output and letting it becontrolled by the sign-bit.

2.4 Control Logic

While the system described in this report is mainly analog in nature some digitalcontrol logic has still been necessary to incorporate for such tasks as mapping thevarious gain settings to digital control signals that can control the various circuitelements and for dealing with enable signal in an intelligent fashion. For thesynthesis of reasonably simple logic it is often sucient to proceed by constructinga truth table which may then be used in an opportunistic fashion to synthesiselogic expressions that maps the input control bits to the functions needed in thecircuit. Based on experience it is often possible to quickly see which type ofexpressions will yield the desired output bits (in this case the control bits usedinternally in the circuit) based on the input bits.

As all of the logic used in the present system is fairly straightforward in naturethis type of method has been used throughout and formal methods have gen-erally not been employed with the exception of the construction of binary-to-thermometer decoders, the method used in that case is described in Section 2.4.1.

In the present case it has been possible to choose between constructing the logicdirectly in the 3.3V-domain or constructing it in the 1.2V-domain and using level-shifters to produce usable control signals. Aside from considerations regardingthe availability of pre-constructed logic gates and design time the main concerninuencing this type of decision is power consumption and speed. If 3.3V-logicis used each switching of the output would consume more power since the powerneeded to change the state at the output of a logic is Psw = 1

2CloadV

2dd [11]. On the

other hand the higher Vt of 3.3V transistor would make such transistors consumeless static leakage power, hence constructing the logic in the 3.3V-domain may bepreferable if the switching activity is deemed to be low. In addition, constructingit in the 3.3V-domain may be preferable if speed is critical since the transitiontime of a logic gate tends to decrease with increasing Vdd.

2.4.1 Binary-to-Thermometer Decoding

Binary-to-Thermometer decoding can be done in a recursive manner. Followinga description given in [2, pp. 114-116] we start by recognising that for a singlebit, binary and thermometer codings yield identical results. Performing binary-to-thermometer decoding of a single bit is therefore trivial and may be done bysimply copying the input bit.

23


If we have n input bits and have already done decoding such that we have athermometer coded representation of the lowest n−1 of these bits we may performbinary-to-thermometer decoding by recognising the following:

To represent a n-bit binary coded value in thermometer form we requiremn = 2n − 1 thermometer bits. As we would previously have had mn−1 =2n−1 − 1 thermometer bits the relationship between the previous and thenew number of thermometer bits is thus mn = 2mn−1 + 1.

The rst new position among the thermometer coded output bits is atmn−1+1. This bit will only be 1 if the value of theSince the value of the binarycoded input will only be aected by input bit n if this bit is 1 we can obtainbit

If the n:th binary input bit (i.e. the MSB) is 1 the binary encoded value isin the upper half of its range and thus all thermometer bits up to mn−1 + 1should be set to 1. If the binary input MSB is 0 then thermometer bitmn−1 + 1 should be set to zero and all lower thermometer bits should beset to the same value as the input thermometer bits. Thus thermometer bitmn−1 +1 may be obtained by simply copying bit n of the binary coded inputwhile the lower bits may be obtained as ti = bn + t′i where ti is bit i of thethermometer coded output, bn bit n of the binary coded input and t′i bit iof the thermometer encoding of the lower n− 1 input bits.

All higher bits in the output may be set to 1 only if the input is in theupper half of its range. Since adding an extra input bit doubles the rangeof possible values these bits may in this case be obtained by simply shiftingthe thermometer coded part of the input up by mn−1 + 1 positions. We cantherefore obtain the upper mn−1 bits of the output as ti+mn−1+1 = bn · t′i.

2.5 Enable Controls

Since many systems are on average only used for a small part of the time itis often possible to save quite a bit of average power consumption by includingenable controls. This is especially true for analog systems where the bulk of thepower consumption is usually due to biasing currents rather than charging anddischarging of capacitive loads as the output voltages at various points in thecircuit change.

The most basic way to disable an analog circuit when it is not to be used istherefore to turn of all bias currents. Since bias currents are generally set usingcurrent-mirrors this can be done by adding enable-control transistors to the biasingcurrent mirrors as illustrated in Figure 12. Here M1 is used as a simple switchto turn o the input current to the current mirror when the part that it biases isto be disabled, M2 ensures that all output transistors controlled by Mcontrol are

24


ven

Ibias

ven

Men,1

Men,2

Mdiode Mout

Iout

Figure 12: A current-mirror with an enable-control transistors added.

turned o by connecting their gates to ground. It ought to be noticed thatM1 willexhibit a Vgs-drop that will lower the available voltage at the input node. Thismay become problematic in cases where low supply voltages are used, if low-Vttransistors are available using such a transistor for M1 may help alleviate anyproblems due to this.

When op-amps are to be disabled there may be parts which are not necessarilyfully disabled even if all bias currents are turned o. For example turning o thebias currents may leave the gates of the transistors comprising a class-AB outputoating or even at some well dened voltage that still allows them to conduct anappreciable amount of current. Hence one should make sure to monitor the currentconsumption in the disable state of an op-amp and make sure that no situationssuch as the one just described occur. In some cases additional transistors may needto be added to connect the gates of certain transistors to Vdd or Vss in the disablestate so as to ensure that they are fully turned o. In some cases it may alsobe desirable to put the outputs into some well dened state by adding transistorsthat connect the output to e.g. Vss when the op-amp is disabled. In other casesit may make more to put the output in a high-Z state so as to make sure thatits eect on other parts of the circuit to which it is connected is minimal when itdisabled. For more exibility regarding this one may design the op-amp such thatthe output is put in a high-Z mode when the amplier is disabled, connections towell-dened voltages such as Vss may then be added outside of the op-amp symbolwhere they are needed.

When circuits have been disabled they generally cannot immediately returnto an operative state once they are enabled but need some start-up time for suchthings as making sure that all bias currents are owing in a steady fashion. As wellas consuming some time this turn-on transition could potentially cause problemsdue to such things as potential latch-ups or stable states other than the intended

25


bias conditions. For these reasons it is prudent to examine the start-up transitionsof circuits with enable controls so that the needed start-up time is known and sothat no errors occur during start-up.3

2.6 Filters

Filters4 can be divided into a number of dierent categories depending on suchthings as whether they operate in the analog or the digital domain and on themethod of implementation.

For the purposes of this thesis purely digital lters (i.e. lters operating indiscrete time using discrete signal levels) are of no interest. However switched-capacitor lters will be briey described, these are not truly digital but neverthe-less share many characteristics with digital lters since they operate in discreterather than continuous time.

Within the general category of purely analog lters (i.e. lters operating in con-tinuous time using continuous signal levels) two commonly used types are active-RC lters and Gm-C lters. The former type uses capacitors and resistors to setthe time constants (or equivalently the poles) of the lter and employs op-ampsas active elements to buer the lters and thus make them insensitive to e.g. loadvariations. The latter type uses transconductance cells together with capacitorsto set the time constants.

Within the general category of active-RC lters a large number of subtypesexist, distinguished by the way in which the passive elements are congured. Twosuch types will be touched upon here: Sallen-Key structures and multiple feedback-structures.

2.6.1 Sallen-Key

Sallen-Key lters can be seen as essentially being derived from two-stage ladderlters by adding a buering amplier with gain K and a feedback path. Designequations for Sallen-Key lters can be found in practically all books about analoglter design, for example [13, p. 163] who provide the following equations for alow-pass design:

R =1

wcCK = 3− 1

Q(11)

Here it is assumed that Z1 = Z2 = R are both resistive and that Zi = Zii = Care both capacitive. wc = 2πfc is the corner frequency (in rad/s, fc is the corner

3The problem with errors during start-up would be prudent to examine even in no enablecontrols are used as the circuit will still go through a start-up phase when the main power isturned on.

4The lters described should more properly be referred to as frequency-selective lters astheir intended function is to pass certain signal frequencies while blocking others. However,this type of usage is so common in analog electronics that it is usually taken as implicit thatfrequency-selective lters are meant whenever lters are mentioned.

26


voutvin

Zii

Z1 Z2

Zi

K

Figure 13: A generalised Sallen-Key lter, adapted from a gure in [13, p. 162]. To ob-tain a low-pass lter Z1 and Z2 should be resistive while Zi and Zii should be capacitive,Ra and Rb are used to set the amplier gain.

frequency in Hz) of the lter and Q is the quality factor, a Butterworth responsemay be obtained by setting Q = 1/

√2.

vout

vin

Zi

Zii

Z1 Z2

Ra

Rb

(a) Single-ended realisation of a Sallen-Keylter, employing an op-amp as the active ele-ment (adapted from a gure in [13]) Ra andRb are used to set the amplier gain.

voutvin

Zi

Z1 Z2

Ra

Rb

FB-

FB+

Zii Ra

Rb

Zi

Z1 Z2

Zii

vFB,-

vFB,+

vFB,-

vFB,+

(b) Fully dierential realisation of a Sallen-Key lter, employing an instrumentationamplier as the active element.

Figure 14: Single-ended and fully dierential implementations of Sallen-Key lters.

As can be seen in the equations presented above it is necessary for the amp-lication to be settable independent of other parameters when using Sallen-Keystructures. This is unproblematic in single-ended designs since two separate feed-back networks can be used for such op-amps, one to set the gain and one connectedin the way illustrated in Figure 13. When using standard fully dierential op-ampsit is not possible however since there is no possibility of using a couple of separatefeedback networks to independently set the gain. As we shall see later however,there exists a type of fully dierential instrumentation amplier that uses a sep-arate input pair to control the gain, employing such an instrumentation amplierinstead of a standard op-amp makes it possible to realise fully dierential Sallen-Key lters.

27


2.6.2 Multiple Feedback (MFB)

voutvin

Z1

Z2

2Zii

Z1

Z2 Zi

Z3

Z3

Zi

Figure 15: A generalised fully dierential MFB lter, to obtain a low-pass structure Z1,Z2 and Z3 should be resistive while Zi and Zii should be capacitive. Adapted from agure in [3, p. 5]

As the name implies, an MFB lter employs multiple feedback paths. Thismakes it possible to control both the gain and the corner frequency with a singlefeedback network, enabling the realisation of fully dierential structures usingnormal op-amps. An easy-to-use set of equations for component sizing is given in[3, p. 5], while easy to use these equations are only valid for a gain of 1 and henceof limited utility, a more detailed set of equations can be found in [10, pp. 7 and19-20].

With a little eort it should most certainly be possible to employ the equationsfrom the application notes presented above to perform the design of an MFB lter.However, Texas Instruments also supply a free-of-charge software package [8] whichcan be used for automatically calculating suitable component values for Sallen-Key as well as MFB lters. Due to the convenience of this approach this softwarehas been used to calculate the component values of the lters used in the naldesign.

2.6.3 Gm-C Filters

Using RC techniques for low bandwidth lters tends to require passive elementswhich are so large that they must be realised o-chip, hence one may want toconsider alternatives. Gm-C lters can be thought of as a class of lters wherethe current-limiting function that is be provided by resistors in an RC-lter isprovided by transistor-implemented transconductors with a large resistance beingroughly equivalent to a small transconductance. Thus it would be possible toproduce more readily integrable designs if one could design transconductors witha small enough gm. In practice there are however limits to how low a gm one can

28


realistically obtain from a transconductor, hence while the technique may make itpossible to produce less area-hungry designs there will still be limits to what can beachieved. Furthermore noise is still a concern and since the input-referred channel-noise unfortunately tends to increase with lower gm one is likely to still end uptrading o between the total capacitance needed to achieve a certain bandwidthand the amount of noise produced by the circuit.

When working with voltage-input, voltage-output op-amps it is often fairlystraightforward to go from single-ended to fully dierential designs by simplyduplicating the feedback networks and connecting them properly (i.e. ensuringthat the positive output feeds back to the negative input and vice versa). Whenworking with transconductor-based designs performing a similar mapping froma single-ended to a dierential design is normally a bit more involved and ofteninvolves adding more transconductors to the circuit.

vout

vinC

iout

(a) Schematic.

voutviniout

gm1

sC

(b) Block diagram.

Figure 16: A single-ended, rst-order Gm-C lter (adapted from [5])

Consider the circuit shown in Figure 16a, this performs the functions illustratedby the block diagram shown in Figure 16a: the output voltage is subtracted fromthe output voltage and the result is multiplied by the gm to produce an outputcurrent which is nally integrated over C to produce an output voltage that canbe fed back to close the loop.

When trying to produce a fully dierential version of this circuit it may betempting to attempt to achieve the same eect by simply cross-coupling the outputwith the input such that the positive input is fed to the negative input and viceversa as shown in Figure 17a. Unfortunately this will not work since it will notresult in a subtraction of input and output, in fact the output would now simplyequal the input since there is a direct connection between output and input. Whatwe need to do is instead to build a circuit which preserves the essential behaviourshown in the block diagram. A circuit which does this is shown in 17b, seen on afunctional level it produces the block diagram shown in 17c where it is apparentthat summing now happens in the current domain rather than at the inputs of adierential pair but that the essential functionality of the single-ended circuit ispreserved.

It may be noted that the dierential version must use two capacitors which are

29


vout

2C

2C

vin iout

(a) Faulty schematic.

vout

2C

2C

vin

gm,1

gm,2

ifb

iin

iout

(b) Working schematic.

vout

vin

ifbgm,1

1sC

gm,2iin

iout

(c) Block diagram.

Figure 17: A fully dierential, rst-order Gm-C lter (adapted from [9]).

30


twice the size of the one used in the single-ended variety. This is necessary becausea dierential transconductor will, for the same gm, output the same amount ofcurrent (with opposite signs) in each output as the single-ended version will do inits single output and hence it has an eective gm which is twice that of a singleended one. One may exploit the Miller eect to reduce the total capacitanceneeded by placing a single capacitor of size C in between the two output nodes,however this may lead to concerns with the stability of the CMFB loop and onemust in this case also pay some attention to the top/bottom-plate problem thatcan arise when realising capacitors in an IC process [9, pp. 577-578 ].

2.6.4 Switched-Capacitor Filters

In RC-lters or Gm-C lters some value needs to be made small or large in absoluteterms in order to achieve a small bandwidth. In a switched-capacitor lter thecorner frequency is set by the ratio of two capacitors together with the clockfrequency at which the structure is run and thus it is - at least in theory - possibleto achieve an arbitrarily low lter bandwidth without resorting to using extremelylarge or small element values.

In practice there are some problems with this. First of all a switched-capacitorlter performs sampling and is thus subject to the Nyquist theorem, hence onenormally cannot allow the clock frequency to be too low since this would leadto unacceptable aliasing artifacts. Second, it is not possible to make the ratiobetween the clock frequency and the corner frequency arbitrarily large as the ltereventually stops working as intended when this ratio grows too big.

Taken together, these two problems make switched-capacitor lters unwieldy ina situation where noise is a large concern and ltering is undertaken mainly to limitthe total noise bandwidth of the system. Obviously limiting the noise bandwidthis meaningless if noise from the entire unwanted part of the frequency spectrumhas already been folded down into the wanted part. Hence in such a usage scenarioit would still be necessary to limit the bandwidth using a purely analog lter evenbefore applying the switched-capacitor one. Furthermore the bandwidth of thisanalog lter would need to be small enough to allow the switched-capacitor lterto work with a reasonable ratio between sampling frequency and corner frequency.

3 Design of Operational Ampliers

3.1 Input Range

The input range of an op-amp generally refers to the range within which the CMvoltage can be allowed to vary, this is described in detail in [7, p. 82]. This rangeis determined by the input stage and, more specically, in which general region itends up depends on whether NMOS or PMOS input transistors are used.

31


For NMOS inputs there is a region below the Vgs of the input transistors plusthe Vds,sat of the biasing transistor where normal assumptions about transistorsbeing in the saturation region no longer hold. Similarly there will be an area abovewhich such assumptions are no longer valid, the precise nature of this area willdepend on the type of load being used but it will generally involve and expressionon the form (VDD − Vload) + Vgs − Vsat. This expression reects the fact that therange is set by the minimum Vds,sat of the input transistors, the part in paranthesesis the quiescent voltage at the node just above the input transistors from whichwe subtract Vds,sat as the total Vds,sat must be exceeded. We add Vgs since the gatevoltage will always exceed the source voltage by this amount.

For PMOS transistors the situation is similar but with the directions reversed.I.e. VCM,in is bounded upwards by VDD − Vgs − Vds,sat and downwards by (VSS +Vload)− Vgs + Vds,sat.

Ibias,N

Ibias,P

iout,N

iout,P

vin,+ vin,-MN,+ MN,-

MP,+ MP,-

VDD

VSS

Figure 18: Using two parallel input pairs to extend the input range.

Generally, the most severe of these limitations will be the downwards one forNMOS input stages and the upward on for PMOS ones. In some situations havingthe input range limited in this way may not be acceptable, in such situations theinput range may be expanded by using an NMOS input stage in parallel with aPMOS one and summing their currents in such a way that the total input stage gmequals the combined gm:s of both input pairs. If there is sucient overlap betweenthe input ranges of the two pairs and if the non-dominant bound (i.e. the upperbound for the NMOS pair and the lower one for the PMOS pair) on the inputrange extends beyond the rail this will enable a rail-to-rail input range.

32


There are some drawbacks to using this type of input stage, the main one isthat the gm will not be constant over the input range but will vary depending onwhether both or just one of the complementary input pairs are turned on. Sincebandwidth of the input stage is a function of its gm this will cause the bandwidth ofthe stage to vary over the input range which may complicate the task of achievinga stable op-amp. [7, pp. 83-96] provides a detailed discussion about ways to reducethis variation with a large variety of circuits proposed to alleviate the problem.

3.2 Swing

The swing of an op-amp refers to some measure of the range in which the outputvoltage of the amplier can be allowed to vary. For theoretical purposes it cansometimes be useful to dene this in terms of the points at which output stagetransistors start leaving their saturation mode of operation as this allows one toconstruct analytical expressions for the swing. However such an approach mayhave limited practical value since the op-amp might not necessarily stop workingas intended even though some transistors are no longer operating in saturation.Elad Alon [1, lecture 10 (video 13, 11:50)] put forth the idea of dening swing interms of some minimum gain. In this case one would x a minimum gain thatthe amplier must deliver and dene the swing to be the range of output voltageswithin which this gain can be guaranteed. Since the precision of an op-amp'sclosed-loop gain depends on the magnitude of the open-loop gain one can oftentranslate precision requirements into a minimum open-loop gain in the case ofop-amps. Using this approach one can then determine the swing of the op-ampas outlined above, making this denition suitable when working with op-amps.

For details on how to set up Cadence for measuring the swing when dened inthis manner, see Section ??.

3.3 Noise

3.3.1 Noise Power Spectral Density Functions and Total Noise

Noise can be described in a number of dierent ways and which description ispreferable depends on the situation at hand. In particular, one often nds noisebeing described in terms of it PSD (Power Spectral Density) or in terms of totalnoise power, voltage or current.

The PSD of a noise source is a function that shows how much noise exists ateach point in the frequency spectrum. The total noise within some frequency bandmay be obtained from the PSD by integrating this function over the frequencyband in question. An important conclusion that may be drawn from this is thatthere are two basic ways of reducing the total noise of a system. One can targetthe PSD itself by trying to reduce the noise density at all frequencies of interest,the other way is to simply reduce the bandwidth of the system since one may then

33


in eect integrate over a smaller frequency band leading to a smaller total noisepower. Limiting the bandwidth may be particularly desirable if the PSD is not atbut shows humps at certain frequncies. For instance (as will be described in moredetail in Section 3.4.3) reducing 1/f -noise by using chopping is based on such anapproach, chopping devices exhibiting 1/f -noise eectively causes the 1/f -noise tobe translated to the chopping frequency (and any harmonics of it that are presentin the chopping modulator) enabling them to be ltered out. With thermal noisewhich exhibits a at PSD function the gains from reducing the bandwidth are notquite as great, nevertheless the total noise will for such noise be linearly dependenton the bandwidth and hence reducing the bandwidth by half will also reduce thetotal noise power by half.

3.3.2 Summing of Noise Sources

Summing of noise sources is not quite as straightforward as one might rst thinkas it involves summing noise powers rather than noise voltages or currents. Thismeans that given two noise sources expressed as noise voltages it is necessary toexpress them as powers for the purpose of summing, after summation one can thenswitch back to an expression in terms of voltage if such a way of expressing thenoise is desired. Given two noise voltages connected in series as shown in Figure

v2v1

Vn,1 Vn,2

Vn,tot

(a) Series connected voltagesources.

v2

v1

In,1 In,2

In,tot

(b) Parallel current sources.

Figure 19: Summing of noise sources.

19a the total noise voltage can be obtained as

Vn,tot =√V 2n,1 + V 2

n,2 (12)

For the current sources shown in Figure 19b summing proceeds in a similar manner:

In,tot =√I2n,1 + I2n,2 (13)

34


A consequence of this way of summing is that the contribution from weaker noisesources quickly becomes insignicant. For example, summing two noise sourceswith noise voltages of 1V and 0.25V respectively produces a total noise voltage ofroughly 1.03V. From this it should be apparent that when attempting to reducethe total noise in a system one should always concentrate on the strongest noisesources rst as the weaker ones will tend to be insignicant.

Nout,tot

Nin,0 H0

Nin,1 H1

...

Nin,K HK

Figure 20: Summing of K noise sources aected by transfer functions, the noise signalsNn represent generalised signals that may be either voltages or currents.

When the situation is such that transfer functions must be taken into accountsome care must be taken to treat the transfer functions correctly when summing.The output noise signal Nout,n from a block is

Nout,n = HnNin,n (14)

Since the signals sum in the manner previously described the total summed noisewill be

No,tot =√H2

0N2in,0 +H2

1N2in,1 + . . .+H2

KN2in,K (15)

3.3.3 Noise In Cascaded Amplier Structures

In most cases it is not the output noise of an amplier in absolute terms that is ofinterest but rather some measure of how much noise is present in comparison tothe strength of some desired signal. This can expressed in very direct terms in theform of an SNR but can also be expressed by e.g. a number of bits of resolutionsince this implicitly expresses a requirement on the amount of noise in comparisonto the smallest signal step that should be possible for the ADC to resolve.

The noise present at the output of an amplier may be input referred by thedividing the strength of the noise with the gain. Doing so is useful since it allowsus to make fair comparisons of the noise performance of ampliers with dierentamounts of gain. It also allows for making a comparison between the noise fromthe signal source and the noise added by the amplier which can be useful since itmakes it possible to check if the noise contribution from the amplier is signicant.

35


It ought to be pointed out that for such gures to be meaningful it is generallynecessary to divide the entire noise spectrum with the signal gain. For manyampliers the gain starts dropping of sharply at some frequency and hence dividingthe output noise with the frequency dependent gain may seem to be the properway to input refer the noise. However, input referal of the noise is done in theinterest of comparing the total noise strength to the signal strength. For such acomparison to be meaningful the noise must be changed in the same manner asthe signal. For an amplier with a proper bandwidth (in relation to the highestfrequency components present in the input signal) the signal will be amplied bythe DC gain or some mosgain close to it and it is thus generally safe to divide theoutput noise by the amplier's DC gain for purposes of input referring it.

3.3.4 MOSFET Noise

V1/f

Figure 21: Schematic model of a MOSFET with 1/f noise (adapted from a gure in [9,p. 199]).

There are two major sources of noise in MOSFET transistors. The rst is 1/fnoise which is sometimes referred to as icker noise, this type of noise derives itsname from the way its density falls o with increasing frequency. Due to thisthe 1/f noise tends to dominate the total transistor noise when working at lowfrequencies. The PSD of 1/f noise when modelled as in Figure 21 is described by

V 21/f =

k

WLCoxf(16)

where k is a constant whose value is determined by the characteristics of thedevice, W is the transistor width, L its length, Cox its gate capacitance per unitarea and f the frequency [9].

An important conclusion which can be drawn from the above expression is that1/f noise is inversely proportional to the area of a MOSFET. Since most othertransistor properties of interest are (at least in the long-channel case) controlled bythe W/L ratio one would usually desire to keep this ratio constant while changingthe length of the transistor. In this case the expression above can be rewritten as

V 21/f =

k

(W/L)L2Coxf∝ 1

L2(17)

36


Ich

Figure 22: Model of the channel noise current due to a CMOS device.

Thermal noise is the second type of noise in MOSFETs and is caused by theresistive nature of the transistor channel, for this reason it is sometimes referredto as channel noise. It can be modelled as shown in Figure 22 and then has a PSDof

I2ch = 4kTγgm (18)

where k is once again a constant dependent on device characteristics, T is thetemperature in Kelvin and γ is a constant that is 2/3 for long-channel devices andgenerally somewhat higher for short-channel ones [12].

Vch

Figure 23: Model of the input-referred channel noise due to a CMOS device.

Since the input-voltage-to-output-current gain of a transistor is determined byits gm we may input-refer this noise source by dividing the above expression byg2m. This results a voltage noise at the transistor gate as shown in Figure 23 withthe the following expression for the noise PSD

V 2ch =

4kTγ

gm(19)

Hence we see that the input referred channel noise power of a transistor is infact inversely proportional to its gm rather than being proportional as one mightthink from the previous expression. It ought to be remarked that this way ofinput-referring the channel noise assumes that the gate current is zero, due to thecapacitive nature of the gate it is therefore unsuitable for use at high frequencies[9, pp. 199 and 201].

Some care needs to be taken in situations such as the one depicted in Figure24, the channel noise due to Mload should here be divided by g2m,in rather than by

37


VSS

VSS

VDD VDD

vin Min

MloadMdiode

In,in

In,load

Ibias vout

Figure 24: A CS stage with a current-source load, for such a stage the channel noise dueto the load is input-referred by dividing its noise current with the gm of the amplifyingtransistor.

g2m,load in order to obtain an equivalent input referred voltage noise source. Wethus get the following expression for the input referred noise

V 2ch,load = 4kTγ

gm,loadg2m,in

(20)

In this case increasing gm,load would cause the noise to increase rather than todecrease and the proper way to reduce the input referred noise is to keep thegm,load/gm,in ratio small. A more detailed analysis of the type of amplier stageshown in Figure 24 is given in [17, lecture 4, p. 34] where it is shown that thetotal input referred channel noise for the entire stage is given by

V 2ch,tot =

4kTγ

gm,in

(1 +

gm,loadgm,in

)(21)

From this it is clear that the primary way to decrease the input referred channelnoise of such a stage is to increase the gm of the input transistors. If the input-stage channel noise of an OP using Miller compensation is decreased in such away this leads to a tradeo between stability and channel noise as increasing gm,inwill increase the bandwidth of the input stage. The stability of the OP is inturn determined by the amount of separation that can be achieved between thedominant (i.e. lower) pole of the input stage and the one due to the output stage,hence achieving stability generally becomes more dicult as the bandwidth of theinput stage is increased.

In circuits driving capacitive loads one may instead opt for making the poleassociated with the output stage dominant and compensate using the load capacit-

38


ance connected to the output pole. With such a compensation scheme increasingthe gm of the input stage would improve phase margin since it would move thenon-dominant pole further away from the dominant one, hence such a schemewould appear to be attractive when optimising for noise. However it must notedthat the feasibility of using such a scheme is dependent on how large the loadcapacitance can be made since the compensating load capacitance oers no polesplitting eect and must thus be made very large to oer enough compensation.

3.3.5 Choice of Architecture

When considering the input referred noise of a multi-stage amplier the rst stagewill generally dominate since the output noise of all following stages will be dividedby the gain of several stages (at the very least their own gain and that of the inputstage) for obtaining the input referred noise. Due to this the primary concernswhen choosing an architecture for minimising noise will concern the input stage.To achieve low overall noise the input stage should of course add little noise itself,it should also provide as much gain as possible since this will minimise the impactof later stages on the input referred noise.

VDD

Ms1,-Ms1,+

Ibias,s1

MCS,N

VSS

vin,+

MN-cascode,-

Ms1,bias

MP-cascode,-

VDD

vCM,error

Vbias,N2

Vbias,P2

Vbias,P1

vout,+

Ibias,stack

Vbias,P1

vin,-

MCS,P

Figure 25: The right half of a folded-cascode op-amp.

In certain architectures there may be other transistors which must be treatedin a similar manner to the input stage regarding noise. In the folded-cascode stageshown in Figure 25 it can be seen by inspection that the transfer function froma current source placed in parallel with MCS,N or MCS,P (where CS in this case isused as an abbreviation of current source) to the output will be the same as that

39


for a current source placed in parallel with the rightmost input transistor. Dueto this the noise currents generated by MCS,N or MCS,P will have a similar impacton the output noise as will the noise current from the rightmost input transistor,conversely we may only divide these current sources by the g2m of the input tran-sistors for the purposes of calculating the PSDs of the equivalent input referrednoise voltage sources. This tends to make folded-cascode op-amps a somewhatunfortunate choice for applications in which noise performance is critical as theextra current source needed will add a signicant amount of extra noise at thevery start of the amplication chain.

3.3.6 Input Stage

To achieve low noise in an op-amp PMOS input devices are generally preferableto NMOS inputs due to P-type devices exhibiting lower icker noise than theirN-type counterparts . Even so this choice should be given some considerations asthere are certain circumstances where the lower 1/f noise is of less importancethan other concerns even when low noise is a requirement. One example of sucha situation is when chopping is applied, see 3.4.5 for more details on this.

The noise from the biasing transistor of the input pair has little eect on thenoise at the output of the OP since any noise current injected by this transistorwill ideally aect both outputs equally and hence not cause any dierential noisecomponent at the output.

Using resistors rather than transistors as loads for the input stage can cause asignicant reduction in the amount of input referred noise added by the rst stage.However, this introduces a tradeo between gain and swing since for a given biascurrent linear resistors with a resistance equal to the g−1ds of the transistor loadswill generally cause a larger voltage drop. Due to this the resistors must normallybe choosen to have a smaller resistance than the one that could be achieved withtransistors in order not to restrict the possible swing too much.

The dierent frequency characteristics of the noise generated by transistors andresistors should also be taken into account when deciding whether to use resistoror transistor loads. For transistors 1/f noise is generally dominant while resistorsideally only generate thermal noise which is spread evenly throughout the wholefrequency spectrum, thus resistors may be preferable as loads in situations when itis possible to restrict the bandwidth of the system to only include low frequencies.The overall nature of the system may also aect this choice, if chopping is used1/f noise may largely be removed and thus transistor loads may be preferable insuch a situation. If correlated double sampling is used the situation is slanted evenmore in favour of using transistor loads since this technique will remove noise atlow frequencies but cause noise at higher frequencies to be folded down.

When using transistor loads one can reduce the amount of 1/f noise from theloads by increasing their area, if this is done by increasing the length this also hasthe benecial eect of increasing the gain. The 1/f noise voltages at the inputs

40


of the load transistors is input referred by rst multiplying them with the g2m ofthe load transistors and then dividing the resulting noise current by the g2m ofthe input transistors. Hence this noise can be decreased by increasing the gm ofthe input transistors or decreasing that of the load transistors. From Equation(7a) it gm ∝ W for a transistor in saturation mode when the bias current is keptconstant, thus one possibile way of decreasing the gm of the load transistors is toreduce their width. Reducing the width will however also cause a linear reductionin the area, since the amount of 1/f noise is inversely proportional to the areareducing the width will cause a net increase in the amount of input referred 1/fnoise.

If large enough areas are used the channel noise (denoted by id by Spectre whenprinting a noise summary) of the input and load transistors may start to dominateover the icker noise (denoted by fn in a noise summary). The PSD of the noisecurrent for this noise is proportional to the gm of the transistor generating thenoise. However, when transforming these noise current to input referred noisevoltages one divides by the g2m of the input transistors. Thus this noise may bedecreased by increasing the gm of the input transistors or decreasing that of theload transistors, as was the case for the 1/f noise due to the load transistors.

3.3.7 Output Stage

In the classic OP architecture the channel noise of the transistors in the outputstage may dominate at high frequencies. This noise is input referred in two steps:rst the power of the total noise current present at the output is divided by theg2m of the output transistors and then the resulting noise voltage is divided by thesquared voltage gain of the input stage. There are thus two basic ways to decreasethe impact of the output transistor channel noise, either by increasing the g2m ofthe output transistor or by increasing the voltage gain of the input stage.

3.4 Closed-Loop Techniques For Reducing Low-FrequencyNoise

A number of design techniques exist for reducing the oset and 1/f noise of anamplier by using surrounding circuitry rather than by altering the design of theamplier itself. These two phenomena can easily be distinguished in theory: anoset is a constant DC signal superposed on the desired signal and 1/f noise is arandom variation in the signal quantity that exists primarily at low frequencies.In practice however this distinction breaks down since it is hard to nd actualDC quantities (in accordance with the theoretical concept of a DC quantity) in anactual circuit where all quantities tend to exhibit some variation over time, henceit is appropriate to refer to both of these phenomena as low-frequency noise.

While this blurring of the distinction may seem to have little in the way ofpractical consequences it does in fact point us towards something that is of prac-

41


tical signicance: since oset and 1/f noise cannot be clearly distinguished inpractice they can also not be distinguished between by any mechanism designedto combat one of them and hence any scheme devised to alleviate problems withone will also alleviate problems with the other.

All of the techniques described here work by taking advantage of self-correlationover time in the disturbing signal, hence they can only be used to reduce low-frequency noise. It ought to be noted that low-frequency is a rather ill-denedconcept and highly dependent on circumstances, for the the noise-reducing tech-niques described here this has the implication that the noise frequencies for whichthey provide eective reduction is dependent on what speed the reduction tech-nique is working at. Hence it is in theory possible to reduce noise at any frequencyusing these techniques although this would require elements with innite band-width and is thus not possible in practice.

3.4.1 Correlated Double Sampling (CDS)

Correlated double sampling - commonly abbreviated CDS - refers to a family oftechniques which sample a disturbing signal during a sampling phase where theinput signal is known and then subtracts it during a valid operation phase. Inanalog circuits this can be done by sampling the oset on a capacitor during thesampling phase and then subtracting the voltage across this capacitor during thevalid phase.

VOS

vinvout

φ1

φ1C1

Figure 26: Illustration of output oset cancellation (adapted from a gure in [1, lecture22]).

Elad Alon [1, lecture 22] has described a relatively simple technique - illustratedin Figure 26 - where the oset as seen at an amplier output is sampled for azero input (i.e. with the input tied to ground) and then subtracted from theoutput during the valid phase. This is commonly referred to as output osetcancellation and has the advantage of being simple. Since the oset is removedfrom an already amplied signal it is also insensitive to errors introduced by theswitched in comparison with techniques that remove the oset already at theinput. For large gains this technique is unlikely to be sucient however as theamplier may already be driven into saturation before the oset can be removed,hence it is often preferable to remove the oset at the input to allow the amplierto function over a wider range of input values.

42


φ2

φ1 C1

C2

vin

vout

VOS

φ2

φ1

φ2

(a) Basic circuit.

C1

C2

vin

vout

VOS

(b) Circuit during ϕ1 (validphase).

C1

C2

vout

VOS

(c) Circuit during ϕ2 (samplingphase).

Figure 27: Resettable switched-capacitor gain circuit with input oset cancellation [9, p.429]. The version shown here is the single-ended one presented in the reference, a fullydierential circuit may be obtained by substituting the op-amp for a fully dierentialone and mirroring the passive network across the amplier.

43


Figure 27 shows a switched capacitor amplier - described in [9, chapter 10] -that removes oset and 1/f noise by using correlated double sampling. Due to thevirtual shortcut between the op-amp input terminals created by the feedback loopthis eectively removes the oset already at the input of the amplier. Duringthe sampling phase (ϕ2) the oset voltage of the OP is sampled on C1 and C2 dueto the virtual shortcut resulting from the amplier feedback control. During thevalid phase the capacitors are placed in such a way that the oset is cancelled.During this phase of operation the capacitors can essentially be viewed as voltagesources, for such a perspective to be valid the time constants associated with thecapacitors must be large in comparison to the period with which noise is sampled(the time constant associated with each capacitor will depend on the size of thecapacitor itself as well as the size of leakage currents due to such things as niteswitch resistances).

Obviously any disturbance that is to be removed by the sampling must be moreor less constant during one sampling period. Precisely what should count as beingconstant is not xed once and for all but rather depends on circumstances and inparticular upon how well the disturbance needs to be cancelled and the speed atwhich disturbances are sampled. The faster a disturbance varies compared to thesampling speed the less well it will be cancelled, hence this type of circuit doeswell at removing disturbances with a low frequency (such as the dominant portionof 1/f noise) but poorly at removing disturbances with a high frequency (such asthe dominant portion of thermal noise).

In fact the sampling mechanism employed in this circuit makes noise perform-ance worse at high enough (compared to the sampling frequency) frequencies.This can be explained in an intuitive manner by considering that for noise whichis high enough frequency there will essentially be no correlation between the noisesampled on the capacitor during the sampling phase and the noise obtained duringthe valid phase. Hence for high frequencies the sampling essentially causes twouncorrelated noise sources to be added together which results in higher total noiseat such frequencies. This can also be explained - but in a less intuitive manner- by noticing that in any sampling process frequency content above the nyquistfrequency will be folded down, hence the total noise power above fs/2 (where fsis the sampling frequency) will be folded down into the desired band and worsenthe noise performance.

In order to avoid charge sharing eects which could aect the precision of thecircuit it should be ensured that ϕ1 and ϕ2 are non-overlapping.

It should be noted that in this circuit the output signal jumps back to theoset voltage during each sampling phase as illustrated in Figure 28, This placeshigh requirements on the slew rate of the OP.

In [9] we also nd an improved version of the previously presented switched-capacitor amplier. The major improvement here compared to the previous circuitis the addition of capacitor C3 which is used to sample the output voltage of theamplier during the valid phase and hold it at the last seen output voltage during

44


0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10−3

0

0.2

0.4

0.6

0.8

1

t (s)

v ϕ(V

)

Clock

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10−3

−1

−0.5

0

0.5

1

Signals

t (s)

v(V

)

voutvin

Figure 28: Typical output signal from the switched-capacitor amplier presented inFigure 27 when used with a gain of 1. In the sampling phase the output goes to theoset voltage which is 0.2V for the system illustrated in the gure.

the sampling phase as illustrated in Figure 30. For input signals which do not varyin level to quickly compared to the sampling frequency this has the advantage ofreducing the slewing requirements placed on the OP.5

The improvements also include the addition of C4 which is used to ensure thata feedback path is always present during the non-overlap period of the clocks.This reduces glitching which aside from being advantageous in the actual circuitcan also be very helpful for simulation - particularly when making heavy use ofideal elements - since glitches tend to produce very sharp transitions which canforce the simulator to reduce its minimum step size and thus prolong simulationtimes to the point where it is no longer feasible to simulate the circuit.

3.4.2 Correlated Double Sampling and Noise Spectrum

The eects which correlated double sampling have on noise have been touched onpreviously, but then only in an intuitive manner which may be useful for under-standing the basic phenomena involved but is of little use for predicting the noise

5One could be led to suspect that C3 worsens the noise performance since any samplingmechanism will fold down high-frequency noise and C3 provides no advantages vis-à-vis low-frequency noise. However, the C3 ideally has no eect on the output during the valid phase butonly during the sampling phase and thus any noise penalty incurred would only aect this phaseof operation.

45


φ2

φ1 C1

C2

vin

vout

VOS

φ2

φ1

φ2

C3

C4

φ1

(a) Basic circuit.

C1

C2

C3

C4

vin

vout

VOS

(b) Circuit during ϕ1 (valid phase).

C1

C2

C3

C4

vout

VOS

(c) Circuit during ϕ2 (sampling phase).

Figure 29: Improved resettable switched-capacitor gain circuit with input oset can-cellation [9, p. 431]. The version shown here is the single-ended one presented in thereference, a fully dierential circuit may be obtained by substituting the op-amp for afully dierential one and mirroring the passive network across the amplier.

46


0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10−3

0

0.2

0.4

0.6

0.8

1

t (s)

v ϕ(V

)

Clock

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10−3

−1

−0.5

0

0.5

1

Signals

t (s)

v(V

)

voutvin

Figure 30: Typical output signal from the improved switched-capacitor amplier presen-ted in Figure 29 when used with a gain of 1.

performance of a circuit.Elad Alon [1, lecture 22] has performed a more rigorous analysis. This analysis

starts by noticing that in the time domain the noise is shaped by the subtractionof noise delayed by Ts/2 (where Ts = 1/fs is the sampling period) from the directnoise signal, i.e.

Vn,out(kTs) = Vn,in(kTs)− Vn,in(kTs − Ts

2

), k ∈ N (22)

A pure delay of δ in the domain corresponds to the exponential function e−jωδ inthe jω-plane, hence in the frequency-domain we may express the output noise onthe form

Vn,out(jω) = Hn(jω)Vn,in = (jω)(1− e−jωTs/2

)Vn,in (23)

where it readily seen that the noise transfer function Hn(jω) =(1− e−jωTs/2

). By

expanding e−jωTs/2 using Euler's identity followed by employing the Pythagoreantrigonometric identity the magnitude of the transfer function may nally be ex-pressed as

|H(f)| =∣∣∣∣2 sin

(ω(f)Ts

4

)∣∣∣∣ =

∣∣∣∣2 sin

(πf

2fs

)∣∣∣∣ (24)

Since sin(π/2) = 1 it is apparent that while at low frequencies the noiseis attenuated, at f = fs the sampling causes the noise to double in strength.Hence - as can be seen in Figure 31 - the noise shaping eects of CDS can under

47


0 500 1000 1500 2000 2500 3000 3500 4000 4500 50000

0.5

1

1.5

2

2.5

f

H

n (V/V)

Vn (V/√Hz)

Hn⋅V

n (V/√Hz)

Figure 31: Illustration of the eects of CDS on the noise performance of a system. Hn

is the noise transfer function as expressed in (24) (for fs = 1kHz) and Vn is an imaginednoise vs. frequency function used for illustrative purposes. The y-axis has been leftunlabeled due to the diering units used there.

48


certain circumstances actually cause the noise performance to become worse. FromFigure 31 it is apparent that to gain an advantage from CDS noise shaping wegenerally need the CDS sampling frequency to be signicantly higher than theknee frequency and for the thermal noise to be low in comparison to the total 1/fnoise.

3.4.3 Chopping

vn

vin vout

1

-1

Figure 32: Block-level illustration of a basic chopping amplier.

Chopping can be used to remove low-frequency disturbances (such as osetsor noise) by exploiting frequency modulation. The most basic form of choppingis shown in Figure 32. The input signal is rst modulated (i.e. multiplied) bya square-wave clock signal with frequency fclk and levels 1 and −1, it is thenamplied by a noisy amplier and after this modulated once more by the sameclock signal before it is low-pass ltered.

When seen as time-domain process it can be easily realised that modulatinga signal twice using the exact same clock signal with levels 1 and −1 will notaect the signal at all since it will be alternately multiplied with 1 · 1 = 1 and−1 · −1 = 1. Hence the chopping should ideally have no eect whatsoever on thesignal.

Disturbances added by the amplier on the other hand are modulated onlyonce. Hence disturbances which are at or essentially at DC will after the secondmodulation show up as square waves with the same frequency as the clock signal.These disturbances can then be removed by the low-pass lter.

To better see what happens to the noise added by the amplier we can alsotake a frequency-domain view of the system. The product of two sinusoidals canbe written

cosx cos y =1

2(cos(x− y) + cos(x+ y)) (25)

Observing the noise spectra before and after modulation it will be seen that thishas the eect of creating two copies of the 1/f noise for every harmonic of theclock signal: one which is shifted up by the frequency of the harmonic and onethat has been similarly shifted and then mirrored around the harmonic frequency.

49


This is illustrated in Figure 33. It ought to be noted that since one obtains onecopy of the noise spectrum for each harmonic of the modulator the amount ofthermal noise may become larger. However the magnitude of the harmonics for asquare wave fall of fairly quickly6, due to the way that noise sources are summed(see Section 3.3.2) the increase in the level of thermal noise is thus quite modest.

0 0.5 1 1.5 2 2.5 3 3.5 4

x 104

0

1

2

f (Hz)

P(W

)

Original Noise Spectrum

0 0.5 1 1.5 2 2.5 3 3.5 4

x 104

0

0.5

1

1.5

f (Hz)

P(W

)

Spectrum of the Modulating Square-Wave

0 0.5 1 1.5 2 2.5 3 3.5 4

x 104

0

1

2

3

f (Hz)

P(W

)

Noise Spectrum After Modulation

Figure 33: Eect of chopping on low-frequency noise.

While chopping would ideally have no eect on the signal this is unsurprisinglynot the case in practice. In particular, the nite slew rate of the amplifer causesartifacts (in the form of ripple at the clock frequency) to be introduced since theamplier is forced to switch the polarity of its output twice for every clock cycle.This limits the usable clock frequency to values well below the bandwidth of theamplier and since all signal frequencies must be well below the clock frequencythis makes chopped ampliers unsuitable for high-frequency applications.

One way to get around the frequency limitation is to use chopper-stabilisedrather than chopped ampliers. Such a structure involves two signal paths theoutputs of which are summed: a chopped high-gain one and an un-chopped lowgain one. The nite slew rate of the amplier causes the gain of the chopped path

6Mathematically, a square wave can be constructed as

, vsq(t) =4

π

∞∑n=1,3,5,...

[1

nsin (2πnft)

], (26)

hence the spectrum contains only odd harmonics of magnitude 4nπ , n ∈ 1, 3, 5, . . . [16].

50


vout

1

-1

vn,1

vin

vn,2

Av,1

Av,2

Figure 34: Block-level illustration of a chopper-stabilised amplier with feedback beingused to control the gain, adapted from a gure in [15]. The parts within the dotted linesshow the amplier itself while the parts outside of this shows the feedback path.

to fall o at higher frequencies and hence the un-chopped path becomes dominantat such frequencies while the relative gains of the ampliers can be choosen suchthat the chopped path becomes dominant at low frequencies (by ensuring thatAv,2 Av,1). The low-frequency noise and the oset will then be dominated bythe contributions from the chopped path (due to the higher gain of this path atlow frequencies) and will thus be supressed well by the chopping of this path. Thedominance of the un-chopped path at high frequencies in turn supresses the rippleintroduced by the chopping.

A possible implementation of this block diagram is shown in Figure 35. Herethe ltering is performed by the integrator formed by gm,4 and the two ltercapacitors, the voltage output from this integrator is converted into a currentby gm,5 to allow the summation shown in Figure 34 to take place in the currentdomain. The structure employs nested Miller compensation, more information onthis compensation technique can be found in [7].

3.4.4 Digital Techniques

Digital techniques can also be used to remove osets by using some calibrationmechanism to approximate the oset and then compensate for it by some suitablemechanism. An example of this is to use a two-input summing amplier whereone of the inputs is the normal signal input and the other is a compensationinput tied to a digitally controlled current source (such a current source can beimplemented using binary-weighted current mirrors with the outputs connectedtogether to produce a sum of binary-weighted currents). Setting the signal inputto some known value would then make it possible to perform a calibration routine

51


1

-1

Cfilter,b

Cfilter,a

Ccomp,1a

Ccomp,1b

Ccomp,2a

Ccomp,2b

vin voutgm,1

gm,3 gm,4 gm,5

gm,2

Figure 35: A possible implementation of the amplier shown in Figure 34, adapted froma gure in [7, p. 367]. The feedback circuitry is not shown in this gure, hence what isillustrated here corresponds to the parts within the dotted lines in Figure 34.

by comparing the output of the amplier to what it ought to be. By graduallyadjusting the bits controlling the compensating current source in a manner similarto the way a SAR ADC performs a conversion the error between the is-outputand the ought-output of the amplier can then be minimised. At the end ofthis procedure the resulting value can then be stored in a register and used tocompensate for DC osets.

While this technique uses a very dierent mechanism than the switched-capacitorschemes described in Section 3.4.1 the basic method is still the same: the erroris sampled during a non-valid phase of operation (it should be obvious from thepreceding description that the amplier must be taken o-line during the calibra-tion routine) and then subtracted during the valid phase. Unlike capacitors whichexhibit leakage and thus cannot be used to store a value for very long a digitalvalue can be stored more or less indenitely. At the same time the techniquedescribed here is slower due to the time needed for the calibration routine, hencethis technique is mainly useful to combat more or less static osets.

It ought to be noted that the technique can - at least in theory - also be usedto supress noise but that this is hardly feasible in practice. Since the underlyingmethods are identical the analysis presented for the eects of CDS on noise is alsolargely valid in this case (although the digital technique also produces roundingerrors which would need to be accounted for in a proper analysis of its eects onnoise). It is thus readily seen that this technique will supress noise that is lowenough in frequency compared to the frequency with which the calibration routine

52


is performed while noise that is high in frequency compared to this can becomemore problematic (with reference to Figure 31 we can however conclude that alsosome higher-frequency noise will be supressed even though some of it will be madeworse).

3.4.5 Op-Amp Design Considerations When Correlated Double Samplingor Chopping is Used

When using CDS or chopping the primary concerns about noise as regards thedesign of the op-amp change due the noise-shaping eects of these two techniques.In particular the normal dominance of 1/f noise no longer occurs and insteadthermal noise tends to become the primary concern.

When CDS is used the 1/f noise will generally be attenuated enough to benegligible but the full noise power from practically all thermal noise within theop-amp bandwidth will be folded down into the desired band. For these reasonsreducing 1/f noise will no longer be much of a concern when using CDS andinstead the total thermal noise needs to be minimised.

When using chopping the situation is similar in that minimising 1/f noisebecomes irrelevant. As is mentioned in Section 3.4.3 this technique causes theentire double-sided noise spectrum to essentially get translated such that the 1/fnoise is centered at the chopping frequency rather than at DC. At the same timethe noise spectrum that was formerly centered on the chopping frequency becomescentered at DC, if the chopping frequency is choosen high enough this noise willbe dominated by the thermal component and thus all design eorts can focus onminimising thermal noise. Since the spectrum of thermal noise is at there isno possibility of individually reducing the thermal noise at a certain frequencyand hence in actual practice the noise concerns when designing an op-amp foruse with chopping tend to become the same as when designing one for use withCDS. However one needs to be a bit more careful about what noise dominatesat the chopping frequency when chopping is used. Generally one wants to use aslow a chopping frequency as possible (to reduce chopping artifacts and bandwidthdemands placed on the op-amp) which, unless requirements due to the highestexpected signal frequencies forces it higher, usually means placing it slightly abovethe 1/f -noise knee frequency. Lowering the thermal noise tends to raise the kneefrequency and hence the op-amp noise may once again start becoming dominatedby the 1/f noise. If further reduction of noise is required one may thus be facedwith the choice of either using a higher chopping frequency so that a frequencyregion dominated by thermal noise becomes translated to DC or lowering the 1/f -noise at the previously selected chopping frequency to make the thermal noisebecome dominant there again. It is evident from this that designing an op-ampfor use with chopping can easily become an iterative process where design decisionsmade at the overall amplier level and at the op-amp-design level can aect andmay need to be weighed against each other.

53


As was mentioned in Section reducing thermal noise is done primarily by ad-justing the ratio between the load- and input-transistor gm:s in the input stage.Hence using CDS or chopping can potentially allow for smaller designs (for a givenamount of noise) since reducing the noise does not necessarily involve increasingtransistor sizes.

3.5 Driving a Load

The driving capability of an OP is determined by range of dierent factors andprecise predictions can therefore be hard to make. In general it is however possibleto determine some rough limits based on the amount of current available to theoutput stage, the details of how this current aects the driving capability dependson the type of load.

3.5.1 Resistive Loads

VSS

VSS

VDD VDD

vin Min

MloadMdiode

Ibiasvout

VSS

Rload

Ibias

Figure 36: A CS stage driving a resistive load.

For resistive loads the available current in the output stage together with thesize of the load imposes limits on the output swing, the manner in which thishappens depends on the topology of the output stage. A simple case is the CSstage shown in 36 where the current delivered by the PMOS current source at thetop sets a limit on the maximum swing in the positive direction since the outputcannot go higher than VCM + Ibias · Rload due to the current delivered to the loadbeing limited to Ibias for the case when the lower transistor turns o completely.The swing in the negative direction is usually less restricted since it is normallypossible for the NMOS at the bottom to turn on enough to sink all of the currentdelivered by the PMOS current source.

54


It should be noted that the minimum open-loop gain needed to maintain asuciently precise close-loop gain must also be taken into account since connectingsmall enough resistances to the output will cause the voltage gain obtained fromthe output stage to drop. Because the output stage buers all previous stages onlythe gain from the last stage in the chain will be aected by the load resistance,hence a general remedy to this problem is to attempt to obtain as much gain aspossible early on in the chain. In extreme cases (i.e. if very large resistive loadsare to be driven at high closed-loop gain precision) more stages may need to beadded.

In cases when resistive loads are to be driven and noise is critical the size ofthe load may also be important since large resistive loads (i.e. small resistors)produce less noise than small ones (i.e. large resistors). Since the ability of theop-amp to drive a large resistive load is dependent on there being enough currentavailable in the output stage overdesign in this regard is costly in terms of powerconsumption. When noise is important one should therefore opt for the smallestpermissible (from a noise perspective) load possible and design to op-amp suchthat it is just (with some margin) able to drive a load of this size.

3.5.2 Capacitive Loads (Slew Rate)

In the case when an op-amp is driving a capacitive load there is no need forthe amplier to constantly supply or draw current to maintain a given voltagelevel. Thus the only limits on the reachable voltage levels are those that mightbe imposed by transistor voltage drops and the issue of driving instead shifts to aquestion of how fast the amplier is capable of charging or discharging a load ofa given size.

Ibias,1

MN,+ MN,-

MP,+ MP,-

VDD

VSS

vin,+ vin,-

VDD

Mout

Ibias,2

VSS

VDD

Rcomp Ccomp

VSS

Cload

Figure 37: A voltage-follower driving a capacitive load.

Suppose that an op-amp is congured as a voltage follower and is made to drive

55


a purely capacitive load while being fed a square-wave input, as shown in Figure37. Each time the input shifts from its high state to its low state or vice versa thefeedback control of the op-amp is temporarily upset as it cannot instantly changeits output voltage to track the input one due to the need to charge the capacitor.Due to the high gain of the op-amp this will cause Mout to be either turned onfully or turned o fully. In the case when the load should be charged to VDD andMout is thus turned on fully the situation is similar to that when a digital inverteris to charge or discharge a load, with Mout temporarily going into its triode modeof operation. Unlike the situation with the inverter the load does not turn othough and hence the current available to charge the load is whatever currentMout can deliver (in the triode mode of operation this will be dependent on thevalue of VDD − Vout since Mout behaves like a resistor) minus the current drawnby the load. In the case when the output should instead be discharged Mout willturn o completely and the discharging will happen linearly since Mload draws aconstant current. The precise details of charging and discharging thus dier butin both cases the feedback loop has essentially been put out of commission andthe charging or discharging current is independent of the input voltage, the termslewing refers to the op-amp being in such a state of operation.7

The slew rate of the op-amp is normally dened as the fastest rate at whichthe output voltage changes for large input signals, i.e. as

SR =∂vout∂t

∣∣∣∣max

(27)

[9]. In the case described here including the maximum rate when charging througha triode-mode transistor would likely give us a gure that is too optimistic, hencewe only include the case when the load is being discharged yielding

SR =IbiasC

(28)

Since the slew rate is a measure of the ability of the op-amp to drive large loadsit is apparent that the bias current used in the output stage is the determiningfactor of the driving capability both in cases when resistive loads are driven andin cases where capacitive loads are driven.

Op-amps which are designed to drive capacitive loads only are sometimes alsoreferred to as Operational Transconductance Ampliers (OTAs). Which descrip-tion is more suitable is dependent on the driving capability of the amplier aswhether it will behave more like a a current source or a more like a voltage sourcedepends on how its gm compares to the output load and on the input frequency.For a large capacitive load compared to the gm the amplier will not produce

7We may alternatively limit this term to only refer to the state when the op-amp is chargingor discharging a load with a constant current and thus exclude the state when the load is beingcharged or discharged through a triode-mode transistor.

56


a large enough output current to quickly charge the load capacitance and hencethe amplier plus the load will start behaving like an integrator for large enoughinput voltages, i.e. increasing the input voltage will cause a larger output currentto charge the load. For smaller loads this eect only comes into play at higherfrequencies whereas at lower frequencies the system behaves like a voltage amp-lier. No xed line can be drawn between these two types of behaviour as whatone would count as being of either type would depend strongly on the desiredbehaviour and the demands imposed by the usage case.

3.6 Stability, Settling Time and Compensation

As op-amps are typically used in a feedback loop to control the amplier gainstability is an issue and the op-amp must therefore be designed to have a suitablephase margin. The phase margin of a system reects not only its stability but alsoits settling behaviour. A high phase margin indicates a heavily damped systemand will thus be indicative of relatively slow settling behaviour with little to noringing. A low phase margin on the other hand suggests that the system haslittle damping and will therefore exhibit quite rapid voltage movements but alsoquite a bit of ringing when settling. Generally, there will thus be some optimalphase margin that allows the system to settle as quickly as possible to withinsome specied deviation from the nal value (theoretically only achieved at timet → ∞). Thus, while stability is a non-negotiable requirement that must alwaysbe achieved in order for the design to be usefult at all, selecting a suitable phasemargin is more complicated than only avoiding instability and a higher value isnot necessarily better.

3.6.1 Selecting a Suitable Phase Margin

Dierent sources suggest dierent rules-of-thumb regarding what phase margin toaim for in an initial design, a commonly seen number is 60 but unfortunatelyone rarely encounters any motivations for why this particular value should beused. [7, p. 162] is one of the sources suggesting to aim for a 60 phase margin,here it is suggested that this corresponds to a Butterworth placement of the poles(assuming an idealised system that has only two poles). This in turn suggeststhat an op-amp designed for such a phase margin would have the relatively quicksettling behaviour of a Butterworth lter in the time domain which is likely to bethe primary reason for the suggestions to aim for this phase margin.

However, while 60 of phase margin might be a good target if nothing else isknown about the system there is no one-size-ts-all solution regarding the phasemargin. When attempting to nd a time response that is optimal in the sense ofminimising the settling time the allowed deviation from the nal value needs tobe taken into account, this can sometimes lead to optimal phase margins whichdeviate from the 60 proposed as a rule-of-thumb [1, lecture 13]. Analytically

57


nding an optimal phase margin in this manner can be rather tricky and henceone may be better of e.g. using an ideal model to nd a near-optimal value usingtrial and error with a simulator.

3.6.2 Basic Stability Behaviour of Op-Amps

Most op-amps use two stages and can therefore be modelled as two-pole systems.In reality there will usually be more poles due to various parasitic capacitancesand resistances but these will mostly be placed high enough in frequency to benegligible and so a two-pole model tends to work reasonably well.

Each pole will add a slope of −20dB/dec to the magnitude transfer functionand a phase shift that is −45 at the pole frequency and becomes −90 at approx-imately one decade above the pole frequency. If both poles in a two-pole systemwere to be placed at the same frequency then the magnitude would start fallingof by −40dB/oct starting at this frequency and the phase would reach −180 adecade above it. Hence to achieve even a modicum of stability the total gain ofthe system would need to be kept below 40dB and for values approaching this gainthe phase margin would be low enough to make the system practically unusuabledue to extreme amounts of ringing (for low enough phase-margins one can obtainsystems which are theoretically stable but exhibit settling times of several years,obviously such systems are not useful for most practical purposes).

In an op-amp it is therefore necessary to separate the poles by a wide enoughmargin that the higher-frequeny pole does not add too much phase shift beforethe total magnitude slope brings the gain down to unity. If this is done the 3dB-bandwidth of the system will be determined by the lower-frequency pole (i.e. weget f3dB = fp,lower) which we then refer to as the dominant pole. Assume that weregard a phase margin of 45 as an absolute minimum, then the non-dominant polemust be placed no lower than the unity gain frequency f0dB. With the poles placedin such a manner the non-dominant pole will only contribute to the magnitudeslope at frequencies above f0dB and hence the 0dB-bandwidth (i.e. the unity-gain bandwidth) will be determined by the dominant pole alone. With a slope of−20dB/dec and a total DC gain (in dB) of GDC it takes GDC/20 decades for thegain to fall o to 0. Hence f0dB must be placed at

f0dB = 10GDC/20 · f3dB (29)

When working with voltage decibels we have ADC = 10GDC/20 where ADC is thelinear-scale gain expressed in (V/V). Under the previously made assumption thetwo poles are at fp,dominant = f3dB and fp,non-dominant = f0dB Thus to achieve aphase margin of at least 45 we need

fp,non-dominantfp,dominant

≥ ADC (30)

58


The phase shift (in degrees) at a given frequency f due to a pole placed at fp equals− arctan( f

fp) · 360

2π, a phase shift of −60 is thus obtained for f = tan(60) · fp ≈

1.73fp. As was previously mentioned a phase shift of −45 is obtained preciselyat f = fp, hence to obtain a 60 phase margin the separation of the poles must beapproximately twice as large as what is needed to obtain one of 45 and thereforewe should in most case aim for a pole separation of at least

fp,non-dominantfp,dominant

≥ 2ADC (31)

This result is also provided in [7, p. 162] but is there presented without anyderivation.

It is interesting to note that in the case of a 1-pole system one obtains thesame expression for the GBW-product (Gain-Bandwidth-product) as for the 0dB-bandwidth. The GBW-product may be expressed

GBW = ADC · f3dB = 10GDC/20 · f3dB (32)

Since a well-compensated op-amp that has at least 45 of phase margin approx-imates a 1-pole system we can thus approximate the GBW-product of such anop-amp by its f0dB. This result is very useful for practical design because it isgenerally easier to predict and measure the 0dB bandwidth than the 3dB one.If the closed-loop gain and bandwidth needed in an amplier is known then thisresult provides an easy way of estimating the needed f0dB of the op-amp used torealise the desired amplier. If we for instance know that we need an amplierwith a closed-loop gain of 5 and a 3dB bandwidth of 1MHz then it is easily cal-culated that the needed GBW-product is 5 · 1MHz = 5MHz and thus we shouldaim for an approximate f0dB of at least 5MHz.

3.6.3 Compensation of Two-Stage Op-Amps

From the preceeding discussion about pole placement and phase margin it is ob-vious that a very large separation of the poles will usually be needed to obtainan acceptable phase margin. Even for a (in the context of op-amps) relativelymodest open-loop gain of 60dB the non-dominant pole will need to be placed at2 · 1060/20 = 2000 times the frequency of the dominant pole to achieve a 60 phasemargin. Such a large separation is hardly realistic to achieve using only transistorsizing and bias current settings, hence we usually need to employ some compens-ation scheme to at the very least limit the bandwidth of the stage associated withthe dominant pole.

The simplest such scheme possible is to simply add some extra capacitancein parallel with the load to limit the bandwidth of the amplier, this approachis illustrated in Figure 38. While this approach can indeed be used to limit thebandwidth of the stage associated with the dominant pole it still usually requires

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vin

Ccomp

vout

Zload,1 Zload,2

gm,1 gm,2

Figure 38: Using an extra capacitor in parallel with the load to to limit the bandwidthof a transconductor, adapted from a gure in [7, p. 166].

the other stage to be designed for a very high bandwidth. If an op-amp is requiredto have a gain of 60dB and a GBW-product of 5MHz (hardly any ambitious gures)this would imply designing the op-amp stage associated with the non-dominantpole for a 0dB-bandwidth of 10GHz. While this might still be within the realmof the possible it would likely force us to use undesirably large biasing currents,moreover the bandwidth target would most likely become highly unrealistic ifa more ambitious GBW-product is aimed for. A further problem is that thistechnique may call for an unrealistically large capacitor to be used.

The latter problem can often be alleviated to some degree if a capacitive load isto be driven. When parallel compensation is used any stage may be choosen to beassociated with the dominant pole, if the outer stage is choosen for this then thecapacitance of the load can be used as part of the compensation capacitor in orderto reduce the amount of extra capacitance which needs to be added. Unfortunatelythis still does not address the problems with high GBW-products leading to largebandwidth demands for the non-dominant stage, hence parallel compensation isunlikely to be of use except for situations where the required GBW-product is notvery high.

vin

Zload,1 Zload,2

Ccomp

voutgm,1 gm,2

Figure 39: Using a Miller-capacitor in parallel with the output stage transconductor tolimit the bandwidth of the input stage, adapted from a gure in [7, p. 170].

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In most cases Miller-compensation, as illustrated in Figure 39 is a better choice.In this scheme the compensating capacitor is connected in parallel with the amp-lier, since the amplier is inverting the capacitor is then subject to the Millereect as described in for example [12, pp. 166-168] and the capacitance actuallyseen by the input stage. The capacitor also functions as a feedback path for theoutput stage and thereby extends its bandwidth [7, p. 171], note that this feedbackpath is open-circuited at low frequencies due to the nite size of the capacitor andhence the DC gain of the output stage remains unaected. The total eect of thiscapacitor is thus to lower the bandwidth of the input stage while simultaneouslyraising that of the output stage. This eect is commonly referred to as pole split-ting (see for instance [12]) and is very benecial for the ability of the op-amp toachieve an acceptable phase margin even when a high GBW-product is required.

There are some issues that need to be considered when Miller-compensation isused. In the case when parallel compensation is employed one may freely choosewhich stage should be associated with the dominant pole, this is no longer possiblewhen Miller-compensation is used. In this case the dominant pole must always beassociated with the input stage since the compensation will otherwise not workproperly, this can sometimes be problematic since the load presented to the outputstage might make it hard to achieve a high enough bandwidth for this stage. Aswe shall see in Section 3.8.5 this becomes particularly problematic when trying toconstruct op-amps with low input-referred thermal noise.

A second issue is the feedforward path introduced by the Miller capacitor.Applying a voltage vin,s2 at the input of the output stage will cause the outputstage transconductor to draw a current iout = −vin,s2gm,s2 but will also cause afrequency-dependent feedforward current iff (jω) = jωCcomp(vin,s2 − vout). Forsome positive frequency these currents will be equal in magnitude and thus atthis frequency all current drawn by the transonductor will be supplied throughthe compensation capacitor with the eect that no current can ow through theload at this frequency. This produces a right half-plane (since it occurs for apositive frequency) zero, such a zero will add even more negative phase shift andfurther cause a positive slope contribution which leads to a degradation of thephase margin [12, p. 364]. The usual way to solve this problem is to add a resistorof size R in series with the compensation capacitor, doing so causes the zero to beplaced at

ωz ≈1

Ccomp(1/gm,s2 −Rcomp)(33)

[12, p. 365]. Hence the zero can be moved to innity by setting Rcomp = 1/gm,s2,it is also possible to use a larger value than this to move the zero into the lefthalf-plane where it can be used to cancel one of the poles [12, p. 365]. Whileusing the zero to cancel a pole can yield large benets in terms of increased phasemargin doing so is risky since it relies on accurately placing the zero in relationto the pole which is dicult to do in the face of such things as process variation

61


and varying loads (it is of course still an option however and some methods fortrying to place the zero accurately in relation to the pole are presented in [12,pp. 365-367]). In practice sizing the resistor at Rcomp = 1/gm,s2 seems to providea good starting point from which the size can be adjusted using trial-and-errorif it is important to nd a more optimal value (if this is done it should howeverbe remembered that absolute resistor values tend not to be very accurate in ICprocesses, hence it is important that one does not rely too much on an accurateresistor value to achieve an acceptable phase margin).

When using a nulling resistor this should theoretically be sized at Rcomp =1/gm,out where gm,out is the transconductance of the output stage (p. 175 inHuijsing). In practice this does not always seem to yield the best possible phasemargin and one may therefore want to treat this value as an initial guess and thenproceed using e.g. sweeps in the simulator to nd a better one.

A further issue that needs to be taken into account when using Miller compens-ation is that it is not possible to split the pole associated with the output stageto a position beyond the pre-compensation 0dB-bandwidth of the output stagesince beyond this point there is simply no gain to be had from the output stage [7,p. 172]. Beyond this point increasing the size of the compensation capacitor willsimply lower the frequency of the internal pole without increasing the frequency ofthe output pole. Doing so is inecient from a power- and area-perspective sincethe same eect could just as well be achieved by decreasing the biasing current ofthe input stage which will decrease the power consumption and additionally notincrease the required are by calling for the addition of more capacitance.

In a similar vein it is shown in [6, p. 641] that in a Miller-compensated op-ampthe output pole will be approximated by

p2 ≈gm,s2Ccomp

C1C2 + Ccomp(C1 + C2)(34)

where C1 and C2 are the total capacitances seen at the output nodes of the rstand second op-amp stages. From this it can be seen that increasing the size of thecompensation capacitor will at most (and this only for an innitely large value ofCcomp) move the output pole to

p2,max ≈gm,s2

C1 + C2

(35)

This is very similar to the previously mentioned result presented in [7] and infact shows that this previous result is not quite as strict as it could be. The0dB-bandwidth (before compensation is added) of the output stage in radianswill be gm,s2/C2 where C2. The dierence here is because the result from [7]presents a maximum theoretical limit only due to characteristics of the outputstage whereas [6] presents a results that also takes into account the fact thatadding a very large Ccomp will cause an eective shortcut to be presented across

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the output amplier which will have the eect of exposing the output node tothe capacitance added by C1. One more thing that should be evident from this isthat using too large a compensation capacitor is not a good idea since making itlarge enough will eventually cause the resulting shortcut path to take the outputstage out of commission at all frequencies of interest, at this point we might aswell dispense with the output stage alltogether.

It ought to be noted that while compensation often needs to be used to helpachieve stable operation the rst course of action should generally be to bring thepoles apart by a reasonable distance through adjusting the gm:s of the amplierstages. Especially when using parallel compensation (see below for more detailson this compensation scheme) it is at least in theory possible to start with a high-bandwidth stage and reduce its bandwidth to any desired value simply by addinga large enough compensation capacitor. However, excessive amplier bandwidthcarries a cost in terms of the larger transistor area and biasing currents needed toincrease the gm:s of the transistors. In addition compensating for a larger thanneeded bandwidth by increasing the compensation capacitance is also wasteful interms of capacitor area. Hence failing to reduce the gm of the stage associated withthe dominant pole prior to applying compensation is likely to produce a design thatis unnecessarily area- and power-hungry. When designing for low thermal noise itmay even so be necessary to use larger gm:s and use the compensation capacitorto reduce the bandwidth. Since the concepts of gm and resistance are very similar(to the point that a resistor with one end grounded can be accurately describedas a voltage-to-current converter with a certain gm) this can be thought of asbeing roughly analagous to the way in which achieving low noise in RC-circuitsultimately requires one to use large capacitors.

3.7 Common-Mode Feedback (CMFB)

In IC design it is common to primarily use fully dierential op-amps due theirbetter rejection of various forms of noise and their increased dynamic range. Whensingle-ended op-amps are used the DC level of the output is set by biasing the op-amp to a suitable operating point, when their fully dierential cousins are used theDC points of the outputs have no such natural levels since the signal is present onlyas the dierence between the voltages of the two outputs and their absolute levelsare therefore unimportant in the ideal case. In a practical amplier the supply railswill impose a limit on the swing of the outputs and hence the largest possible signalswing is obtained when the DC levels at the outputs are at the point halfway inbetween the supply rails. There is thus need of a mechanism to establish a suitableCM voltage VCM at the outputs around which the dierential signal componentis allowed to vary. For this reason fully dierential op-amps normally include aCMFB (Common-Mode Feedback) network that uses a feedback mechanism toestablish such an operating point. There are essentially three tasks which mustbe performed by the CMFB network:

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1. A sensing network must sense the CM voltage at the output of the OP, inpractice this means that some network should sense the mean output voltageof the two outputs.

2. An error amplier must compare the sensed CM level to a reference voltageand amplify the error.

3. The output voltage from the error amplier must be fed back to the OP insuch a way as to cause the output CM level to be pulled towards the valueof the reference voltage.

This introduces a number of new issues to the design process that are not presentwhen using single-ended ampliers. To start with, the sensing of the output CMvoltage should ideally be done in such a way as to present no additional load atthe output. In practice this can obviously not be achieved and thus some way tominimise the eect of the sensing network needs to be found. This is particularlyimportant for op-amp architecture such as the folded-cascode one which depend ona high output impedance to achieve their gain. In such cases the sensing networkobviously cannot be allowed to present a large load to the op-amp output as thiswould signicantly degrade its performance. A number of ways to perform thesensing are presented in separate sections below.

The error voltage that is fed back must obviously be connected to some pointin the circuit, this point will usually be a transistor whose gate is connected to theerror voltage and whose output current aects the output common-mode voltagein such a way as to close the feedback loop. Since the CMFB loop is a feedbacksystem it is the subject to the usual problems regarding stability and settling timethat aect all such systems. For this reason the choice of where in the structure toplace the return points is of some importance, in short it is generally advantageousfor stability to place the return points close to the amplier output since this willmean that there are less poles in the CMFB loop. On the other hand proper CMlevels need to be established in all voltage-output stages so if the return pointsof the CMFB network is put in the output stage additional CMFB networks mayneed to be added to obtain well-dened CM level in the previous stages.

The options available for including the return point are highly dependent onthe overall op-amp architecture used. Therefore the more specic details aboutthe inclusion and sizing of return point transistors will be saved for Section 3.8where more details on specic architectures will be presented.

3.7.1 Error Amplier

The error amplier employed in the CMFB network typically consists of a dier-ential pair with diode loads as shown in Figure 40. While diode loads have ratherlow impedances and are thus suboptimal in terms of the gain obtainable fromthe amplier they allow for more robust designs. As we shall see more of later

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vCM,out

VDD

MP,2MP,1

Ibias

MN,2MN,1

VSS VSS

VCM,ref

vCM,error

Figure 40: Typical error amplier used in a CMFB network. The PMOS-input versionshown here should be used if the return point transistors are of the NMOS type, if theseare instead of the PMOS type the NMOS-input equivalent should be used instead.

the return point transistors are typically inserted by connecting the gate of somebiasing transistor to the error voltage rather than to the control voltage producedby the diode in a current mirror. To obtain a robust design the transistors shouldthen as a rule-of-thumb be sized such that they under quiescent conditions (i.e.when the currents through the two brances of the error amplier are equal) sinkor source as much current as other, xed bias-current parts of the main circuitdemands them to. By using diode-connected loads in the error amplier this iseasily accomplished by noting that the load in the output branch of the error amp-lier and the return transistor essentially form a current mirror. Under quiescentconditions (i.e. when vCM,out = VCM,ref half of the total bias current fed to theerror amplier will be carried by the output branch. Knowing this one can easilyset the current sinked our sourced by the return transistors by adjusting either orboth of the mirroring ratio of this current mirror and the size of the bias currentfed to the error amplier. This makes it possible to set up formulas for the sizingwhich can benecial as using such a formula to set sizes in the simulator allowsfor automatically changing sizes and thus facilitates such things as sweeping otherparameters to nd optimal values for them. In Section 3.8.3 some formulas of thistype will be presented.

Since one can use the mirroring ratio between the return point transistorsand the load transistors of the CMFB circuit to determine how much current theformer will sink it is not strictly necessary to feed the same amount of bias currentto the CMFB network as to the input transistors. In practice doing so seems tobe a good practice however as it generally seems to yield better results when thecircuit is faced with varying loads, for instance when using the OP in a switched-capacitor circuit where the operating conditions can change drastically depending

65


on the active clock phase. When increasing or decreasing the bias current fed tothe CMFB network some attention must be paid to the sizes of the dierentialinput pair and of the load transistors it further appears to be good practice toadjust the size of these so that it is roughly proportional to the CMFB bias currentsince these transistors might otherwise be too small to handle this bias current.

The inclusion of the error amplier of course adds one pole to the CMFBloop. For this reason the CMFB loop in an op-amp where the CMFB returnpoints are placed in the input stage will have one more pole than the main path,making obtaining an acceptable phase margin in the CMFB loop into an even morechallenging problem than what it is for the main path. This is made particularlyproblematic by the fact that one then has several paths which partially sharethe same ampliers, hence adjusting the pole placement in one of these paths toenable the addition of an eective compensation network may cause one to obtainan unfortunate order of pole placements in the other path which in turn makes theCMFB network trickier than the main path. This provides us with another reasonto use diode loads in the error amplier, while their low gain may be problematicfrom the point of view of achieving high precision in the CMFB loop it will at thesame time be advantageous from the point of view of achieving a stable loop.

3.7.2 Resistive Sensing

C1 R1

C2

vCM,out

vout,+

vout,-

R2

Figure 41: Resistive CMFB sensing.

Figure 41 shows how the schematic of a resistive sensing scheme. As is evidentthis scheme is very simple and simply involves two resistors being used to form themean of the voltage at the two op-amp outputs. The capacitors are not strictlynecessary but generally needs to be included in practice to improve stability. Whilesimple, this type of sensing scheme may call for the use of very large resistors assmall ones will present a large load to the op-amp outputs. This can cause thisscheme to become vary area-hungry and furthermore could potentially cause itto add quite a bit of thermal noise from the resistors, this may however be at

66


least somewhat mitigated by the fact that the noise is added at the output of theop-amp.

3.7.3 Buered Resistive Sensing

C1

R1

C2

vCM,out

vout,-

R2

vout,+

Ibias

M1

Ibias

M2

Figure 42: Buered resistive CMFB sensing (gure adapted from one found in [9, p.290]).

As can be seen from Figure 42 this scheme essentially employs the same prin-ciple as the resistive sensing one with the dierence that common-drain stageshave been added between the op-amp outputs and the transistors. This buersthe outputs from the resistors and thus makes it possible to use much smallerresistors which reduces the problems with area and noise . On the other hand thebuering introduces a level shift by the Vgs of the buering transistors. This levelshift can be compensated for by adding a similar buer (with equal sizing and biascurrent) at the VCM,ref side of the error amplier but this level shift still has theeect of reducing the available swing since low enough signal levels at the buerinputs will cause the transistors to go out of saturation.

3.7.4 Transistor Sensing

The transistor sensing CMFB networks shown in 43 employs current summing forregulating the CM voltage and merges the sensing into the error amplier suchthat the network shown here performs both of these functions. Two dierentialpairs referenced against the CM reference voltage are placed in parallel so thatthey deliver their output currents to the same loads. If the negative and positiveoutput voltages are shifted by the same amount but in opposite directions thetotal current delivered to each branch will remain the same (provided that notransistors go out of saturation) since such a change will cause an increase incurrent delivered to one branch by one of the dierential pairs to be matched bythe decrease in current delivered by the other pair. In the case of a change inthe output CM voltage the change in the current delivered will be in the same

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VDD

MP,2MP,1

Ibias

MN,2MN,1

VSS VSS

VCM,ref

VDD

MP,4MP,3

Ibias

vCM,error

vout,-vout,+

Figure 43: Transistor CMFB sensing (gure adapted from one found in [9, p. 288]).

direction for both of the pairs, hence such a change will cause the output voltagesof the circuit to change.

Sizing is essentially the same as for the resistive sensing scheme except thatusing two biasing transistor means that twice the bias current fed to either one ofthese is available. This should be taken into account when choosing the mirroringratio between the CMFB network loads and the return transistors, i.e. if themirroring ratio of the CMFB network biasing transistors is kept at the same valueas in the resistive scheme the CMFB-loads-to-return-transistor mirroring ratioshould be halved.

Like the buered resistive sensing scheme this technique also reduces the outputswing.

3.7.5 Switched-Capacitor CMFB

Like the transistor sensing scheme presented previously, the switched-capacitorCMFB scheme shown in 44 also combines all necessary functions in a single net-work. Unlike the previously presented schemes (and in spite of what is stated inthe list of tasks included in the introductory presentation of CMFB networks) itdoes not include any amplier.

Conceptually one can understand the function of the network by imaginingremoving all parts of the network except the two CC capacitors and connectingvCM,error to the gate(s) of some transistor(s) such that the path through the ca-pacitors forms a negative feedback loop. If this was to be done any change in theaverage level of the two outputs would be resisted by the feedback loop and theoutput CM level would thus be regulated. However there would be little control

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IbiasVCM,ref

vCM,error

vout,+

MN,1

VSS

VDD

Vbias Vbias

CS CC

VCM,ref

Vbias

CSCC

φ1

φ1

φ2

φ2

φ1

φ1

φ2

φ2

vout,-

Figure 44: Switched-capacitor CMFB sensing (gure adapted from one found in [9, p.291]). The version shown here should be used if the CMFB return point is implementedby an NMOS transistor, if a PMOS transistor is used the circuit would need to beadapted to reect this.

over which voltage the CM level would be regulated to and in addition the lack ofany reset mechanism for the capacitors would mean that large DC voltages couldpotentially be built up on them. To alleviate these problems the switches and theCS capacitors are added, in phase 1 the CS transistors are charged to Vbias andin phase 2 their charge is partially transferred to the CC capacitors. It shouldbe noted that in phase 2 all capacitors are oating, hence In the absence of anyother changes this would after some time cause the CC capacitors to be chargedto Vbias − VCM,ref , since these capacitors are always oating they will not set thevCM,error node to any absolute voltage but rather act as voltage sources connectedbetween the outputs and vCM,error. This allows one to choose which voltage shouldbe presented at vCM,error under quiescent conditions (i.e. when) by simply select-ing an appropriate Vbias. By thinking of the diode-connected transistor generatingVbias and the CMFB return transistor as a current mirror one can thus set thecurrent sinked our sourced by the latter in a manner similar to the one describedin Section 3.7.1. The explanation given here closely follows one given in [1, lecture15].

Using a switched-capacitor CMFB network can save quite a bit of currentconsumption as the bias current used for the dierential pair in a continuous-modeerror amplier can make up a signicant part of the total current consumption ofthe op-amp. They also allow the full output swing of the OP to be used. Howeverdue to the time-discrete nature of their operation such CMFB networks tend toadd spiking to the output voltage, thus they are mainly useful in op-amps meantto be used in the implementation of switched-capacitor circuits which add similarartifacts anyway and where the output is thus usually taken to be valid only duringrestricted time intervals. They could potentially also be of use when chopping isapplied since the lter used to remove chopping artifacts should also remove thespiking if the CMFB network is clocked at the same (or a higher) speed as thechoppers.

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Simulations involving switched-capacitor CMFB networks can be rather di-cult to perform properly. In particular it is problematic to obtain the type of datanormally used for estimating CMFB stability from the simulator. Additionallysimulation times can grow very long since the CMFB network needs some set-tling time and since the switching can force the simulator to reduce its timestep.The possible savings in current consumption must therefore be weighed againstthe possible problems that can result from using an SC network for this task asa well-tested circuit that is known to be robust but is also more power-hungrymight be preferable to a less power-hungry one where the robustness has not beenpossible to test to the same degree.

3.8 Design Heuristics

In this section an attempt will be made to present a reasonably well-orderedmethod for the general design of op-amps, from the choice of architecture to initialsizing. Due to the large number of both independent (e.g. choice of architecture orsizing of transistors) and dependent (e.g. performance measures such as bandwidthor power consumption) parameters involved in the design of op-amps it is unlikelythat something like a denitive method for this can ever be found, particularlyconsidering that dierent situations may lead to very dierent sets of priorities.However, having a bit of a system is likely to be better than having none as itcan at the very least provide one with a starting point that may then be adaptedaccording to the situation at hand.

The heuristics presented here are based on experience obtained during thecourse of the thesis work. Obviously the amount of experience that can be gainedfrom roughly half a year's worth of work is rather limited, hence the heuristicspresented here should be viewed as tentative as it is quite possible that the authormight reject any or all of them after gaining more experience.

3.8.1 Choice of Architecture

The choice of an architecture is the most fundamental decision to be made whendesigning an op-amp. Due to the large number of possible architectures and theeven larger number of possible usage scenarios for an op-amp there is no suchthing as an architecture which is optimal in all situations, rather the choice oughtto depend on the task at hand.

A basic question to be considered is whether the op-amp is to be designed forgeneral-purpose use or for a specic application where the important parametersare known beforehand. In the former case the op-amp must be designed to bea compromise between several dierent performance measures and thus there islittle room for optimising the amplier to do well at a particular task. In the lattercase such optimisation can be made and before the actual design begins attentionshould therefore be paid to how the requirements imposed by the task may be

70


Folded CascodeClass-AB

Output FoldedCascode

GA-GA

Gain + ++

Swing − ++ +

Noise − − +

LoadFlexibility

− ++ +

DesignComplexity

+ −

Table 2: Design guide for choosing between the three op-amp architectures described inthe present text. Load exibility refers to the op-amp's capability to drive resistive aswell as capacitive loads as certain architectures can only drive the latter load type.

translated into requirements on the op-amp. The following text generally assumesthat an application-specic op-amp is to be designed.

A further consideration that ought to be made when considering the architec-ture is how it inuences the complexity of the design task and thus in turn thedesign time. Given the large number of dierent architectures which can be foundand the complexity of many of them a single designer can hardly be familiar withall of them. Obviously opting for an architecture that the designer is well acquain-ted with is likely to produce considerable savings in design time. Furthermore it isquite possible that a designer could produce more optimal results using a familiararchitecture than using one which might otherwise be more suited for the task butof which the designer has little knowledge.

Type of Load: In the case of application-specic op-amps the type of load thatis to be driven determines which architectures are viable. In IC design theload will often be capacitive in nature, in such cases it is possible to usearchitectures such as the telescopic or folded-cascode ones that rely on ahigh output impedance to achieve large voltage gain. If resistive loads needto be driven (which must usually be assumed if a general-purpose op-amp isto be designed) then such architectures generally cannot be used since theloading would lower the gain of the op-amp too much.

Swing: Swing is another major factor in the decision of architecture. In par-ticular, since cascodes always takes up some of the voltage headroom any

71


architectures involving cascodes should be avoided if rail-to-rail swing is de-sired. The telescopic architecture is particularly problematic in this case dueto the stacked cascodes which give rise to very strict limitations on swing,this architecture should therefore generally be avoided although it might stillbe an option in some special cases where it is known in advance that theneeded output swing is very small.

Distribution of Gain: Most op-amps employ at least two amplication stagesand hence the distribution of the total gain between the stages may needto be given some consideration. In a two-stage op-amp the input stage willhave a well-known load (the output stage) that in a CMOS process will becapacitive in nature. The output stage on the other hand can be presentedwith a range of dierent loads which may additionally be resistive in nature.For these reasons it is generally best to realise as much of the gain as possiblein the input stage when working with 2-stage op-amps as the high gain ofthe amplier might otherwise be ruined when it is used in a feedback loop.Having a large gain early on in the chain is also benecial for noise sincemore gain early on makes the contributions from later stages less signicant.

3.8.2 Creating a Schematic and Performing Initial Sizing

While the precise details of creating the initial schematic and sizing the transistorsare obviously very dependent on the particular architecture to be used there aresome general guidelines that can be used to make the initial schematic constructionand sizing easier. At this stage it appears to be prudent to attempt to create agood starting point that can later on be resized to conform to various performancerequirement proles. Hence what is described here aims at trying to produce sucha starting point rather than at directly trying to size for the actual performancespecication.

Since op-amps are made out of a number of simpler structures such as one-transistor ampliers and dierential pairs it is possible to construct them in astep-by-step fashion. In principle it is possible to use a single dierential pairas an op-amp (although not a very good one as it will generally have to littlegain to yield much in the way of precision), hence one may start by constructing asingle dierential pair. By adding a testbench containing all necessary surroundingcircuitry such as signal sources and a feedback path it is possible to test this dier-ential pair as though it was an op-amp.8 If a single-ended op-amp is constructedthe dierential pair should be constructed with the familiar current-mirror loadused in single-ended op-amp structures, in this case the testbench can be used toensure that a correct DC operating point is obtained at the op-amp output.

8In a hierarchical schematic capture software such as Cadence it may be advantageous tocreate a separate testbench containing such things as signal sources and feedback circuitry andcreate the op-amp in a component with a symbol that can then be added to this testbench.

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In the case when a fully dierential op-amp is constructed the DC operatingpoint must already at this stage be established using a CMFB loop. To avoidthe possible complications due to adding a proper CMFB network one may addan idealised one consisting of two large resistors for sensing the common modevoltage (it should be noted that a capacitor may need to be added in parallelwith each resistor to achieve stability) followed by an ideal amplier amplifyingthe dierence between the sensed voltage and a reference voltage.9 When only asingle stage is used the only suitable place to connect the error voltage obtained atthe output of this amplier is to the gates of the load transistors. The total loopamplication must obviously have the correct sign but since it is simple to changethe sign when an ideal amplier is used and since there are only two possibilites itmay be more time-ecient to use an initial guess and check the correctness usingthe simulator than to spend too much time on guring it out in a more formalmanner. It should be noted that ideal ampliers can cause some problems withsimulation because they can be made to behave in ways that a more realistic modelcould not. Such problems can often be solved by making sure that the behaviourof the ideal model does not diverge too much from a realistic manner of behaviour,e.g. by keeping the gain low (from experience, a gain around 100 seems to providea good starting point) and by possibly adding an output pole (using a resistor anda capacitor) to limit the bandwidth of the amplier.

Once the input stage has been conrmed to be working properly one cancontinue the process by adding further stages if a multi-stage op-amp is to beconstructed or by adding such things as cascodes in case a telescopic or folded-cascode op-amp is to be constructed. As a further note it can be helpful to at rstadd simplied cascode stacks using ideal current-source loads in the case when afolded-cascode op-amp is to be constructed. In this way one can save the problemof generating proper bias voltages for the cascode stack loads until a later step.To avoid the need to start over from the beginning it may also be helpful to savecopies of each step so that it is easy to back-track in case something turns out notto work.

Each time a new step or feature is added it will obviously be necessary to makesome decisions regarding sizing. While it would be hard to describe any type ofsizing as being neutral it is generally desirable for designs to consume as little areaas possible, in addition small transistors have less intrinsic capacitance and canthus be used at higher frequencies compared to larger ones. Thus a reasonablestrategy that one may adopt for initial sizing is to make all transistors as small aspossible.

As stages are added some decisions must also be made regarding the size ofbias currents. The previously mentioned concept of V ∗ can be used to provide astarting point by setting the currents such that all transistors have a V ∗ close to the

9In Cadence an ideal amplier can be constructed using the vcvs component found in theanalogLib library.

73


optimum (in terms of the trado between transit frequency and gm/Id) for theirlength. If the optimal V ∗-points for the technology have not been examined settingV ∗ to 200mV should generally yield a good compromise [1]. Taken together withminimum size transistors this will ensure that the initial starting point that onelater uses when sizing to achieve acceptable performance parameters is economicalin terms of area and power consumption (the latter since the optimal V ∗ yields agood tradeo between power consumption and bandwidth).

The sizing of transistors and currents ought to be done in such a way thatthe eventual starting point that is produced has an acceptable phase margin, fora general starting point a value of 60 is reasonable to aim at. In the case of atwo-stage op-amp this will likely make it necessary to increase the bandwidth ofthe output stage which - if one is aiming to keep a constant V ∗ - implies increasingboth the transistor size and current.

3.8.3 Folded-Cascode Op-Amps

VDD

Ms1,-Ms1,+

Ibias,s1

MCMFB,return,-

VSS

vin,+

MN-cascode,-

Ms1,bias

Ms2,bias,-

MP-cascode,-

VDD

vCM,error

Vbias,N2

Vbias,P2

Vbias,P1

vout,+

Ibias,stack

Vbias,P1

vin,-

MCMFB,return,+

VSS

MN-cascode,+

Ms2,bias,+

MP-cascode,+

VDD

vCM,error

Vbias,N2

Vbias,P2

Vbias,P1

vout,-

Ibias,stack

Figure 45: Schematic of a typical folded-cascode op-amp with PMOS input transistors.

The schematic for a typical folded-cascode op-amp using PMOS input tran-sistors is shown in Figure 45. Neither the generation of suitable bias voltages northe CMFB network are shown but the points where these would be connectedare indicated by the node names. Vbias,P1 would typically be generated using acurrent mirror, Vbias,P2 and Vbias,N2 could also be generated in this manner but are

74


more easily generated using gain-boosting transistors (descriptions of how suchtransistors are employed can be found in e.g. [12, pp. 309-313]) . In order tomake it possible to distinguish which side a particular transistor has been placedon the name of all transistors has either + or − appended at the end, the formerfor transistors which are placed at the same side as the positive input and thelatter for transistors which are placed at the side of the negative input.

Sizing: Most applications impose a requirement on the minimum bandwidththat the op-amp must achieve. Since bandwidth and power consumption are in-timately linked one generally would not want to use more bandwidth than neces-sary (with the exception of providing a bit of margin to ensure that the bandwidthstays within acceptable limits in the face of variations due to process imperfec-tions, temperature etc.), hence a good starting point for the sizing is to make theadjustments necessary to achieve the necessary bandwidth.

In a folded-cascode op-amp most transistors act as current-copying devicesrather than as voltage-to-current converters, thus the only gm involved in settingthe 0dB-bandwidth is that of the input transistors10 giving us

f0dB =gm,s1

2πCload(36)

This simplies the setting of the bandwidth considerably and can hence be verybenecial in terms of design time, making folded-cascode op-amps into a goodchoice of architecture wherever design time is an important factor.

The load is generally determined by the usage scenario, hence it is apparentfrom (36) that the intermediate design parameter available to set the bandwidthis gm,s1 which in turn means that one can adjust the bandwidht by adjusting theW/L ratio and/or the bias current of the input stage. If one aims to keep thetransistors at a constant V ∗ this can be done by simultaneously adjusting boththe W/L ratio and the bias current by the same factor. It is also apparent from(36) that the worst-case bandwidth occurs for the largest possible load, hence ifthe load might vary then gm,s1 should be set so that the minimum bandwidth(with some margin) is achieved at the largest possible load. As a side note, ahigher bandwidth op-amp will generally have more problems with stability so inthe case with a varying load it is important to examine stability for the smallestload.

Once the bandwidth is set one should examine the DC gain of the amplier. Ifit is not high enough there are two basic ways of increasing it without adding anyextra transistors: increasing the length of the cascodes and decreasing the bias

10This is a somewhat simplied view of what is taking place in a folded-cascode amplier. Infact cascode stages do have bandwidth limitations but their bandwidth tend to be much higherthan that of common-source amplier stages and thus generally will not be involved in settingthe bandwidth. Their bandwidth may however still need to be considered for the purpose ofachieving stability.

75


current of the eintire cascode stack. As this is done the eects on the phase of theamplier should be monitored to ensure that the phase margin does not becomeunacceptable. If one cannot achieve enough gain in this way impedance boostingtransistors may be added to the cascodes. This will cost some extra current sincethe boosting transistors need to be biased, on the other hand there will no longer beany need to use some diode arrangment to generate bias voltages for the cascodesand thus the total extra current cost is likely to be modest. The lazy designerwill thus most likely already have added boosting transistors in order to simplifythe task of generating these bias voltages. If boost transistors are added then thegain increases by the voltage gain of these transistors, hence the gain may now beincreased further by increasing the length of these transistors.

In cases where swing is an important factor the folded-cascode architectureshould usually be avoided. Even so, it ought to be noted that it is possible toincrease the swing somewhat by increasing the W/L-ratio of the of the cascodesand - if present - of the boosting transistors. Rearranging Equation (6) gives us

Vov =gm

µnCox(W/L)(37)

from which it is apparent that for a constant Id increasing W/L will cause Vov todecrease, thus enabling a larger swing. Due to the close analogy between Vov andV ∗ this will also change V ∗ and will thus to move the aected transistors away fromtheir power-to-transit-frequency optimal region of operation. This should also beapparent if one referers to Equation (7b) where it can be seen that changing theW/L will cause the gm to change, without a corresponding change in Id this willobviously change the gm/Id of the transistor.

In order to provide an abbreviated outline intended to serve as a rough guidefor systematic design, the above points may be briey summed up as follows:

1. Initially size all transistors at the minimum possible size that is compatiblewith achieving an acceptable phase margin. Set the bias currents such thatthe V ∗ of each transistors is approximatly at the point which provides thebest trade-o between transit frequency and gm/Id (if this value has notbeen examined, aim for a V ∗ of roughly 200mV).

2. Assuming that the target 0dB-bandwidth and the worst-case load capacit-ance are known, adjust the input stage gm to achieve the desired bandwidthunder worst-case load conditions. Refering to Equation (7b), use simultan-eous adjustments of W/L and the bias current by an equal factor to changethe gm while leaving V ∗ more or less unchanged.

3. Increase the length of the cascode-stack transistors and/or decrease the biascurrent of the cascode-stack to increase the gain if needed. If not enoughgain can be achieved in this way add boosting transistors to the cascodes, ifthis is done the increasing their length and/or decreasing their bias currents

76


will also improve the gain. Monitor the phase response as this is done toensure that the phase margin does not become unacceptable.

4. If more swing is needed, increase the W/L of the cascodes and - if present -of the boosting transistors.

CMFB Network Design: The exact expression for the sizing of the CMFBreturn transistors will depend on the architecture of the OP and the placementof these transistors. For a PMOS-input folded-cascode OP with the return tran-sistors placed at the bottom of the cascode stacks (in an NMOS input OP thecorresponding transistors would instead be at the top of the cascode stacks) theywill be required to sink half of the bias current fed to the input-pair plus thecurrent fed to one cascode stack. They will be controlled by a diode-connectedtransistor in the CMFB circuit that under quiescent conditions should be sinkinghalf of the total bias current fed to CMFB network. Hence we obtain the followingexpression for the mirroring ratio of the return transistors:(

1

2Ns1,bias +Ns2,bias

)Ibias =

1

2NCMFB,biasNCMFB,returnIbias

⇔ (38)

NCMFB,return =Ns1,bias + 2Ns2,bias

NCMFB,bias

In this expression Ns1,bias is the mirroring ratio of the input pair bias transistor(Ms1,bias in Figure 45), Ns2,bias is the mirroring ratio of the stack biasing transistors(Ms2,bias,+ and Ms2,bias,−) and NCMFB,bias is the mirroring ratio of the transistorbiasing the CMFB network (i.e. the transistor that would be used to implementthe biasing current source in a practical implementation of the the network shownin Figure 40). Ibias is the global bias current supplied to the OP.

It is also at least in principle possible to place the return transistors at thetop of the cascode stacks (for PMOS input OPs, the corresponding location in anNMOS input OP would be at the bottom of the stack). In this case they should besized to source the intended biasing current for the cascode stack under quiescentconditions while the transistors at the bottom of the stack must be sized to sinkhalf the bias current fed to the input pair plus the bias current for the stacks.Using this position for the CMFB return transistors will cause these to handlea smaller amount of current than they would need to if they were placed at thebottom of the stacks. This in turn causes any changes in their bias voltages tohave a smaller eect on the output CM voltage which makes the regulation ofthis voltage less eective, hence positioning the CMFB return transistors at thebottom of the cascode stacks (or at the top for NMOS input OPs) is generally tobe preferred.

77


3.8.4 Folded-Cascode Op-Amps With Class-AB Outputs

A class-AB output may be added to a folded-cascode op-amp by adding an extrastage and some biasing circuitry as shown in Figure 46. The added circuitryconsists of the output stage itself comprised of transistors Mout,N and Mout,P anda biasing network consisting of transistors MAB-bias,N and MAB-bias,P .

The function of the biasing network can be seen in several dierent ways,in [7, pp. 125-128 and 254-260] it is described in terms of currents. We mayalso opt for looking at it in terms of voltages by recognising that the DC gatevoltages of the output transistors are set by the gate voltages of MAB-bias,N andMAB-bias,P plus/minus the Vgs-drops of these two transistors. Recognising this itis apparent that we have a plethora of options for changing the bias points of theoutput transistor gates as anything that changes either the gate voltages of thebiasing transistors or their Vgs-drops will aect the biasing points in the outputstage. The biasing points of the output stage in turn determines such things asthe bias current consumption and bandwidth (with gm,out = gm,out,N + gm,out,P asan intermediate parameter that together with the load capacitance determines thebandwidth) of the output stage.

Since the output stage is essentially a two-transistor GA stage adding this partgives rise to stability problems which are similar to those presented for the GA-GAarchitecture, hence some manipulation of the stage bandwidths may be needed.Assuming that the cascodes have a large bandwidth compared to the GA stageswe may treat the structure as a two-stage one. In this case the parts up until theoutput stage are treated as a single stage with its bandwidth set by the gm of theinput transistors together with the capacitive loading presented at the inputs tothe output stage. Unfortunately this capacitance is not easy to estimate, henceusing the simulator to measure it is probably the best option. One can then usethe input transistor gm to manipulate the bandwidth, referring to Equation (7b)since the Vgs of the input transistors is xed by the input CM voltage. Linearadjustment of the input stage transconductance and bandwidth is thus possibleby simultaneously adjusting W/L and Id by the same factor.

The bandwidth of the output stage is determined by the total output stagetransconductance gm,out = gm,out,N + gm,out,P together with the load capacitance.In this case the parameters which may be varied independently of each other areno longer the W/L-ratio and the drain current but rather the W/L-ratio and Vov.Hence (7a) is more suitable to refer to than (7b) when attempting to manipulatethe gm in a systematic manner. While it is possible to manipulate gm by changingVov this is not straightforward since Vov depends on a rather large number ofother parameters (as previously described), hence changing the W/L-ratios of theoutput transistors provides the easiest way of manipulating the bandwidth. Doingso yields an approximately linear increase in gm,out.

78


MCMFB-return

VSS

MN-cascode

Ms2,bias

MP-cascode

VDD

vCM,error

Vbias,N2

Vbias,P2

Vbias,P1

Ibias,stack

Iin

vout

(a) Cascode stack before theaddition of the class-AB out-put.

MCMFB-return

VSS

MN-cascode

Ms2,bias

MP-cascode

VDD

vCM,error

Vbias,N2

Vbias,P2

Vbias,P1

Ibias,stack

Iin

voutMAB-bias,N MAB-bias,P VAB-bias,PVAB-bias,N

Mout,P

Mout,N

VDD

VSS

(b) Cascode stack with the class-AB output added.

VSS

VDD

Vbias,N2

VSS

MAB-bias,N1

VDD

Vbias,P2

Vbias,P1

Ibias,AB-N

MAB-bias,N2

MAB-diode,N2

MAB-diode,N1

MAB-diode,P2

MAB-diode,P1

Vbias,N1

MAB-bias,P2

MAB-bias,P1

Ibias,AB-P

VAB-bias,N VAB-bias,P

(c) Biasing circuitry for the class-AB output stage.

Figure 46: Addition of an extra stage and biasing circuitry to provide a folded-cascodeop-amp with a class-AB output.

79


3.8.5 GA-GA Op-Amps

Ibias,s1

MN,+ MN,-

MP,+ MP,-

VDD

VSS

vin,+ vin,-

VDD

Mout,-

VDD

Rcomp Ccomp

Vbias

VSS

Mload,-

vout,+

Mbias

Ibias,s2

Mout,+

VDD

RcompCcomp

VSS

Mload,+

vout,-

Ibias,s2

verror,s2

VSS

Mdiode

Ibias

Vbias

VDD

verror,s1

verror,s2

Figure 47: Schematic of a typical GA-GA op-amp. The CMFB error voltage shouldbe connected either to verror,s1 or to verror,s2. In the former case the output stage loadtransistors should be constant-current sources and verror,s2 should thus be tied to Vbias.In the latter case the inner CMFB loop shown in Figure 48 should be used.

The GA-GA op-amp shown in Figure 47 is the classic op-amp structureconsisting of two stages which are both congured as common-source ampliers.The term GA-GA is taken from [7] where common-source stages are referred toas General Ampliers (GA), hence the name describes the overall structure of thearchitecture.

In folded-cascode ampliers one can often neglect considering the bandwidth ofthe cascode stages due to this being inherently much higher than that of common-source stages, such a thing obviously cannot be done when both stages are of thecommon-source type. In this case a compensation network must usually be addedto achieve stability, if Miller-compensation is used the addition of the compensa-tion network changes the overall frequency characteristics of both the individualstages and the op-amp as a whole. This makes designing a GA-GA op-amp for acertain bandwidth quite a bit more dicult than was the case for a folded-cascodeop-amp and one must generally perform some iteration involving changing thebandwidths of the individual stages as well as the sizing of the compensationnetwork in order to achieve both the desired bandwidth and the desired phasemargin.

To achieve stability using Miller-compensation the bandwidth of the outputstage must be considerably higher than that of the input stage even before thecompensation is added. It has proven dicult to give exact numbers for how muchhigher but as a rule-of-thumb 10-100 times have worked well. Since the additionof the Miller capacitor decreases the bandwidth of the dominant (if the op-amp

80


is properly designed) input stage the bandwidth of this stage must also be a bithigher than the target bandwidth before the compensation network is added.

Achieving this separation of the stage bandwidths can be very problematicwhen low thermal noise is the primary design goal. In order to decrease the input-referred thermal noise the noise due to the input stage must be decreased as thisstage by far has the largest impact on the total input-referred noise. For thenoise of this stage to be decreased it will generally be necessary to increase the gmof the input transistors which unfortunately also has the eect of increasing thebandwidth of the input stage and thus forces one to also increase the bandwidthof the output stage in order to achieve sucient separation of the poles. If thisprocess is pushed far enough the parasitic capacitances at various other nodes willeventually become large enough that one starts getting signicant contributionsto the phase other than those from the two poles accounted for in the descriptionfound here. This eventually places a limit on how much one can increase the gmof the input stage while still maintaining an acceptable phase margin which inturn limits the noise performance that can be achieved through sizing the op-ampitself.

When attempting to achieve stable operation this should be done for the worst-case scenario. This scenario occurs for the largest expected load (since increas-ing the op-amp load reduces the bandwidth of the non-dominant output stage),the lowest possible output stage transconductance (reducing the output stagetransconductance also reduces the output stage bandwidth) and for unity-gainfeedback. One thing that may be noticed here is that if one knows in advancethat unity-gain feedback will never be used then stability is not as dicult toachieve which ultimately translates into less current being needed in the outputstage since the bandwidth of this stage can then be reduced. [7]

The gain of a GA-GA op-amp can be dicult to control because most of theparameters that inuence it (bias currents and transistor W/L-ratios) also inu-ence stage bandwidths. Thus there is generally not much room for adjusting thegain after the desired bandwidth as well as stability have been achieved. There ishowever still some room to inuence the gain without too much eect on the stagebandwidths11 by adjusting the lengths of the transistors. It should be rememberedthat since there is nothing to buer the output stage any gain achieved here mightbe ruined by the load and hence one should generally attempt to achieve the bulkof the gain in the input stage. In case not enough gain can be achieved in this wayit may be necessary to add more stages so that one ends up with for example a GA-GA-GA amplier, doing so complicates the design of the compensation networksconsiderably though.

11Assuming that the capacitances seen by each stage are dominated by contributions otherthan those from the transistors. Otherwise changing the transistor lenghts would also change thebandwidths, in particular changing the length of the output transistors will increase the loadingthat this stage presents to the input stage and hence decrease the input stage bandwidth.

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Compensation Network Design: Below follows an attempt at formulating abrief step-by-step procedure to help in the design of compensation networks forGA-GA op-amps:

1. Investigate which phase margin yields the lowest settling time based on re-quirements on the deviation from the nal value.

2. Adjust the gm:s of the op-amp stages to bring the poles apart by a reasonableamount (10-100 times seems to be good starting value in practice).

3. Add the compensation capacitor together with a series resistor sized atRcomp = 1/gm,s2, size the capacitor such that the desired phase margin isachieved.

The last two steps tend to require some trial-and-error and should thus be per-formed iteratively, in particular it might be possible to nd values that achieve alower power consumption and smaller capacitor area.

Ibias,s1

MN,+ MN,-

MP,+ MP,-

VDD

VSS

vin,+ vin,-

VDD

Vbias Mbias

Rsense,+ Rsense,-

vout,s1,- vout,s1,+

Figure 48: Inner CMFB loop used to control the CM level of the input stage if the mainCMFB network error voltage is fed to the output stages.

CMFB Network Design: As indicated in Figure 47 there are two possibleplaces to connect the error voltage from the CMFB network. All stages shouldhave their CM levels controlled by some feedback mechanism, hence if the errorvoltage from the main CMFB loop is connected to the Verror,s2 nodes an innerCMFB loop such as the one shown in Figure 48 is needed. In this loop the two

82


resistors are used to sense the CM voltage at the output of the stage by taking themean of the two output voltages. The sensed CM voltage is then fed directly tothe gates of the load transistors which provides negative feedback that stabilisesthe CM level at the output of the stage.

The extra CMFB loop will unfortunately present a resistive load at the outputof the stage which may limit the achievable gain. As previously mentioned inSections 3.3.5 and 3.8.1 it is desirable to achieve the bulk of the gain in the inputstage as the op-amp can otherwise easily become noisy and sensitive to loading.Hence any limitation on the gain here is particularly problematic and it is usuallypreferable to connect the main CMFB loop error voltage to the Verror,s1 node sothat the main loop controls the CM levels of all stages.

3.9 Design of Instrumentation Ampliers

The primary distinction between op-amps and instrumentation ampliers concerntheir input impedance and the use of a dierential input. An instrumentationamplier can basically be thought of as an op-amp-like amplier with a dierentialinput where the feedback path has somehow been separated from the input path toenable the amplier to have a very high input impdedance. In contrast, a normalop-amp can be congured such that the closed-loop structure has a dierentialinput but for this one has to add resistors in the signal path which limits theachievable input impedance and may thus cause the amplier to load the source.In sensor applications there is often a need for dierential readouts from sourcewhich can have rather high source resistances, hence practically any amount of loadpresented to the source can be problematic. In such applications instrumentationampliers are therefore often used in the place of normal op-amps.

A common way of constructing instrumentation ampliers is shown in Figure49. This structure is fairly straightforward and basically consists of a fully dier-ential op-amp-based amplier where two op-amp-based buers have been placedon the inputs to allow for keeping the input impedance high. However, [7, p. 320]points out that this type of structure has the problem that its CMRR ultimatelydepends on the accuracy with which the resistors can be matched. For this reasonthis structure is referred to as a semi-instrumentation amplier in [7].

Feedback-based ampliers can be described in general terms by the block dia-gram shown in Figure 50a. This general description can be mapped to the non-inverting op-amp-based amplier shown in Figure 50b in a very straighforwardmanner. In the op-amp-based structure the subtraction takes place at the inputto the dierential pair in the rst gm-cell, the two op-amp stages implement theamplier and the feedback factor β is set by a resistive divider. This yields a gainof

Aclosed-loop =A

1 + βA(39)

which for high a enough gain A is accurately approximated by Aclosed-loop ≈ β−1

83


vin,+

vin,-

vout,-

vout,+

R1

R2

R2

R3

R4

R5

R6

Figure 49: A common instrumentation amplier structure (adapted from a gure in [7,p. 320]).

β

Avin vout

(a) Functional block-diagramof a feedback-based amplier.

vin

Zload,1 Zload,2

voutgm,1 gm,2

R1

R2

Subtraction and A:

β:

(b) Its mappping to an op-amp based structure.

Figure 50: Principle of feedback-controlled ampliers.

84


[6, p. 554].

β

Avin vout

gm,fb

gm,in

Figure 51: A dierent implementation of the block diagram in Figure 50a.

We may obtain another type of instrumentation amplier by instead imple-menting the feedback structure from Figure 50a using the type of structure shownin Figure 51. Here the input and output voltages are rst converted to currentsthrough the usage of transconductances gm,s1 and gm,β and the subtraction thentakes place in the current domain. A should in this case be a transimpedance gainand may thus be implemented by simply passing the sum-of-currents through e.g.a resistor. In practice gm,s1 and gm,β will be implemented using two dierentialpairs with their outputs connected together such that their currents are summed,therefore the gates of the transistors will ensure that the feedback path is isolatedfrom the signal path and hence feedback can be used to control the gain withoutaecting the source.

One possible way of implementing the structure in Figure 51 is shown in Fig-ure 52. Here a GA-GA op-amp has been made into a GA-GA instrumentationamplier by simply replicating the input stage to provide a separate feedbackinput.

Here only a single set of load transistors have been drawn to make the currentsumming more obvious. Since the bias current provided by this load will doublewhen an exta input stage is added the load should normally be made twice aswide, since this can be accomplised by adding another pair of load transistors inparallel one can in practice simply copy the whole input stage structure includingthe loads making this modication very straightforward in any schematic capturesoftware.

85


I bia

s,s1

Ms1

,+M

s1,-

MP

,+M

P,-

VD

D

VSS

v in,+

v in,-

VD

D

Mout,-

VD

D

Rco

mp

Cco

mp

Vbia

s

VSS

Vbia

sM

load,-

v out,+

Mbia

s,s1

I bia

s,s2

Mout,+V

DD

Rco

mp

Cco

mp

VSS

Mlo

ad,+

v out,-

I bia

s,s2

Vbia

s

VSS

Mdio

de

I bia

s

Vbia

s

VD

D

v CM

,err

or

I bia

s,fb

Mfb

,+M

fb,-

VSS

v fb,+

Vbia

sM

bia

s,fb

v fb,-

gm

,fb

gm

,in

Figure 52: A possible transistor-level implementation of the structure shown in Figure51, based on a GA-GA op-amp.

86


Ibias

Min,+ Min,-

VSS

vin,+ vin,-

Vbias Mbias

Rdegen Rdegen

Iout,+ Iout,-

Figure 53: Source-degenerated gm-cell.

The instrumentation amplier shown in Figure 52 has an issue with its gainaccuracy which is limited by the extent to which the gm:s of the two input stagesare matched. Mismatches in the gm:s of the stages may occur not only due toprocess-induced component variation but also due to diering CM voltages at thetwo inputs12 Since the input CM level of the feedback input is the output CM levelof the amplier an obvious way to alleviate any problems due CM mismatches isto ensure that the output CM level of the amplier is well regulated and tracksthe CM level at the main input.

If this is not enough another option is to use gm-cells whose gm:s are lesssensitive to variations in the input gate DC voltages. The source degeneratedstage shown in Figure 53 is an example of such a cell. It should be noticedhowever that since the source degeneration lowers the gm it is highly likely (thishas not been examined and is thus presented as a speculative remark) that thistype of cell exhibits more noise than its non-degenerated cousin. Several types ofgm-cells with tunable gm have been presented in the literature (for instance in [9]),using such cells together with some suitable tuning scheme may also be an optionif high precision is needed.

12This is caused by the non-ideal nature of the biasing current sources. If the biasing currentsource for each input could be made ideal the input CM voltages would have no inuencewhatsoever on the gm:s of the input pairs which would then be set according to Equation (7b).Any change in the input CM voltage would in this case lead to a corresponding change in thevoltage at the virtual ground node between the two input transistors and the current source ofeach pair, causing the Vov of the transistors to remain constant. In practice such ideal currentsource can unfortunately not be implemented and due to the nite resistance of realiseablesources changes in the CM voltage may inuence the Vov:s and hence cause gm mismatches thatcan degrade the gain accuracy.

87


4 Design Details

4.1 Initial System Planning

vsig,0 vsig,1 vsig,2 S

vin,0

voutvin,1

vin,2

Gain Control 1

Gain Control 2

Offset Control 2

Gain Control 3

Offset Control 3

ADC

Figure 54: Overview of the system as originally conceived.

A rough outline of the functional blocks in the originally conceived system isshown in Figure 54. All stages provides gain control but only the last two providecontrol of the oset, in addition the last stage provides ltering for the purposesof anti-aliasing and reducing the noise bandwidth of the system before analog-to-digital conversion. A global enable input is provided to oer the possibility topower the entire amplier chain down when it is not to be used.

4.1.1 Gain Partitioning

A gain of 1000 would hardly be feasible to achieve using a single amplier stage.Since 1000 = 103 this gure naturally suggests an architecture using three stageseach having a maximum gain of 10, the usage of 3 stages was therefore decidedupon at the outset of the design work. In the discussions leading to this decision itwas also decided that each stage should be possible to bypass. Some implicationsregarding the requirements placed on each stage are presented below.

4.1.2 Oset and Low-Frequency Noise Removal

Initial attempts at constructing the ampliers employed the improved version ofthe switched-capacitor gain circuit described in Section 3.4.1. However it wasfound that a low enough level of input referred noise is probably not feasible toachieve using this structure due to the problems with folding of noise when usingCDS described in Section 3.4.2. As a result work on this structure was abandonedin favor of structures employing resistive feedback.

Some experiments with using chopping to remove low-frequency noise were alsoperformed. In the end it was however found that the gains from employing thistechnique were to small to motivate the introduction of potential problems due tochopping artifacts, hence all reduction of 1/f noise has been performed by simplyadjusting the sizing of relevant transistors and no special techniques have been

88


employed for this purpose. Considering the high maximum gain of the amplierchain not including any oset-reduction techniques would most likely make thecircuit unusuable. The digital oset-removal technique described in Section 3.4.4has therefore been used. This technique adds extra noise and was therefore onlyused in stages two and three.

4.1.3 Anti-Aliasing and Limiting the Noise Bandwidth

Since the ADC following the amplier chain performs sampling folding of inputsignal components above the Nyquist frequency is an issue. From the initial doc-uments supplying details on expected input signals and usage scenarios it wouldappear that all signals would be limited in frequency, however it would most likelybe imprudent to expect the spectrum of all inputs to fall within a narrow frequencyrange as the input could also contain harmonics of the nominal input frequencies.In addition the stringent requirements on noise makes folding of noise into a ser-ious issue as this could cause the eective noise bandwidth to become very highand thus make it impossible to obtain an acceptable noise performance.

For these reasons it was desirable to add a lter at the very end of the amplierchain. However it was strongly undesirable to add another stage to the chain asthis would lead to higher power consumption (particularly considering that thislter circuit would need as high a swing as the nal amplication stage) and thusit became desirable to merge the lter into the nal amplier stage.

4.2 Stage Descriptions

4.2.1 First Stage

In many ways the most extreme requirements were placed on the rst stage inthe chain as this stage needs to work with a weak signal coming from a relativelyhigh-impedance source. The input signal of later stages will already have beenamplied and will come from an amplier with relatively low output impedanceand hence the requirements on these will be less stringent.

Due to the weak signal the rst stage is required to have good noise performancewhile the high impedance of the input source causes it to require a high inputimpedance. In order to provide a high input impedeance an instrumentationamplier with separate feedback inputs - as described in Section 3.9 - rather thanan op-amp was used in this stage. The instrumentation amplier was not designedas such but rather created as a derivative of the previously constructed op-amp(used in stages two and three) by including a copy of the input pair to use forthe feedback inputs and adjusting the sizing of the input-stage load transistorsaccordingly.

Programmable gain (with possible settings of 1, 5 and 10) was implemented byusing programmable passive elements to set the closed-loop gain of the amplier.

89


Some gain control logic was constructed to map binary gain control-values tosignals suitable for controlling the various programmable passive components.

4.2.2 Second Stage

The second stage does not need to provide a high input impedance as in the caserst stage, thus it was possible to use an op-amp based structure employing simpleresistive-feedback to control the gain. The amplier is based around a GA-GAop-amp that has was designed with the primary objective of achieving low noise.Due to this it uses quite a large amount of chip area as transistor size directlyinuences the level of the 1/f noise and indirectly (through taking part in settingthe gm of the transistors) also inuences the level of thermal noise.

As in the case of the rst stage programmable passive components togetherwith suitable control logic is used to obtain programmable gain (with possiblesettings of 1, 5 and 10). Programmable oset is implemented by adding an osetcurrent at the input.

4.2.3 Third Stage

The design of the third stage was complicated by the desirability to implementltering as well as programmable gain (with possible settings of 1, 2, 4, 6, 8 and10). As has been noted in Section 2.6.1 the gain cannot be set independently of theQ in Sallen-Key lter structures, for this reason the MFB structure was choosenfor the lter implementation with the same op-amp as in stage two being used forthe active element. To simplify the procedure, FilterPro [8] was used to performthe sizing and the necessary values were then implemented using programmablepassive components. In an MFB structure implementing a low-pass lter theresistive elements involved in determining the gain are also involved in determiningthe 3dB-bandwidth of the lter, hence to keep the bandwidth constant whilechanging these values it became necessary to also change the value of one of thecapacitors. As a result, stage three includes programmable capacitors as well asprogrammable resistors.

4.3 Bypasses

Bypasses were implemented in all stages using a combination of MUXes and DE-MUXes as described in Section 2.2.3. While bypassing a stage causes its eectivegain to be 1 this is still distinct from using a gain setting of 1 since a bypassedstage will not be used to condition the signal in any way. In particular, this meansthat any programmable oset (stages 2 and 3), ltering (stage 3) or impedancebuering (stage 1) oered by the stage in question will not be active. To conservepower, the active element in a bypassed stage is automatically disabled.

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It ought to be noted that due to an oversight during the construction thecompensation for switch resistances described there has not yet been carried outas of the time of writing. Further discussion of this problem will follow in Section7.1.4.

4.4 Input MUXing

Gain Control A1

Gain Control A2

Offset Control A2

Gain Control A3

Offset Control A3

Gain Control B1

Gain Control B2

Offset Control B2

Gain Control B3

Offset Control B3

Gain Control C1

Gain Control C2

Offset Control C2

Gain Control C3

Offset Control C3

S

vin,0

voutvin,1

vin,2

vsig,0

vsig,1

vsig,2

ADC

A1 ∈

1,5,10

A2 ∈

1,5,10

A3 ∈

1,2,4,6,8,10

Figure 55: Overall system with input MUXing being used only for the ADC. Compare tothe originally conceived system shown in Figure 54 where only a single, MUXed amplierchain is being used.

The need to incorporate low-pass lters for the purposes of anti-aliasing and redu-cing the noise bandwidth unfortunately proved to be a major problem in regardto the desideratum of using MUXing to allow a single amplier chain to processall sensor inputs in a round-robin fashion. As the very function of a low-pass lteris to reduce the bandwidth and thus passing slow transitions while rejecting fastones the abrupt jumps in the signal level that could result from MUXing betweenseveral inputs would not be passed properly by a lter with a small bandwidth,leading to a severely distorted output. An obvious solution would have been toincrease the lter bandwidth but this would have placed much higher demands

91


on the ADC as it would then have had to sample at a higher rate to increase theNyquist frequency. In addition the noise bandwidth would increase which wouldhave made it much harder to achieve an acceptable noise performance for the sys-tem as a whole. For this reason it was eventually decided that the amplier chainsshould not be MUXed and that the MUX should instead be moved after thesechains, placing it in between the amplication chains and the ADC as shown inFigure 55.

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5 Results

5.1 Overall Circuit Performance

Name Value Comments

Input Referred Noise 22.6µV Summed from 0.1Hz to 32kHz

Gain Error −0.494dB

Current Consumption 355µA

Current consumption of onesingle amplier chain, the totalcurrent consumption is 3 times

larger.

Estimated Area 780µm× 780µmArea of one single amplier

chain, the total estimated areais 3 times larger.

Table 3: Key performance gures of the circuit as a whole, the results presented here arefor a single amplier chain. The area was estimated using Layout XL with the utilisationratio set to 40%, all other values are means from 47 Monte Carlo runs with the nominalgain set to 60dB.

The most important performance gures for the circuit are presented in Table 3where the mean values from 100 Monte Carlo runs at a nominal gain of 60dBare used. These values are repeated in Tables 4, 5 and 6 where one can also ndmore detailed output from the Monte Carlo simulations as well as information foradditional nominal gain settings.

G (dB) Av,tot Av,1 Av,2 Av,3 vn (µV)(nominal) Min Max µ σ0 1 1 1 1 48.6 92.9 71.1 8.6320 10 10 1 1 19.4 28.3 23.5 1.6640 100 10 10 1 18.9 27.0 22.6 1.4960 1000 10 10 10 19.5 26.3 22.6 1.48

Table 4: System input referred noise in the 0.1Hz-32kHz band at various gain settings,simulated with process variation and mismatch.

When running Monte Carlo tests on the system at maximum nominal gainthe oset voltages in the ampliers sometimes cause the dierential output to bedriven to its maximum possible output swing during the dc analysis, this in turncauses the gain measured during a subsequent ac analysis to become very low.In the complete system such eects should not occur13 and such results shouldtherefore be excluded when calculating the evaluation statistics.

13The oset should be cancelled by the digital oset cancellation system, however the needed

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G (dB) Av,tot Av,1 Av,2 Av,3 Gain Error (dB)(nominal) Min Max µ σ0 1 1 1 1 -2.63 3.29 -0.190 1.1220 10 10 1 1 -2.68 3.26 -0.214 1.1240 100 10 10 1 -2.81 3.12 -0.348 1.1160 1000 10 10 10 -2.79 2.30 -0.494 1.12

Table 5: System gain error at various gain settings, simulated with process variationand mismatch.

No function for excluding points seems to be provided in ADE XL, as a work-around a smaller number of runs have been made in which such outliers do notoccur. The values in the last rows in tables 4, 5, 6 and 7 have therefore beenobtained using only 47 rather than 100 runs.

G (dB) Av,tot Av,1 Av,2 Av,3 Current Consumption (µA)(nominal) Min Max µ σ0 1 1 1 1 313 403 351 17.420 10 10 1 1 320 413 359 17.840 100 10 10 1 315 408 354 17.860 1000 10 10 10 313 397 355 16.9

Table 6: System current consumption at various gain settings, simulated with processvariation and mismatch. The presented values are for a single amplier chain.

The noise was measured using the Cadence noise analysis. The obtained outputnoise result (in V/

√Hz) was input-referred using the DC gain (since all expected

signals would be amplied by this gain) and squared to obtain a PSD whichwas integrated from 0.1Hz to 32kHz. The voltage noise was then obtained bycomputing the square root of the integrated noise power.

G (dB) Av,tot Av,1 Av,2 Av,3 f3dB (kHz)(nominal) Min Max µ σ0 1 1 1 1 32.1 32.2 32.1 0.0054520 10 10 1 1 32.1 32.2 32.1 0.0054440 100 10 10 1 32.1 32.2 32.2 0.0054260 1000 10 10 10 32.0 32.1 32.1 0.00236

Table 7: System 3dB-bandwidth at various gain settings, simulated with process vari-ation and mismatch.

calibration routine has not been written and would in any case be likely to prolong the simulationtime by enough to make it unfeasible to use during Monte Carlo evaluation.

94


The gain error was computed by measuring the simulated gain at 0.1Hz usingthe Cadence ac analysis and subtracting the nominal gain from the one obtainedfrom simulation, hence a negative value in this column means that the simulatedgain was lower than the nominal one by the stated amount of decibels. Currentconsumption was measured by adding the currents owing into the positive supplyport and the bias current port during a dc analysis. The 3dB-bandwidth wasmeasured using the output from an ac analysis and was calculated by nding thepoint at which the gain had fallen of by 3dB compared to the DC gain.

Gain Gcm,dm (dB) Gvdd,dm (dB) Gvss,dm (dB)Av,tot = 1 −69.4 −24.7 −26.2

Av,tot = 1000 −9.50 −6.69 −7.05

(a) System power supply to dierential output gain and common-modeto dierential-mode gain.

Gain Gvdd,out+ (dB) Gvss,out+ (dB)Av,tot = 1 4.66 10.0

Av,tot = 1000 3.87 10.44

(b) System power supply to single-ended output gain.

Table 8: Simulated system gain from the power supply to the dierential and single-ended outputs, the table for the dierential output also includes the common-mode todierential-mode gain. All values presented are maxima within a frequency band of0.1Hz to 10GHz.

The dierential disturbance gains were measured by using the xf analysis toobtain the transfer functions from the relevant sources to the dierential output.The values listed in Table 8a are the maximum values of each curve, in each casethe worst-case value among 98 Monte Carlo runs (100 Monte Carlo runs withoutliers excluded) was choosen. The single-ended disturbance gains were obtainedin a similar manner but using the transfer functions from the sources to the positiveoutput. Each curve shown in Figure 56 has been taken from the same run as thecorresponding worst-case value presented in Table 8a or 8b.

95


10−2

100

102

104

106

108

1010

−140

−120

−100

−80

−60

−40

−20

0

f (Hz)

Gain

(dB)

Gcm,dm

Gvdd,dm

Gvss,dm

(a) Gcm,dm, Gvdd,dm and Gvss,dm.

10−2

100

102

104

106

108

1010

−50

−40

−30

−20

−10

0

10

20

f (Hz)

Gain

(dB)

Gvdd,out+

Gvss,out+

(b) Gvdd,out+ and Gvss,out+.

Figure 56: System disturbance gains plotted versus frequency for Av,tot = 1000. Theworst cases has been choosen among 98 Monte Carlo runs (100 Monte Carlo runs withoutliers removed).

96


5.2 Op-Amp

5.2.1 Open-Loop Measurements

Name Value Comments

DC Gain 79dB

0dB Bandwidth 80MHzApproximately equal togain-bandwidth product

CMFB 0dB Bandwidth 10MHz

Phase Margin 75

CMFB Phase Margin 49

Input-Referred Noise 16µV Summed from 0.1Hz to 32kHz


Output CM voltage deviationfrom reference

+11mV

Table 9: Open-loop simulation results for the op-amp, all measurements were made withIbias = 10µA.

5.2.2 Closed-Loop Measurements With Mismatch and Process Vari-ation

Closed-Loop Gain Gdc (dB) PM () Gdc,cmfb (dB) PMcmfb (°)Av,cl = 1 75.8 39.3 35.2 51.7Av,cl = 10 63.5 62.5 50.2 54.2

Table 10: Loop gain and phase margin for the main and CMFB paths with the op-ampset in a closed-loop conguration. Out of 100 Monte Carlo runs the one yielding theworst gain was choosen for the main loop measurements, for the CMFB loop the runyielding the worst PM was used. The PM values are those reported by the Cadence stb

analysis.

For high-gain devices such as op-amps the eects of mismatch cannot be prop-erly investigated using an open-loop conguration because the resulting osetvoltage tends to drive the outputs to the rails. After the designed was nishedMonte Carlo-runs were therefore performed with the op-amp put in a closed-loopconguration with iprobe components from Cadence's analogLib library insertedto break the loop and measure its behaviour.14 All of these measurments wereperformed using the stb analysis.

14Some theoretical background about measurements involving breaking of a loop to measurethe loop behaviour can be found in [1] and [12].

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−50

0

50

Gain

(dB)

f0dB = 80MHz

100

102

104

106

108

1010

−400

−300

−200

−100

0

f (Hz)

Phase

()

(a) Main loop.

−50

0

50

Gain

(dB)

f0dB = 10MHz

100

102

104

106

108

1010

−400

−300

−200

−100

0

f (Hz)

Phase

()

(b) CMFB loop.

Figure 57: Bode plots for the open-loop op-amp.

98


−50

0

50

Gain

(dB)

f0dB = 16MHz

100

102

104

106

108

1010

−400

−300

−200

−100

0

f (Hz)

Phase

()

(a) Main loop.

−100

−50

0

50

Gain

(dB)

f0dB = 9MHz

100

102

104

106

108

1010

−100

−50

0

50

100

150

200

f (Hz)

Phase

()

(b) CMFB loop.

Figure 58: Bode plots for the op-amp congured in a closed loop with a gain of 1, thecurves here illustrate the loop gain and phase (obtained by breaking the loop using theiprobe component from analogLib) under the given feedback conditions rather than theclosed-loop behaviour under the same conditions.

99


−100

−50

0

50

100Gain

(dB)

f0dB = 6.5MHz

100

102

104

106

108

1010

−400

−300

−200

−100

0

f (Hz)

Phase

()

(a) Main loop.

−100

−50

0

50

100

Gain

(dB)

f0dB = 6.2MHz

100

102

104

106

108

1010

−100

−50

0

50

100

150

200

f (Hz)

Phase

()

(b) CMFB loop.

Figure 59: Bode plots for the op-amp congured in a closed loop with a gain of 10, thecurves here illustrate the loop gain and phase (obtained by breaking the loop using theiprobe component from analogLib) under the given feedback conditions rather than theclosed-loop behaviour under the same conditions.

100


Because this behaviour can change depending on the closed-loop gain suchmeasurements were made for closed-loop gains of Av,cl = 1 and Av,cl = 10. Two240kΩ resistors were used to set the closed-loop gain for the former case, a 240kΩand a 24kΩ resistor were used in the latter case. For each parameter the worstcase from 100 runs is presented.

Closed-Loop Gain Gcm,dm (dB) Gvdd,dm (dB) Gvss,dm (dB)Av,cl = 1 −47.9 −32.9 −29.3Av,cl = 10 −52.4 −33.1 −31.8

(a) Op-amp power supply to dierential output gain and common-mode todierential-mode gain.

Closed-Loop Gain Gvdd,out+ (dB) Gvss,out+ (dB)Av,cl = 1 1.34 9.01Av,cl = 10 1.37 8.90

(b) Op-amp power supply to single-ended output gain.

Table 11: Simulated op-amp gain from the power supply to the dierential and single-ended outputs, the table for the dierential output also includes the common-mode todierential-mode gain. All values presented are maxima within a frequency band of0.1Hz to 10GHz, the worst cases from 100 Monte Carlo runs have been selected.

While it is customary to present rejection-ratio values the gains used in thecalculation of such ratios are presented here instead. The rationale for this decisionis that rejection-ratios fall of to very low values at high frequencies due to acombination of large disturbance gains and a small signal gain. When presentinga single rejection curve the eects of these are hard to separate, hence presentingthe gains involved is more informative. The gain curves were obtained using thexf analysis.

The Gvdd,out+ and Gvss,out+ curves reveal a troublesome behaviour in whichthese disturbance gains reaches positive values at high enough frequencies. Com-parison to the dierential counterparts reveals that such disturbances are stillsuppressed in the dierential signal (even with mismatch taken into account) buteven so this behaviour will cause disturbances to aect the output CM voltage.

When input-referring disturbances the signal gain should be used. If all desiredsignals fall close to DC they will approximately be amplied by the DC gain andinput-referring should then be done using this gain rather than the frequency-dependent gain curve, all values presented here have been input-referred in thismanner.

For the oset mean values are presented in addition to worst-case ones, theclose-to-zero means indicate that there is little skew towards positive or negativeosets.

101


10−2

100

102

104

106

108

1010

−110

−100

−90

−80

−70

−60

−50

−40

−30

f (Hz)

Gain

(dB)

Gcm,dm

Gvdd,dm

Gvss,dm


10−2

100

102

104

106

108

1010

−60

−50

−40

−30

−20

−10

0

10

f (Hz)

Gain

(dB)

Gvdd,out+

Gvss,out+


Figure 60: Op-amp disturbance gains plotted versus frequency for Av,cl = 10.

102


Closed-Loop Gain vnoise,in (µV) voffset,in (mV) µoffset,in (µV)Av,cl = 1 38.8 7.19 −44.5Av,cl = 10 18.2 3.95 −24.4

Table 12: Simulated op-amp noise and oset, all values are worst-cases from 100 MonteCarlo runs and have been input-referred using the DC gain. The noise voltages havebeen obtained by summing the PSD (obtained using the noise analysis in Cadence) from0.1Hz to 32kHz which roughly represents the system bandwidth. The worst-case osetsare absolute values while the oset means are signed.

5.3 Instrumentation Amp

5.3.1 Open-Loop Measurements

Name Value Comments

DC Gain 79dB

0dB Bandwidth 80MHzApproximately equal togain-bandwidth product

CMFB 0dB Bandwidth 14MHz

Phase Margin 77

CMFB Phase Margin 43

Input-Referred Noise 15µV Summed from 0.1Hz to 32kHz


Output CM voltage deviationfrom reference

−52mV

Table 13: Open-loop simulation results for the instrumentation amplier, all measure-ments were made with Ibias = 10µA.

The performance gures for the instrumentation should be very similar to thosefor the op-amp since the share the same basic design, that this is indeed the caseis evident from Table 13. All tests of the instrumentation amplier performancegures have been carried out in the same manner as those for the op-amp.

5.3.2 Closed-Loop Measurements With Mismatch and Process Vari-ation

The noise performance would be expected to be slightly worse than in the case ofthe op-amp since the extra input also contributes noise. Interestingly enough thesimulation results are inconclusive regarding this, the instrumentation amplier

103


−100

−50

0

50

100Gain

(dB)

f0dB = 80MHz

100

102

104

106

108

1010

−400

−300

−200

−100

0

f (Hz)

Phase

()

(a) Main loop.

−100

−50

0

50

100

Gain

(dB)

f0dB = 14MHz

100

102

104

106

108

1010

−400

−300

−200

−100

0

f (Hz)

Phase

()

(b) CMFB loop.

Figure 61: Bode plots for the open-loop instrumentation amplier.

104


Closed-Loop Gain Gdc (dB) PM () Gdc,cmfb (dB) PMcmfb (°)Av,cl = 1 75.1 54.7 40.5 65.4Av,cl = 10 58.12 72.8 52.6 71.4

Table 14: Loop gain and phase margin for the main and CMFB paths with the instru-mentation amplier set in a closed-loop conguration. Out of 100 Monte Carlo runs theone yielding the worst gain was choosen for the main loop measurements, for the CMFBloop the run yielding the worst PM was used. The PM values are those reported by theCadence stb analysis.

Closed-Loop Gain Gcm,dm (dB) Gvdd,dm (dB) Gvss,dm (dB)Av,cl = 1 −39.1 −27.3 −29.0Av,cl = 10 −31.2 −30.4 −27.3

(a) Instrumentation amplier power supply to dierential output gain andcommon-mode to dierential-mode gain.

Closed-Loop Gain Gvdd,out+ (dB) Gvss,out+ (dB)Av,cl = 1 7.69 18.17Av,cl = 10 3.36 10.0

(b) Instrumentation amplier power supply to single-ended out-put gain.

Table 15: Simulated instrumentation amplier gain from the power supply to the dif-ferential and single-ended outputs, the table for the dierential output also includes thecommon-mode to dierential-mode gain. All values presented are maxima within a fre-quency band of 0.1Hz to 10GHz, the worst cases from 100 Monte Carlo runs have beenselected.

105


−50

0

50

Gain

(dB)

f0dB = 16MHz

100

102

104

106

108

1010

−400

−300

−200

−100

0

f (Hz)

Phase

()

(a) Main loop.

−100

−50

0

50

Gain

(dB)

f0dB = 30MHz

100

102

104

106

108

1010

−100

−50

0

50

100

150

200

250

f (Hz)

Phase

()

(b) CMFB loop.

Figure 62: Bode plots for the instrumentation amplier congured in a closed loop witha gain of 1, the curves here illustrate the loop gain and phase (obtained by breaking theloop using the iprobe component from analogLib) under the given feedback conditionsclosed-loop behaviour under the same conditions.

106


−100

−50

0

50

100Gain

(dB)

f0dB = 10MHz

100

102

104

106

108

1010

−400

−300

−200

−100

0

f (Hz)

Phase

()

(a) Main loop.

−100

−50

0

50

100

Gain

(dB)

f0dB = 29MHz

100

102

104

106

108

1010

−100

−50

0

50

100

150

200

f (Hz)

Phase

()

(b) CMFB loop.

Figure 63: Bode plots for the instrumentation amplier congured in a closed loop witha gain of 10, the curves here illustrate the loop gain and phase (obtained by breakingthe loop using the iprobe component from analogLib) under the given feedback conditionsrather than the closed-loop behaviour under the same conditions.

107


does indeed exhibit worse noise performance than the op-amp at a closed-loopgain of 10 but is better at a gain of 1 and for the open-loop case.

Closed-Loop Gain vnoise,in (µV) voffset,in (mV) µoffset,in (µV)Av,cl = 1 25.5 4.82 −169Av,cl = 10 26.1 4.80 −168

Table 16: Simulated instrumentation amplier noise and oset, all values are worst-casesfrom 100 Monte Carlo runs and have been input-referred using the DC gain. The noisevoltages have been obtained by summing the PSD (obtained using the noise analysis inCadence) from 0.1Hz to 32kHz which roughly represents the system bandwidth. Theworst-case osets are absolute values while the oset means are signed.

5.4 Programmable Current Source

Branch Nominal Simulated Current (nA)Current (nA) Min Max µ σ

I0 50 22.0 105 51.5 16.6I1 100 46.1 221 110 34.2I2 200 81.8 386 209 62.4I3 400 186 819 413 125.4

Iout,+ 750 300 1317 734 221Iout,− -750 337 1400 765 233

(a) Branch and output currents.

Branch Nominal Simulated Current (nA)Current (nA) Min Max µ σ

I1 − I0 50 17.6 149 58.0 19.0I2 − I1 100 34.1 253 98.9 31.4I3 − I2 200 65.8 543 210 61.2

Iout,+ − Iout,− 0 -431 626 12.7 135

(b) Step sizes and output current mismatch.

Table 17: Currents, step sizes and output current mismatch in the programmable sourcewith the control value set to 31, tested for process variation and mismatch using 100Monte Carlo runs.

A DC analysis with an input value of 31 was run 100 times with process variationand mismatch on the programmable current source to determine the current ineach branch. The results presented in Table 17a are rather disturbing as the thevariation in the branch currents are high enough to provide reason to suspect thatthe source may become non-monotonous for some chips out of a batch. However,

108


10−2

100

102

104

106

108

1010

−110

−100

−90

−80

−70

−60

−50

−40

−30

f (Hz)

Gain

(dB)

Gcm,dm

Gvdd,dm

Gvss,dm


10−2

100

102

104

106

108

1010

−60

−50

−40

−30

−20

−10

0

10

f (Hz)

Gain

(dB)

Gvdd,out+

Gvss,out+


Figure 64: Instrumentation amplier disturbance gains plotted versus frequency forAv,cl = 10.

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the results in Table 17b indicate that this is very unlikely to happen as the meanvalues of the step sizes are in all cases more than 3 σ:s away from 0. While thesource obviously is not very precise this is likely to be less of a problem due toit being used in a feedback loop that will provide some compensation for suchimprecisions, hence monotonicity is the largest issue for this part.

A further test with swept input values was done (using a tran simulation) toexamine monotonicity in the nominal case, as is evident from Figure 65 this isunproblematic.

0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01−800

−600

−400

−200

0

200

400

600

800

t (s)

I(nA)

Iout,+−Iout,−

Figure 65: Output from the programmable current source when sweeping the input valuefrom 0 to 31.

110


6 Discussion

While a system performing the required tasks has been constructed the outcomecan nevertheless not be considered a complete success since the desired perform-ance specications have not been met. Arguably noise (specied indirectly interms of a desired bit resolution) is the most important performance measure andwhile it approaches a permissible value it is still not satisfactory.

Even so the tradeos made when trying to achieve an acceptable noise perform-ance have had unfortunate eects on other gures of merit. Area is a particularlyproblematic aspect as the transistor sizes used to achieve low noise make thedesign very resource-hungry in this respect. The current consumption is close thespecied maximum but also does not quite meet the specication.

These tradeos have primarily been made in the design of the op-amps. Un-fortunately there are not many options when it comes to lowering noise and allthat there are tend to eventually translate into larger area and power consump-tion. The need to increase the gm of a transistor to decrease its thermal noisecontribution has been particularly problematic due to the bandwidth increase itsimultaneously causes. In cases where the rst op-amp stage should contributethe dominant pole this leads to a dicult tradeo where lowering noise increasesthe dominant pole frequency and thus makes stability dicult to achieve. So farthe only way that has been found to deal with this problem is to increase thebandwidth of the second stage but this has eventually led to op-amps which havefar more bandwidth than needed and as a result consumes quite a bit of power.

In addition CMFB network design has been complicated by the large band-widths in the main loop which have made it dicult to make this loop stable.During this project, CMFB stability has mostly been the limiting factor in tryingto achieve good noise performance.

6.1 Thoughts on Workow

Aside from what has already been discussed above some lessons about workowmay also be gained from this experience. It is hard to make any denitive state-ments about this subject as dierent people tend to nd dierent ways of workingand the preferred workow thus appears to depend quite a bit on personal pref-erences, nevertheless it should be possible to at the very least identify potentialpoints where a particular workow could be improved. In particular some eortspent on trying to create standard schemes or templates for oft-repeated taskscould possibly save quite a bit of work in the long run.

Reecting on the present project it is apparent that quite a bit of eort hasbeen expended on constructing what is essentially the same testbench multipletimes when trying dierent op-amp architectures. One possible method to avoidthis would be to attempt to create a library with template testbenches for well-known device types. A primary candidate for this would be a testbench for op-

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amps as a bewildering amount of gures-of-merit exists for these devices makingtestbenches for the arduous to construct. This can in turn easily lead to guresof merit being left out when a new testbench is constructed - sometimes due tobeing consciously saved for later but often due to a simple oversight - which canlead to bad design decisions as all important parameters are not being taken intoaccount. Hence using template testbenches could potentially have quality benetsas well as saving time.

Another point where a better workow could have been used would have beento start setting up the overall system structure together with appropriate test-benches at an earlier point. In the present case all such undertakings were per-formed quite late, it is likely that this is part of the cause for the lack of propertesting of the overall system as the time necessary for this task was underestim-ated. However, it ought to be considered that this task may quite possibly appeareasier in hindsight since such things as limited experience might have made it hardto construct reasonable overall structures at the outset of the project. Neverthe-less, it might have been possible to perform this earlier than when it was done anddoing so might have been helpful in achieving some clarity regarding the natureof the overall system.

7 Future Work

7.1 Remaining Issues

7.1.1 Noise Performance

Comparing the overall system noise performance to the requirments listed in Sec-tion 1.2 it is apparent that the noise specication has not been met and thatthe system cannot achieve a resolution of even 12 bits, hence some improvementsof the noise performance are needed. It is dubious whether much improvementscan be made in the analog domain and thus it may be necessary to take a morecomprehensive view of the system to achieve this.

There is likely some room for improving the performance by simply reducingthe bandwidth. At present the analog circuitry uses a bandwidth of 32kHz set bythe lter in stage 3 which is larger than needed. Achieving a lower bandwidth inthe analog domain is not feasible as it would require unrealistically large passivecomponents in the lter but subsequent ltering in the digital domain would bepossible. This could be done in a dynamic fashion such that less bandwidth isused for lower-frequency input signals to gain better perfomance in such cases.

As has been noted in Section 4.1.2 the chain at present performs no low-frequency noise removal. It is therefore likely that reducing the bandwidth farenough will eventually yield diminishing returns as low-frequency noise starts todominate, in this case it may be necessary to reintroduce chopping in the chainfor any further improvements to be obtained.

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7.1.2 Oset Current Source Robustness

As is obvious from Table ?? the oset current sources are not robust in the faceof mismatch and process variations. As these sources are to be used as part offeedback loops some variation in the output current should be unproblematic butthe variation at present is large enough that the sources can be expected to benon-monotonic for some chips out of a batch, this may cause the feedback loop toyield unexpected results that may force the chip to be discarded. In addition thevariability between the two output currents is too large.

The cause of these problems lies in the small currents being used. This leadsto the voltages generated by the controlling diodes in the source current mirrors tobe too low which puts the transistors in weak or moderate inversion where theirsensitivity to variations and mismatch are much higher than in the saturationregion. The obvious x for this problem would thus be to attempt to ensure thatall transistors operate in or close to the strong inversion regime, however doing somay be hard without increasing the currents.

7.1.3 Lack of Proper Testing

The lack of proper testing is a troubling issue as it could potentially mean thatthere are as-of-yet-undiscovered fatal aws in the design. In general it would bedesirable to have constructed a testbench that can go through all possible com-binations of settings and check that the circuit behaves as expected and exhibitsacceptable performance for each and every such combination.

There are also some more specic test which should be carried out:

Ramp-up and Ramp-Down: At present no tests have been made of the circuitbehaviour when it is presented with a slow ramp-up or ramp-down of thesupply voltage, a type of situation that is likely to occur when the circuit ispowered on and o. Due to this there could possibly exist some undiscoveredlatch-up behaviour that may cause the circuit to get stuck in an undesiredstate when presented with such supply voltages.

CMRR and PSRR: The CMRR and PSRR of the circuit as a whole shouldlikely be tested.

Checks on start-up time: Some checks ought to be performed of how fast thesystem is able to transition into a functioning state after being brought backfrom its disabled state

7.1.4 Compensation For MUX Switch Resistances

The gain of stages 2 and 3 does not compensate for the resistance added bythe MUX/DEMUX switches. This is due to an oversight during the design inconjuction with time constraints during the nal weeks of design. In principle it

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is possible to compensate for this by sizing the input resistances of the amplierssuch that they achieve their correct values when the switch resistances of theMUXes/DEMUXes are taken into account, unfortunately this is complicated bythe bypass function. Even assuming ideal op-amps with zero output resistanceand a likewise ideal signal source the second stage would see an extra resistancefrom one single switch when the rst stage is engaged but an extra resistancedue to two series-connected switches when the rst stage is bypassed. While theassumption of an ideal op-amp might be reasonably close to actual reality theassumption of an ideal signal source most denitely is not. Hence the additionalresistance due to the source must also be taken into account when the rst stageis bypassed, fortunately this resistance is reasonably well-known since it is partsof the specication of the measurement bridge. The situation for the third stage issimilar but becomes slightly more complicated since the resistance seen dependson the bypassing or not of two stages rather than one.

Depending on how serious of an issue this is and upon other concerns that mayaect the decision it may be desirable to add equalising resistances in the mannerdescribed in Section 2.2.3. In practice this would entails adding one always-ontransistor switch and one resistor - using whatever type of process resistor isjudged to be closest in nature to the resistors in the measurement bridge - betweenthe amplier and the MUX in the rst stage. In the second stage a copy of thepreviously added resistance would be inserted in addition to one further always-ontransistor swithc. The gain setting resistances could then be modied accordingly.

7.1.5 CMFB Reference Voltage

The CMFB voltage reference still has no realistic source. Probably take frombridge at least for the rst stage, since it's fed to a high impedance dierentialpair input buering should not be necessary and would make little dierence interms of loading since buering would be done with an op-amp that would haveone side of a dierential pair as its input.

7.1.6 Segment Values in the Programmable Passive Components

The sizing of the passive components used in each segment of the programmablepassives are at present such that it would not be possible to use unit elementsin their implementation, this could be a major issue due to the resulting prob-lems with matching and therefore with such things as gain accuracy and possiblyCMRR. In addition, matching would need to be achieved between elements of dif-ferent types if the overall matching is to be precise. As this is likely not possibleone must conclude that good matching probably is not possible in the presentdesign and that achieving good matching would call for the use of e.g. switched-capacitor structures instead. Due to the previously noted problems with foldingof noise in such structures one is therefore confronted with the dilemma of either

114


being able to achieve an acceptable noise level but not acceptable matching orbeing able to achieve acceptble matching but not acceptable noise levels. It is ofcourse quite possible that some better method exists that would allow for both ofthese to be achieved simultaneously but at the time of writing no such method isknown to the author.

7.1.7 Power Supply Disturbances

10−2

100

102

104

106

108

1010

−60

−40

−20

0

20

40

60

80

100

f (Hz)

Gain

(dB)

GCMFB (dB)Gps,cm (dB)

Figure 66: CMFB gain and single-ended power-supply disturbance gain.

High-frequency disturbances originating from the power supplies can at presentfeed through into the outputs. As can be inferred from Figure 66 this is connectedto the CMFB gain. When this gain starts falling o the suppression of the single-ended disturbance gain gets worse because the the CMFB loop can no longerregulate the output CM voltage at high frequencies. Assuming a perfectly sym-metrical circuit this will aect the CM level only but not the dierential outputvoltage, in practice inevitable process variations will ensure that this aects thedierential PSRR as well.

In principle the problem could be solved by redesigning the op-amp to obtaina higher CMFB loop bandwidth but in practice this introduces a tradeo withnoise. Referring to Figure 47 we see that each load transistor in the input stageform a GA amplier with the CM error voltage as input and the main transistoras its load. This amplier contributes the dominant pole to the CMFB loop andwould thus need to be increased to increase the CMFB bandwidth.

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To increase the bandwidth of this stage one must increase its gm15 but this

cannot be done without degrading the noise performance since - as is evident fromEquation (21) - the input referred noise of the rst stage depends on the ratiobetween the load gm and the main transistor gm.

7.2 Potential Improvements

7.2.1 Elimination of MUXes

The bypass mechanism of each stage presently involves both a MUX and a DE-MUX, placing two switch resistances in the signal path. The control logic isdesigned to disable the op-amp when a stage is bypassed, in combination with theop-amps being designed to set their outputs in high-Z mode when disabled thisshould allow for eliminating the MUX from the bypass mechanism.

7.2.2 Improving the Gain Precision of Stage One

The gain precision of the rst stage can degrade due to diering CM input levels atthe two inputs to the instrumentation amplier causing dierent gm:s. The gainprecision might potentially be possible to improve using some gm linearisationtechnique such as the source degeneration described in Section 3.9.

7.2.3 Usage of Chopping For Low-Frequency Noise Removal

In Section ?? it was mentioned that the op-amps consume considerable area asa result of being designed for low noise. Since reduction of 1/f -noise is a majorfactor behind the high area consumption it might be possible to reduce the areaby using chopping as this might allow one to use larger transistors for the sameamount of noise. However it must be remembered that decreasing thermal noisealso indirectly tends to call for an increase in area (through the connection betweentransistor width and gm), hence it is possible that any gains obtained through thiswould be to small to motivate doing it. Since the knee frequency of the transistorneeds to be placed below the chopping frequency for chopping to be eective it isalso quite possible that any attempts at signicantly reducing the area would callfor using a high chopping frequency for the same amount of noise to be obtained.This would in turn call for higher op-amp bandwidth which could cause a tradeobetween area and power to occur for a given amount of noise.

15In principle one could also decrease its load capacitance but the load for this stage is dueto other components and cannot be changed without seriously aecting other characteristics ofthe op-amp.

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7.2.4 Optimisation of Op-Amps

The dierent requirements placed on the dierent stages might have made it ad-vantageous to employ a dierent type of architectures for each stage, however onlyone single op-amp ended up being used in the actual design due to time constaints.

The requirements placed on the rst stage are primarily good noise perform-ance and high input impedance while good swing is not very important. Thepresently used instrumentation amplier is well optimised for noise and input im-pedance but does not take advantage of the relaxed swing requirements.

The requirements placed on the second amplier stage are essentially some-where in between those placed on the rst and third stages while the third amp-lier stage has very relaxed requirements regarding noise performance and inputimpedance but requires a large output swing. The op-amp presently used in thesetwo stages is not very well optimised for either of them, in particular its noiseperformance is better than needed and thus noise performance could probably betraded for power consumption.

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Appendices

A Derivations of Wheatstone Bridge Equations

vdf

R1 R2

R3 R4

VDD

Figure 67: Using a Wheatstone bridge to measure the resistance of a resistor Rx, thisschematic was shown previously in Figure 2 but is reproduced here for convenience.

Suppose that all of the xed resistances in Figure 67 are equal such that R2 =R3 = R4 = R and that the bridge is unbalanced by letting R1 vary around anominal resistance R such that R1 = R + ∆R1. The dierential output voltagewill then be

vdf = vout,+ − vout,− =

(R

2R− R

2R + ∆R1

)Vdd. (40)

We may rearrange this to obtain

∆R1 =RVdd

vdf + 12Vdd− 2R (41)

from which it is apparent that knowing R, Vdd and vdf we can calculate by howmuch Rx deviates from its nominal value. For a strain guage this implicates that ifwe have some function mapping the variations in resistance to variations in strainthen (assuming that R and Vdd are already known) we can determine the strainput on the sensor from measurements of vdf .

Because measurements of any quantity can only be carried out with niteprecision it is of interest to know how large variations we can expect in vdf from agiven variation in ∆R1. To estimate this we perform a Taylor expansion around∆R1 = 0 to obtain

R

2R + ∆R1

≈ 1

2− ∆R1

22R+

∆R21

23R− ∆R3

1

24R+ · · · ≈ 1

2− ∆R1

4R. (42)

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This approximation holds for R ∆R1 which is a valid assumption for strainguages due to their small variations in resistance when the strain is altered.

The setup where only a single resistor is made to vary is called a quarter-bridge.We can obtain a stronger signal by allowing more of the resistors to vary, we referto such setups as half-bridges (when two resistors vary) or full bridges (when allresistors vary). Suppose that both R1 and R3 are made to vary with ∆R1 and ∆R3

being equal in magnitude but opposite in sign such that −∆R1 = ∆R3 = ∆R, wethen obtain

v− =R3 + ∆R3

R1 + ∆R1 +R3 + ∆R3

=1

2+

∆R

2R(43)

The dierential output voltage for the half-bridge case thus becomes

vdf =

(1

2−[

1

2− ∆R

2R

])Vdd =

∆R

2RVdd (44)

The same eect may obviously be obtained by letting one of the resistors on thepositive side vary with an appropriate sign. In the full-bridge case where both res-istors on both sides are allowed to vary (with equal magnitudes and appropriatelychoosen signs) we obtain

vdf =∆R

RVdd (45)

Obviously using a full bridge would be preferable as 2 bits of performance aregained for this case compared to the quarter-bridge one.

Since physical components always have some tolerance it is of interest to knowwhat maximum oset voltage one can expect from a bridge. In this case allresistors may vary and we thus essentially obtain a full bridge, if ∆Rmax is speciedas a percentage P of the total nominal resistance so that ∆Rmax = 0.01P · R weobtain

voffset,max =0.01P ·R

RVdd = 0.01P · Vdd (46)

To model a Wheatstone bridge as a signal source the output resistance is neededin addition to the output voltage. Each output node sees two parallel resistorsconnected to AC ground, hence there is R/2 ohms of resistance in each branch.

B Noise-Reduction in the Digital Domain

A simple way to increase the eective resolution of an ADC is by averaging sev-eral output values. Assuming that the desired signal value stays approximatelyconstant during the time over which the averaging is done. Suppose that we haveK sampled voltages vi = VS + vn,i where VS is a signal voltage that is equal for allsamples and the vn,i(σn) voltages are uncorrelated noise voltages with zero mean

119


and a common variance σn. In this case the powers of all noise voltages are equaland averaging therefore yields

vavg =KVS +

√vn,1 + vn,2 + · · ·+ vn,K

K= Vs +

√KV 2

n (σn)

K= VS +

Vn(σn)√K

(47)

From this it is apparent that the noise voltage decreases with the square root ofthe number of averaged samples. Since we gain one bit of eective resolution forevery doubling of the SNR we must thus average 22L samples to gain L bits ofeective resolution.

D D D

↓4

sin

sout

1/4 1/4 1/4 1/4

Figure 68: Block diagram of an averaging function that produces one output sample forevery 4 input samples.

Averaging of consecutive samples is likely not a very ecient way to reducenoise however. Averaging of four input samples to produce one output sample isillustrated in Figure 68 where it can be seen that it can be done by applying asliding average lter to the input followed by a decimation by four. From this itis easily realised that what is actually performed is four times of downsamplingwith the decimation lter implemented using the sliding average method. Thistype of lter implementation is simple but much better lters can be made, usinga better lter would likely increase the performance gains from the system.

A further insight provided by this way of viewing averaging is that the noisereduction is performed by decreasing the noise bandwidth. From this it is apparentthat the eciency of this scheme is dependent on the frequency characteristics ofthe noise. If 1/f -noise dominates this method is unlikely to yield much of aperformance improvement since low-frequency noise has a high degree of temporalself-correlation, resulting in the assumptions used in (47) no longer being valid.

C Performing Measurements in Cadence

, in this case the immovable reference point will end up in a dierent positioncompared to the sources used in the xf simulation and the positive and negativePSRR values will both be equal to the positive PSRR from the previous case.

120


We may additionally be interested in the PSRR for each of the two outputs.Because no cancellation of common-mode disturbances from the power supply willoccur when looking at a single output this gure can be expected to be quite abit worse than the dierential one, in particular it provides some hints as to howthe common-mode voltage at the output will be aected by supply disturbances.For the positive output this PSRR may be dened as

PSRRse,lin =

∣∣∣∣Adm,out+

Aps,out+

∣∣∣∣ (48)

An analogous denition may be used in the case of the negative output.

C.1 Noise In Switched-Capacitor Circuits

For an open-loop OP measuring noise is generally fairly straightforward whenworking in the Cadence environment due to the inclusion of a noise analysis inthe simulation type options. When working with periodically varying architecturesuch as switched-capacitor circuits the noise of the system as a whole is moredicult to measure since the time-varying nature of the system must be takeninto account. For instance, the SC amplier described in Section 3.4.1 sampleslow-frequency noise in its non-valid operation phase and subtracts it during thevalid phase. When SC circuits are used it is ultimately the noise in the sampledsignal that is of interest. Since sampling will introduce folding of noise above theNyquist frequency this noise may dier from the noise obtained for the continuouscase.

C.1.1 Setting Up a PSS Simulation

As is the case for most clocked circuits SC circuit require special methods forsimulation due to their periodically varying nature. Cadence provides a numberof simulation methods for handling circuits of this type. All of these methods arebased on the concept of a stable periodic operating point, i.e. a state in which theoperating point of the circuit varies periodically in such a manner that it ideallywould behave identically from cycle to cycle. To nd such an operating point allperiodic simulations require that one rst run a pss simulation, this is essentiallya type of transient simulation which attempts to nd a time period within whichthe circuit starts and ends in the same operating point although the operatingpoint may vary between the start and end of this time period. In setting up thissimulation one is required to set the following parameters:

Beat Frequency or Beat Period: This parameter sets the length of the cycleto be used when the simulator attempts to nd a periodically varying oper-ating point. It should be choosen in such a way that all varying signals in thecircuit have time to repeat at least one cycle within the choosen timespan.

121


Output Harmonics: The number of output harmonics determines how manyharmonics of the beat frequency are taken into account when results based onthe PSS simulation are calculated. It should be set based on some acceptablecompromise between simulation speed and accuracy, a possible method fornding such a compromise is to gradually increase it and see where theoutput value of interest stop changing by much.

tstab: tstab sets an initial time during which a transient analysis is performedbefore an attempt is made to nd a PSS operating point, it should be setsuch that the circuit has enough time to become stable during this initialtransient run.

In addition to the above which must be set for the simulation to run maxacfreq isalso an important parameter in many situations. It determines the maximum ACfrequency which will be taken into account when PSS-based analyses such as pnoiseare run, if the value is too low the output from such analyses may be misleadingsince for e.g. a switched-capacitor amplier too little noise might be folded downif this parameter is not set such that the full noise bandwidth is included. It canbe found by choosing Options ä Accuracy in the PSS setup window.

C.1.2 Open-Loop Noise

The open-loop noise is essentially continuous in nature. It is possible to meas-ure it in a simulation run where one also measures pnoise by using the switchesprovided in the analogLib library to put the circuit in open-loop when the normalnoise analysis is run and in closed-loop for all pss-based simulations. The noisesimulation uses the ac position of the switches and all pss-based analyses uses thetran position.

C.1.3 Closed-Loop Noise

It is possible to see the eects of the sampling by choosing the sampling point, thismay be useful for validating that the setup used yields results that conform to whattheory would have one expect. For instance, when using the switched-capacitorgain-circuit from Section 3.4.1 selecting the sampling point such that samplingoccurs during the non-valid phase will cause no cancellation of low-frequency noiseto occur in the measured noise and the output noise will thus be quite high. Ifselected such that sampling occurs during the valid phase low-frequency noise willbe reduced quite a bit compared to the previous case.

C.2 Operating Point Information

Spectre provides operating point information which can be used to gain knowledgeabout the value of many transistor parameters during the DC simulation. Inform-ation about the meaning of the various outputs can be found by using Spectre's

122


help function, if the bsim4 model is used the pertinent information can be foundby typing spectre -h bsim4 in a terminal window.

C.2.1 Saving Operating Point Information During a DC Sweep

Operating point data is not stored automatically during DC sweeps. If one requiresthis information to be stored - for example to determine which operating pointsvarious transistors are in for various DC points - then one should create a textle with instructions for which parameters to save. As an example the followingwill cause the information about Vgs, Vds and the operation region to be saved fordevices M3 and M6:

save M3:vgs save M3:vds save M3:region

save M6:vgs save M6:vds save M6:region

Once created, this text le should be added to the model libraries by selectingSetup ä Model Libraries. . . in the ADE window.

C.2.2 Region

The region output provides information about which operating region a transistorwas in during the DC simulation. The numbers obtained from this output mapsto operation regions in the following way:

0. Cuto

1. Linear

2. Saturation

3. Subthreshold

4. Breakdown

C.2.3 gm/Id and V*

Spectre makes gm/Id available as part of the operating point information for eachdevice under the name gmoverid. It can be accessed in many ways, for exampleusing the results browser where it is found under dcOpInfo ä <device name> ä

gmoverid or through selecting OPT ä <device> ä gmoverid using the calculator.It is also possible to use OPT("/<device name>","gmoverid") in any place thataccepts OCEAN commands, e.g. in the calculator or in the ICFB window.

V ∗ may be accessed by noting that (8) can be rewritten on the form

V ∗ :=2

gm/Id(49)

and e.g. adding expressions performing this calculation for each device of interestto the ADE outputs.

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D Code

D.1 Sage-Code to Calculate Proper Resistance-Segment Siz-ings For Programmable Resistors

# 3-segment case. Numbered Rs are target resistances that we wish to get

# from the different settings, lettered Rs are the to-be-calculated

# resistances of each segment. Note that we are always adding on more

# resistance for each Rn so for the solutions to make sense R1 must be

# smaller than R2 and so on:

def par(x,y):

return x*y/(x+y)

R1=25e3

R2=50e3

R3=250e3

Rsw=273

Ra,Rb,Rc = var('Ra Rb Rc')

sol=solve([Ra+par(Rb,Rsw)+par(Rc,Rsw)==R1,Ra+Rb+par(Rc,Rsw)==R2,Ra+Rb+Rc==...

R3], Ra,Rb,Rc)

print sol

for a in sol:

print "Solution set:"

for b in a:

print b.lhs()

print b.rhs().n()

print ""

124


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