Concurrent Test Generation
description
Transcript of Concurrent Test Generation
Dec. 19, 2005 ATS05: Agrawal and Doshi 1
Concurrent Test Generation
Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA
Vishwani D. AgrawalAlok S. Doshi
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Problem Statement
• To find the smallest test set to detect all single stuck-at faults in a combinational circuit.
• An existing solution:– Group faults into fault sets using fault independence– Generate concurrent tests for each group
• Contribution of this paper: Devise a simulation-based implementation for this solution.
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Outline
• Introduction
• Simulation-based Independence Fault Collapsing
• Simulation-based Concurrent Test Generation
• Results
• Conclusions
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Introduction
v1v2v3. . .T(F1) T(F2)
Problem of finding a minimal test:• Static compaction cannot guarantee optimality.• Dynamic compaction is complex.
• Solution: Target both faults F1 and F2 at the same time to find a single test. We define this as concurrent test generation.
Test set for fault F1 Test set for fault F2
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Fault Classification
F1 and F2 are equivalent. F1 dominates F2.
F1 and F2 are independent. F1 and F2 are concurrently testable.
T(F1) = T(F2)
T(F1)
T(F2)
T(F1) T(F2) T(F2)T(F1)
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Example Circuit2
4
1
6
8
73
9
5
10
11
a
b
cd
e
x
y
C17 - ISCAS85 Benchmark Circuit
1 R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits,” Proc. Design, Automation and Test in Europe (DATE) Conf., Mar. 2005, pp. 1014 - 1019.
All faults areStuck-at-1 type
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Independence Matrix and Graph
1 2 3 4 5
6 7 8 9 1 0
11
C17 - ISCAS85 Benchmark Circuit
F 1 2 3 4 5 6 7 8 9 10 11
1 0 1 1 1 1 1 0 0 1 0 1
2 1 0 0 1 1 0 1 0 0 0 1
3 1 0 0 0 1 1 1 1 0 1 1
4 1 1 0 0 1 0 1 0 0 0 1
5 1 1 1 1 0 0 0 1 1 1 0
6 1 0 1 0 0 0 1 1 1 0 0
7 0 1 1 1 0 1 0 1 1 0 0
8 0 0 1 0 1 1 1 0 1 1 1
9 1 0 0 0 1 1 1 1 0 1 1
10 0 0 1 0 1 0 0 1 1 0 1
11 1 1 1 1 0 0 0 1 1 1 0
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Independence Fault Collapsing
1,8 5,11,7
3,9,2 4,6,10
2 A. S. Doshi and V. D. Agrawal, “Independence Fault Collapsing,” Proc. 9th VLSI Design and Test Symp., Aug. 2005, pp. 357 - 364.
C17 - ISCAS85 Benchmark Circuit
A “similarity” based algorithm [2] collapses the independence graph:
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Simulation-based Independence Fault Collapsing
2 A. S. Doshi and V. D. Agrawal, “Independence Fault Collapsing,” Proc. 9th VLSI Design and Test Symp., Aug. 2005, pp. 357 - 364.
• The independence graph generation procedure [2] requires ATPG.
• Here we present a new method for graph generation using simulation:– Start with a fully-connected independence graph
for an equivalence collapsed fault set.– Simulation of random vectors without fault
dropping removes edges between faults detected by the same vector.
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Simulation-based Independence Fault Collapsing
74181 4-bit ALU
301
0
25000
50000
75000
100000
0 500 1000 1500 2000 2500
Random Vectors
Nu
mb
er o
f ed
ges
0
80
160
240
320
Fau
lts
Det
ecte
d
90601 Fault Coverage (293)
Number of edges in graph (20004)
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Simulation-based Concurrent Test Generation
• For each group, generate all test vectors for the first fault in the group.– If the number of test vectors for a fault is large, use
a subset (e.g., 250 maximum) of vectors.
• Simulate all faults in the group to select one vector that detects most faults in that group.– If more vectors than one detect the same number
of faults within the group, then select the vector that detects most faults outside the group as well.
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74181 4-bit ALU ResultGroup number Number of faults in group Concurrent test vector
1
2
3
4
5
6
7
8
9
10
11
12
13
9
15
11
6
11
17
11
16
16
22
22
56
81
01100011111100
01101100000110
10100101111010
11011010100000
10110101011010
10100111101010
10010101001110
01000111101011
11100010010011
11011100110100
01010001100001
All 56 faults detected by eleven
previously generated vectors
10101001110110
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* Sun Ultra 5 *** Pentium Pro PC ** Hamzaoglu and Patel, IEEE-TCAD, 2000
Results
CircuitNo. of
concurrent groups
Concurrent ATPG Single-fault ATPG
Vectors CPU s*
Atalanta Best known
Vectors CPU s* Vectors CPU s***
1-b adder2-b adder4-b adder8-b adder
16-b adder32-b adder4-b ALU
c17c432c499c880
c1355c1908c2670c3540c5315c6288c7552
555777
134
30522484
10681
1079223
190
55579
11124
34522984
11192
13010425
198
0.0850.0920.1030.182
3.39.7
11.40.08210.414.623.334
49.6 57.6
119.6216.3158.1360.7
5-77-9
8-1110-1513-2217-2522-40
6-949-7754-68
52-10685-109
118-173106-192147-263114-224
32-48209-358
0000
0.0170.0500.033
00.0830.0330.133
0.10.51.21.9
0.7334.7
5.283
555555
124
27**52**16**84**
106**44**84**37**12**73**
--------
150.1
21.90.9
88.147.1
174.5748.6347.7663.8
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Number of Vectors for Increasing Circuit Sizes (100% Stuck-at Coverage)
0
50
100
150
200
250
300
350
400
minconc-ATPGsf-ATPG
Single-fault ATPG(no compaction)
Concurrent ATPG
Minimum achieved!(dynamic compaction)
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CPU Seconds for Increasing Circuit Sizes (100% Stuck-at Fault Coverage)
0
100
200
300
400
500
600
700
800
minconc-ATPG
Concurrent ATPG
Minimum achieved!(dynamic compaction)
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Conclusion• Concurrent test generation produces compact tests
when combined with independence fault collapsing.• ATPG and set covering problems have exponential
time complexities. Hence, we cannot expect absolute optimality for large circuits.
• The concurrent ATPG procedure of this paper gives significantly smaller, and sometimes the optimum, test sets.
• There is scope for improving the simulation-based algorithms for independence fault collapsing and concurrent test generation.
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Thank You!