COMPUTER ARCHITECTURE (P175B125) Assoc.Prof. Stasys Maciulevičius

COMPUTER ARCHITECTURE

(P175B125)

Assoc.Prof. Stasys Maciulevič[email protected]

mailto:[email protected]





©S.Maciulevičius 22013

Input/output

We will define input/output as a subsystem of components that moves coded data between external devices and a host system, consisting of a CPU and main memory.

I/O subsystems include, but are not limited to: Blocks of main memory that are devoted to I/O functions Buses that provide the means of moving data into and out of

the system Control modules in the host and in peripheral devices Interfaces to external components such as keyboards and disks Cabling or communications links between the host system and

its peripherals


Computer and its I/O devices

CPU

Cache

Main memory

I/O bus

I/O controller

HD HD

I/O controller

I/O controller

Graphicunit LAN

Interrupt requests


Input/output problems

The possibility to connect various peripheral devices

Performing of input/output operations parallel with operations in processor

Maximally simplified programming of input and output processes

The response to various emergency situations and problems in peripheral equipment


Problem-solving ways

Modularity of peripheral equipment (constructive completeness, a simple connection)

Uniform data formats Unified interface Unified instruction formats and types


Interrupts

Much of the functionality embedded inside a computer is implemented by hardware devices other than the processor

Since each device operates at its own pace, a method is needed for synchronizing the operation of the processor with these devices

There are two basic ways that the processor could do this: Polling: The processor could take turns going to each device and

asking if they have anything they need it to do. This is called polling the devices

Interrupting: The other way that the processor can handle information transfers is to let the devices request them when they need its attention. This is the basis for the use of interrupts


Polling

First, it is very wasteful in terms of processing power, since the processor is constantly busy reading the status of the attached devices instead of executing some useful code

Second, when the rate of data transfer is extremely high, the processor might lose data bytes arriving from the hardware devices


Interrupting

Instead of polling hardware devices to wait for their response, each device is responsible for notifying the processor about its current state

When a hardware device needs the processor's attention, it simply sends an electrical signal (hardware interrupt) through a dedicated pin in the interrupt controller chip (located on the computer's motherboard)


Interrupts

A message from one part of the computer to another (normally to the system processor) that tells it that it needs to stop what it is doing, and do something else instead is called interrupt

An IRQ is an interrupt request, and is the name for the actual signal that is used when a peripheral requests an interrupt of the processor

In addition to the hardware interrupts, there are also software interrupts. These are used by various software programs in response to different events that occur as the operating system and applications run


Interrupts

Interrupting (Interrupt handling) programs

Interrupt requests

Main program

Processor

Environment


Interrupt types

External interrupts (asynchronous to current process): • hardware faults (power, …)• timer• other processes or processors• processes in external devices• user, operatorInternal interrupts – exceptions (synchronous to current

process): • addressing errors• operand errors (/0, …)• operation errors (overflow, …)• invalid operation• mode changing


Interrupt types

Software interrupts (synchronous to current process): • software interrupts (for testing) • debugging interrupts

Switching to interrupt handling : • after completing of inctruction (most often)• during execution of inctruction (rarely)• when execution fails (e.g., page fault)Interrupt handling: • at microprogram level (rarely)• at program level (most often)


Interrupts

Parameters:• number of request lines• response time• switching time• nesting

Main progr.IRQInterrupt handlingResponse

Switchingtime (latency) time


Interrupt levels

321

321

3

22

11

Requests

Single levelsystem

Multi levelsystem

Interrupt priority levelsInterrupt handling order:


Interrupt handling

Interrupt handling procedure:• reception of an interrupt signal• interrupt identification • saving current program state• exexuting of interrupting (interrupt handling)

program• restoring saved program state


Interrupt handling

When a device asserts its interrupt request signal, it must be processed in an orderly fashion

All CPUs, and many devices, have some mechanism for enabling/disabling interrupt recognition and processing: At the device level, there is usually an interrupt control

register with bits to enable or disable the interrupts that device can generate

At the CPU level, a global mechanism functions to inhibit/enable (often called the global interrupt enable) recognition of interrupts


Interrupt handling

Systems with multiple interrupt inputs provide the ability to mask (inhibit) interrupt requests individually and/or on a priority basis. This capability may be built into the CPU or provided by an external interrupt controller. Typically, there are one or more interrupt mask registers, with individual bits allowing or inhibiting individual interrupt sources

There is often also one non-maskable interrupt input to the CPU that is used to signal important conditions such as pending power fail, reset button pressed


Interrupt handling in IBM/360

Int.request (2 class)

New PSW

1

2

3

4

5

Interrupting program

Old PSW

1

2

3

4

5

Interrupted program

Interrupted program

Status storing

Program

Status restoring

PSW register1

2

5

6

3

4


Interrupt controller

The interrupt controller serves as an intermediate between the hardware devices and the processor

Its responsibility is to alert the processor when one of the hardware devices needs its immediate attention

In this case, the processor stops its current activity and jumps to execute a function (interrupt handler) which was previously associated with the calling device (or more accurately, associated with the interrupt vector of the device)


Interrupt controller (Intel)

The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU

It is cascadable for up to 64 vectored priority interrupts without additional circuitry

The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts.


Interrupt controller (Intel)INTA INT

D7 - D0

IR0IR1IR2IR3IR4IR5IR6IR7

Control logic

Interrupt request register(IRR)

Prioritety resolver

Interrupt service register(ISR)

Interrupt mask register(IMR)

Data bus buffer

Read/ Write logic

Kaskadinio jungimo

valdymas

RDWRA0

CS

CAS0

CAS1

CAS2

SP/EN


Interrupt controller

IOWCIORCINTA

IRQ lines

Data bus

Address selector

Address bus

To CPU

For cascading

CS A0 INT D7-D0

WR

RD 8259A CASINTA

IR0 IR7


Interrupt controllers in PC/AT

IR0IR1 INTIR2…IR7 CAS

Perif.device 02

Perif.device 03

Perif.device 09

Perif.device 10

Perif.device 11

Perif.device 15

IR0IR1 INTIR2IR3IR4IR5IR6IR7 CAS

NMIINTR

Master8259A

Slave8259A

Processor

Perif.device 00

Perif.device 01

PC/XT computers have only one chip 8259A PC/AT computers have two chips 8259A,

cascadded as follows:


Interrupt vector An interrupt vector is the memory address of an

interrupt handler, or an index into an array called an interrupt vector table

Interrupt vector tables contain the memory addresses of interrupt handlers. When an interrupt is generated, the processor saves its execution state via a context switch, and begins execution of the interrupt handler at the interrupt vector

OS Vectors occupied by the master 8259A

Vectors occupied by the slave 8259A

DOS 8h - Fh 70h - 77hWindows 95 / 98 50h - 57h 58h - 5Fh

Windows NT 30h - 37h 38h - 3Fh


Exceptions

Exceptions belong to a special type of software interrupts

They are generated by the processor itself whenever some unexpected critical event occurs

For instance, a page fault exception (interrupt 14) is triggered when the processor attempts to access a page, which is marked as not-present. The exception handler can then reload the page from disk (virtual memory) and restart the instruction which generated the exception


Exceptions

Three types of exceptions can be generated by the processor: faults, traps and aborts When a fault exception occurs, the CS and (E)IP registers

which are pushed on the stack, point to the address of the instruction, which generated the exception. This gives the exception handler a chance to fix the condition which caused the exception to occur, before restarting the faulting instruction

Traps are similar to interrupts in the sense that they make the processor push the address of the next instruction to the stack

Aborts neglect to specify the location of the faulting instruction, since they are usually used to indicate severe errors (such as hardware errors or illegal system tables) which are not recoverable


Some exceptions (in real-mode)

Exception Vector Condition Division by

Zero 0 Attempting to execute a DIV or an IDIV instruction with a divisor which equals zero.

Debug / Single Step 1

Used in conjunction with the debug registers to indicate a breakpoint hit. The processor also issues this interrupt after executing every instruction when the TRAP flag is set

Overflow 4When performing arithmetic instructions with signed operands, the processor set the OF flag to indicate an overflow. The INTO instruction tests this flag and if it is set - generates an exception

Invalid Opcode 6

Occurs when the processor executes one of the reserved opcodes or uses the LOCK prefix improperly. Can also indicate an invalid operand following an opcode


Addressing of peripheral equipment and I/O instructions

a) separate address space (PDP)b) overlapping address spaces

Instructions:a) move – universal (both for memory access and

peripheral equipment)b) load/store - for memory access, in/out - for

peripheral equipment access


Transfer of information

The transfer of information between the processor and a peripheral consists of the following steps:1. Selection of the device and checking the

device for readiness2. Transfer initiation, when the device is ready3. Information transfer4. Conclusion


General I/O structure

Memory

CPU

Address bus

Data busControl and status

Device 1

Interface

Device 2

Interface

Device n

Interface

Deviceselectionlines


Device interface

A device interface is unique to a particular device since each device is unique with respect to its data representation and read-write operational characteristics

The major functions of a device interface are Timing Control Data conversion Error detection and correction


Device interface

The timing and control aspects correspond to the manipulation of control and status signals to bring about the data transfer

In addition, the operating speed difference between the CPU and the device must be compensated for by the interface

In general, data conversion from one code to the other is needed, since each device (or the medium on which data are represented) may use a different code to represent data

Errors occur during transmission and must be detected and if possible corrected by the interface


Device interface

Decoder(selector) Status Buffer

TransducerData

Binarydata

Commands Status

Device

Deviceselection

Control(from CPU)

Status(to CPU)

Datalines

DevicecontrollerControl


Device interface

Device selection is performed by address decoding

The transducer converts the data represented on the I/O medium (tape, disk, etc.) into the binary format and stores it in the data buffer, if the device is an input device

In the case of an output device, the CPU sends data into the buffer and the transducer converts this binary data into a format suitable for output onto the external medium


Programmed I/O

a) unconditional I/O b) conditional I/O

in/out port

in/out port

Ready? No

Yes

Port – address of peripheral device


Programmed I/O

c) interrupt mode I/O

Main program

Preparation of interrupt system

Exchange subpro-

gramINTR

INTR

...

Preparation of information exchange


Ports

Input port – any data source that can be selected performing the input command

Output port – any data receiver that can be selected performing the output command

Port addresses are sent through the address bus (or part of it)


I/O channels

I/O channel is a generic term that refers to a high-performance input/output architecture that is implemented in various forms on a number of computer architectures, especially on mainframe computers

In the past they were generally implemented with a custom processor, known alternately as I/O processor or peripheral processor


Classic: IBM I/O channels

Processor

I/O channelMain

memory I/O controller


I/O channel

A channel is an independent hardware component that coordinates all I/O to a set of controllers or devices

The CPU of a system that uses channel I/O typically has only one machine instruction for input and output; this instruction is used to pass input/output commands to the specialized I/O hardware in the form of channel programs

I/O thereafter proceeds without intervention from the CPU until an event requiring notification of the operating system occurs, at which point the I/O hardware signals an interrupt to the CPU


I/O channel

Each channel may support one or more controllers and/or devices

A channel program is a sequence of I/O instructions executed by the input/output channel processor in the IBM System/360 and subsequent architectures

The channel program consists of one or more channel command words

A channel command word (CCW) is an instruction for a specialized I/O channel processor


Main functions of I/O channel to address the data array in memory to set the length of data array to form memory addresses to calculate volume of data transmitted to determine the end of I/O operation to buffer data during tansfer to change data formats to minimize the processor participation in I/O to form interrupt requests to transfer information about the status of

peripheral device


Direct memory access (DMA)

The programmed and interrupt mode I/O structures transfer data from the device into or out of a CPU register

Direct memory access (DMA) is a feature of modern computers and microprocessors that allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of the CPU

Many hardware systems use DMA including disk drive controllers, graphics cards, network cards, and sound cards


Direct memory access

CPU executes

some process

CPU inicializes DMA, setting

DMA controller

DMA controls

dataexchange

INTR

...

Cyc- le

ste-aling



The sequence of events during a DMA transfer:1. CPU initializes DMA controller, setting AR (Address

Register), WCR (Word Count Register) and sends to DMA controller command to start data transmission; continues processing

2. If WCR0, DMA controller gathers data; when word is ready for transfer, holds CPU (i.e., “steals” a memory cycle); if WCR=0, sends transfer-complete interrupt to CPU



3. CPU continues with any processing that does not need a memory access; if memory access is needed, tries to acquire a memory cycle if DMA controller is not accessing the memory

4. DMA controller transfers data; releases the memory; decrements WCR; increments AR; goes to step 2

DMA controllers can be either dedicated to one device or shared among several input/output devices


DMA controller

Standard DMA transfers are managed by the DMA controller, built into the system chipset on modern PCs

The original PC and XT had one of these controllers and supported 4 DMA channels, 0 to 3

Starting with the IBM AT, a second DMA controller was added


DMA controller (8237A)

0 channelData bus

buffer

1 channelControl unit

2 channelMode control

block

3 channel

TR(16)

CR(8)SR(8)

RR(4)

MASK(4)

CAR (16)BAR (16)

CWR (16)

MR (6)

WCR (16)

DREQ0

DACK0

D

Control signals

DREQ1

DACK1DREQ2

DACK2

DREQ3

DACK3


Registers and modes

Registers: CR – Command Register SR – Status Register CAR – Current Address Register BAR – Basic Address Register CWR – Current WordCount Reg. WCR – Basic WordCount Reg. SR – Request Register MASK – Mask Register


DMA operation

The multimode DMA controller issues a HRQ to the processor whenever there is at least one valid DMA request from a peripheral device. When the processor replies with a HLDA signal, the 8237A takes control of the address bus, the data bus and the control bus

The address for the first transfer operation comes out in two bytes - the least significant 8 bits on the eight address outputs and the most significant 8 bits on the data bus

The contents of the data bus are then latched into an 8-bit latch to complete the full 16 bits of the address bus


DMA operation modes

DMA service will take place in one of four modes: Single Transfer Mode. In Single Transfer mode the device is

programmed to make one transfer only. The word count will be decremented and the address decremented or incremented following each transfer. When the word count ``rolls over'' from zero to FFFFH, a Terminal Count (TC) will cause an Autoinitialize if the channel has been programmed to do so

Block Transfer Mode. In Block Transfer mode the device is activated by DREQ to continue making transfers during the service until a TC, caused by word count going to FFFFH, or an external End of Process (EOP) is encountered


DMA operation modes

Demand Transfer Mode. In Demand Transfer mode the device is programmed to continue making transfers until a TC or external EOP is encountered or until DREQ goes inact. Thus transfers may continue until the I/O device has exhausted its data capacity

Cascade Mode. This mode is used to cascade more than one 8237A together for simple system expansion. The HRQ and HLDA signals from the additional 8237A are connected to the DREQ and DACK signals of a channel of the initial 8237A. This allows the DMA requests of the additional device to propagate through the priority network circuitry of the preceding device


Cascading

CPU

8237ADREQDACK

HRQHLDA

DREQDACK

8237AHRQHLDA

8237A

HRQHLDA

Slaves

Master

COMPUTER ARCHITECTURE (P175B125) Assoc.Prof. Stasys Maciulevičius

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