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COMPARISON OF ADAPTIVE VOLTAGE/FREQUENCY SCALING AND ASYNCHRONOUS PROCESSOR ARCHITECTURES FOR NEURAL...
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Transcript of COMPARISON OF ADAPTIVE VOLTAGE/FREQUENCY SCALING AND ASYNCHRONOUS PROCESSOR ARCHITECTURES FOR NEURAL...
![Page 1: COMPARISON OF ADAPTIVE VOLTAGE/FREQUENCY SCALING AND ASYNCHRONOUS PROCESSOR ARCHITECTURES FOR NEURAL SPIKE SORTING J. Leverett A. Pratt R. Hochman May.](https://reader035.fdocuments.net/reader035/viewer/2022062421/56649cec5503460f949b8489/html5/thumbnails/1.jpg)
COMPARISON OF ADAPTIVE VOLTAGE/FREQUENCY SCALING AND ASYNCHRONOUS PROCESSOR ARCHITECTURES FOR NEURAL SPIKE SORTING
J. L
ever
ett
A. Pratt
R. H
ochm
an
May 2013 – EE241 Final Project
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Introduction to ‘Spikes’Frequency Range 10-500Hz
Duration 3-5ms
Resolution 8-bit
‘Spikes,’also called ‘action potentials,’ are when the electrical potential of a neuron rises shortly. It is part of the communication protocol of the brain.
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Spike Sorting Systems
• Operate at constant 37°C • Extremely low power• Extremely low area
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Purpose Statement
Adaptive Voltage and Frequency Scaling Asynchronous Timing
vs.
Determine the conditions
• under which adaptive voltage and frequency scaling provides a better power performance than asynchronous timing in a neural spike processor.
• under which asynchronous timing provides a better power performance than adaptive voltage and frequency scaling in a neural spike processor.
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Theory• E = I*VDD*t• If you can decrease voltage and/or current faster than the increase in delay for an operation, you save
energy.• Asynchronous circuits process data at the same energy ‘every time.’ • When data rates are low, I and VDD may be reduced such that the energy per spike of a synchronous
solution is lower than the asynchronous solution.• The issue is that at some point, leakage current dominates, making increased operating time
undesirable.
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Verilog Function
• Detection of the largest value in a spike and the point at which it occurs facilitates spike sorting.
• Sorting spikes on chip results in a reduced amount of transmitted data.
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Synchronous Logic
?
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Prior Art
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Asynchronous Logic
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Data Collection Methodology
Determination of max. frequency and E vs. VDD.
Known Simplifications• Process Corners• Entire Verification Space• Noise/Margins• Critical Path Monitors• Adaptive control circuitry
Synthesis
Place and Route
.sp netlist
E vs. f Data
Verilog Cadence hSpice Matlab
sim
sim
sim
LVS sim
*RC
Parasitic extraction
Logic
Demonstrations of functionalitywith synch and asynch.
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Spice Data: Energy/Op vs. Frequency
Asynchronous:300 less MOSFETS>5000 less Rs and Cs
At 20kHz: Synch: 1.9E-9A – 7.6pJ Asynch: 1.71E-9A, 6.8pJ
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Spice Data: Current Breakdown - Synchronous
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Assumptions• Process Corners
• Only used TT as effects should be linear on both architectures.
• Verification Space• Test vector data was designed to be representative, not the worse
case scenario. Testing across a wide range of frequencies and voltages is an open problem.
• Noise/Margins• Assumed no noise for this analysis. Noise should hurt both circuits
equally.
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• Subthreshold critical path monitors are highly sensitive to PVT both globally and locally.
• Current is exponential with changes in , , and T.
• Implies a currently unachievable level of specificity.
• First order approximation might be to double energy.
Critical Path Monitor
Adaptive Control Circuitry, Clock, + Vdd •Assuming that the adaptive frequencies are less than the global clock, we can implement the change in frequency with a clock divider (counter).
•Voltage scaling circuitry would take the global supply and reduce it using one of many possible techniques. –Linear Regulators: Inefficient for large changes in voltage.–Capacitive Regulator: Results in supply ripples.–Magnetic Regulator: Highest efficiency, but requires external parts
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Matlab: Transient State Machine at .5MHz
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Matlab: Transient State Machine at .6Mhz
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Matlab: Transient State Machine at 5Mhz
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Matlab: Total Energy + Vdd vs. Event Frequency
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Conclusion• Asynchronous logic operates at a higher frequency for all
supply values than the synchronous version. Similarly, for an equal operating frequencies, asynchronous can operate at a lower VDD.
• For the speed of a neural processor, both circuits operate at the lowest supply voltage and leakage current dominates. There is no means to perform adaptive analysis.
• In an application where incoming data frequency is on the order of magnitude of the intrinsic asynchronous circuit operating frequency, the adaptive circuit requires less energy, as long as the average voltage required of the adaptive circuit is less than the intrinsic voltage of the asynchronous circuit.
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References and Acknowledgements
Acknowledgements: Brian Zimmer, Nathan Narevsky, Jan Rabaey, Stevo Bailey, Tsung-Te Liu, Bora Nikolic
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APPENDIX
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Spice Data: Power vs. Max Operating Freq.