COMP541 Memories - I
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Transcript of COMP541 Memories - I
1
COMP541
Memories - I
Montek Singh
Oct {8, 15}, 2014
Topics Lab 8
Briefly discuss RAM specification in Verilog
Overview of Memory TypesRead-Only Memory (ROM): PROMs, FLASH, etc.Random-Access Memory (RAM)
Static todayDynamic next
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Verilog for RAM (Lab 8)module ram_module #( parameter Abits = 4, // Number of bits in address parameter Dbits = 4, // Number of bits in data parameter Nloc = 16 // Number of memory locations)( input clock, input wr, // WriteEnable: if wr==1, data is written into mem input [Abits-1 : 0] addr, // Address for specifying location input [Dbits-1 : 0] din, // Data for writing (if wr==1) output [Dbits-1 : 0] dout // Data read from memory (all the time) );
reg [Dbits-1 : 0] mem [Nloc-1 : 0];// The actual registers where data is stored// Memory write: only when wr==1 and clock tick
always @(posedge clock) if(wr) mem[addr] <= din;
assign dout = mem[addr]; // Memory read all the time, no clock involved
endmodule
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Types of Memory Many dimensions
Read Only vs. Read/Write (or write seldom)Volatile vs. Non-VolatileRequires refresh or not
Look at ROM first to examine interface
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Non-Volatile Memory Technologies Mask (old) ROM
read-only memory Fuses (old) PROM
programmable read-only memory Erasable EPROM
erasable programmable read-only memory Electrically erasable EEPROM
electrically-erasable programmable read-only memory today called FLASH!
used everywhere!
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Details of ROM Memory that is permanent
k address lines2k itemsn bits
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Notional View of Internals
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Programmed Truth Table
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Resulting Programming
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Mask ROMs Oldest technology Originally “mask” used as last step in
manufacturingSpecify metal layer (connections)Used for volume applicationsLong turnaroundUsed for applications such as embedded systems and,
in the old days, boot ROM
but cheap to mass produce!
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Programmable ROM (PROM) Early ones had fusible links
High voltage would blow out linksFast to programSingle use
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UV EPROM Erasable PROM
Common technologies used UV light to erase complete device
Took about 10 minutesHolds state as charge in very well insulated areas of
the chipNonvolatile for several (10?) years
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EEPROM Electrically Erasable PROM
Similar technology to UV EPROMErased in blocks by higher voltageProgramming is slower than reading
Today’s flavor is called “flash memory”Digital cameras, MP3 players, BIOSLimited lifeSome support individual word write, some block
Our boards have it:A flash memory chip on our Nexys boardsHas a “boot block” that is carefully protectedWe will learn to use it in upcoming labs
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How Flash Works Special transistor with floating gate This is part of device surrounded by insulation
So charge placed there can stay for yearsAside: some newer devices store multiple bits of info
in a cell
Interested in this? If so, we can cover in more detail w/ transistors
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Read/Write Memories Flash is obviously writeable
But not meant to be written rapidly (say at CPU rates)And often writing must be by entire blocks (disk
replacement)
For frequent writing, use RAM
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Random Access Memories So called because it takes same amount of
time to address any particular locationNot entirely true for modern DRAMs, but somewhat
true…
First look at asynchronous static RAM reading and writing typically controlled by
“handshakes”clock may still be present, but actions controlled by
handshake signals
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Simple View of RAM Typical parameters:
some word size nsome capacity 2k
k bits of address line
Need a line to specify reading or writing typically only one wire needed
sometimes two separate ones
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Example: 1K x 16 memory RAM comes in variety of
sizes from 1-bit widemain issue is no. of pins
available on chip
Memory size often specified in bytesThis would be 2KB memory10 address lines (=1K
locations)16 data lines (=2
bytes/location)
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Writing Sequence of steps
Set up address linesSet up data linesActivate write line (e.g., maybe a positive edge)
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Reading Steps
Setup address linesActivate read lineData available soon
for asynchronous memory: after simply a specified amount of time
for synchronous memory: after a clock edge
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Chip Select Enable:
Usually a line to enable the chipWhy?
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Timing: Writing
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Timing: Reading
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Static vs. Dynamic RAM Different internal implementations: SRAM vs.
DRAMDRAM:
DRAM stores charge in capacitorDisappears after short period of timeMust be refreshedSmall sizeHigher storage density larger capacities
SRAM:SRAM easier to useUses transistors (think of it as latch)FasterMore expensive per bitSmaller sizes
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Structure of SRAM Internally, each bit stored in a “latch”
One memory cell per bitCell consists of a few transistorsNot really a latch made of NANDs/NORs, but logically
equivalentBehaves like an SR latch
Control logicalso need extra logic around the latch to make it work like
a memory cell
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Structure of SRAM Several optimized circuits often used
replace a full-fledged SR latch with something simpler, smaller, faster…Not really a latch made of NANDs/NORs, but logically
equivalentBehaves like an SR latch
e.g., a simpler 6-transistor memory cellwordline Select(bitline, bitline’) (B, B’) as well as (C, C’)
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wordline
bitline bitline
Example: A Simple Organization Note:
In reality, more complexOnly one word-line is “on” at a time
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wordline311
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2:4Decoder
Address
01
00
storedbit = 0
wordline2
wordline1
wordline0
storedbit = 1
storedbit = 0
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
storedbit = 0
storedbit = 0
storedbit = 1
storedbit = 1
bitline2 bitline1 bitline0
Data2 Data1 Data0
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Zoom in: A single bit slice Operation:
Cells connected to form 1 bit position (column)
Word Select enables one latch from address lines
only this cell is writable only this cell is read
B (and B’) set by: Read/Write’ Data In Bit Select
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Let’s look at a single bit cell
stored bit
wordline
bitline
Example:
stored bit = 0
wordline = 1
stored bit = 1
stored bit = 0
stored bit = 1
bitline =
(a) (b)
wordline = 1
wordline = 0
wordline = 0
bitline =
bitline =
bitline =0
1
Z
Z
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Bit Slices and Modules Entire column of cells
called a bit slicebasically a 1-bit wide
memory! Module
module refers to a single chip of memory
1-bit wide memory chips are quite common!
Inside an SRAM Bit Cell Actual implementation does not use a real SR
latch!a tinier approximation is used logically behaves very much like an SR latchbut much smaller and faster!
stored bit
wordline
bitline
wordline
bitline bitline
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16 X 1 RAM “Chip”
Now shows address decoder selects
appropriate location
Row/Column Layout For larger RAMs:
decoder becomes pretty bigalso run into chip layout issues
Typically: larger memories use “2D” matrix layoutsee next slide
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16 X 1 RAM as 4 X 4 Array
Two decodersRowColumn
Address just broken up
Not visible from outside on SRAMs
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Not the same as 8 X 2 RAM! Minor change in
logic and pinsSpot the difference!
Spot the difference!
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Realistic Sizes Example: 256Kb memory organized 32K X 8
Single-column layout would need 15-bit decoder with 32K outputs!
Better organization:A 2D (i.e., square) layout with:
9-bit row and 6-bit column decoders
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SRAM Performance Latency and Throughput important
Current ones have cycle times in low nanosecondssay 1-2ns (top-end ones even lower)
Used as cache (typically on-chip or off-chip secondary cache)
Sizes up to 8Mbit or so for fast chipsExpensive ones can go a bit bigger
Energy/powerSRAMs also better for low power vs. DRAMs
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Wider Memory What if you don’t have enough bit width?
use multiple chips and side-by-side
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Larger/Wider Memories Made up from sets of
chips Consider a 64K by 8
RAMour building block
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Larger Let’s build a larger
memory256K X 8Decoder for high-order 2
bitsSelects chipLook at selection logicAddress ranges
Tri-state outputs
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Summary Today we looked at:
Quick look at non-volatile memoryStatic RAM
Next topic:Dynamic RAM
Complex, largest, cheapMuch more design effort to use
Talk about memories for lab
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