Combinational Logic

Computer Organization Ellen Walker

Hiram College

Figures from Computer Organization and Design 3ed, D.A. Patterson & J.L. Hennessey, Morgan Kauffman © 2005 unless otherwise specified

Types of Logic

•  Combinational Logic –  Outputs depend only on inputs –  Outputs change (after delay) as inputs change

•  Sequential Logic –  Outputs depend on inputs and memory (including

previous output) –  Memory values called state –  Outputs (and state) change synchronously based

on a clock signal

Truth Tables

•  Completely describe combinational logic •  Column for each input and output •  Row for each possible combination of

inputs – For n inputs, there are 2^n entries

Truth Table Example A B C A * B A * (B+C) 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1

Primary Boolean Operations

A B A * B

0 0 0

0 1 0

1 0 0

1 1 1

A B A + B

0 0 0

0 1 1

1 0 1

1 1 1

NOT (~) : ~0 = 1 and ~1 = 0 This is written as an overbar in the textbook

Axioms of Boolean Algebra

•  Identity A+0=A, A*1=A •  Zero and One A+1=1, A*0=0 •  Inverse A+ ~A=1, A *~A=0 •  Commutative A+B=B+A, A*B=B*A •  Associative A+(B+C)=(A+B)+C

A*(B*C)=(A*B)*C •  Distributive A+(B*C) = (A+B)*(A+C)

A *(B+C) = (A*B) + (A*C)

DeMorgan’s Laws

•  The NOT operation is distributed through parentheses by – Negating every variable AND – Changing AND to OR and vice versa

•  ~(A+B) = ~A * ~B •  ~(A * B) = ~A + ~B

Logic Equation Examples

•  Consider 3 inputs A, B, C •  ANY: true if at least one is true

ANY = A+B+C •  MOST: true if two or more are true

MOST = (A*B)+(A*C)+(B*C) •  ONE: true if exactly one is true

ONE = ~A*~B*C + ~A*B*~C + A*~B*~C

Many Possible Equations

•  TWO: Exactly TWO of A,B,C are true TWO = A*B*~C + A*~B*C + ~A*B*C TWO = (A*B + A*C + B*C) * ~(A*B*C)

•  Can we prove these expressions are equivalent? – Yes, if their truth tables are identical – Yes, if we can find a sequence of axioms to

transform one to the other

Gates

•  Gates implement basic logic functions

and

nor

not

nand

or

Negation Shorthand

•  Bubble on input or output can replace a NOT gate

Implementing Equations Directly

•  Gates for + , * and bubbles for ~ •  Wires for inputs and outputs •  TWO = A*B*~C + A*~B*C + ~A*B*C

A B C

TWO

Another Implementation

•  TWO = (A*B + A*C + B*C) * ~(A*B*C) A B C

TWO

Truth Table to Gates

•  AND gate for every “1” in the output column – Bubble 0 inputs in the row, don’t bubble 1

inputs •  OR gate to connect rows together •  This is called Sum of Products

formulation

Example A B C X 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0

(~A*~B*~C) +

(~A*B*~C) + (~A*B*C) +

(A*B*~C)

Simplifying

•  Group together expressions with common elements

•  ~A~B~C + ~AB~C = ~A~C •  ~AB~C + ~ABC = ~AB •  ~ABC + ABC = BC

Simplified Circuit

Fewer gates and fewer inputs

Karnaugh Map

•  Rewrite truth table in a rectangular matrix

•  “Rows” with common subexpressions are adjacent

•  Find simplifications by circling adjacent 1’s – Circles can wrap around top/bottom

Kmap Example

A B C X 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0

1 0 1 1 0 0 0 1 A

C

B

4-Variable Kmap

•  Numbers indicate row of truth table

Example

•  4 variables represent 4 bits of a number representing an hour

•  Outputs are the 4 bits of the next hour (output for 1011 (11) should be 0000)

•  Outputs for 12, 13, 14, and 15 are don’t cares

•  Tool: KV-Diagram Applet

Important Building Blocks

•  Decoder – N inputs form a binary number – Corresponding bit from 2^N outputs is set

•  Multiplexor – 2^N “data” inputs, N “address” inputs – Corresponding bit from “data” is copied to

(single) output bit

3-to-8 Decoder Truth Table i2 i1 i0 o0 o1 o2 o3 o4 o5 o6 o7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1

3-to-8 Decoder Symbol

3 Decoder

out0

out7

…

Input line with slash is a “bus” - indicates 3 inputs bundled together

Multiplexor (2-bit selector)

•  Circuit to “select” one of its data inputs based on address inputs

•  Simplest multiplexor has 2 data inputs (A&B), 1 address (or selector) input Out = ~S * A + S * B

General Multiplexors

•  Build using N to 2^N decoder – Address bits are input to decoder – N AND gates, each gets 1 data input, and

corresponding decoder output –  OR gate connecting the AND gates

•  O = d0*i0+d1*i1+i2*i2+… – dj is j’th output of decoder –  ij is j’th input to the multiplexor

Multiplexor as Logic Implementor

•  For N inputs, use an N input multiplexor •  Address inputs are actual inputs to circult •  Data inputs fixed to corresponding outputs

from truth table •  Multiplexor “selects” the correct row of the

truth table, hence the correct output •  Any function can be implemented with 1

multiplexor (of the appropriate size)

Programmed Logic Array

•  A Programmed Logic Array implements Sum of Products form directly

•  AND gates (generate product terms) •  OR gates (combine product terms into

outputs) •  Since structure is so regular, build PLA

in silicon, use fuses to connect inputs to gates

PLA Example

And block

Or Block (only 1)

Read Only Memory

•  ROM is essentially many multiplexors working in parallel

•  Address bits (input) – Choose a memory location

•  Data bits (output) – Value of bits at that memory location

ROM Size

•  Width = number of bits per address (e.g. word size, number of data lines)

•  Height = number of addresses (e.g. words in memory) –  If there are N input (address) lines, the

height is 2^N •  Total number of bits stored = height x

width

Implementing a Function in ROM

•  Given N inputs, M outputs •  ROM

–  Height = –  Width =

•  Program each word in ROM with the outputs corresponding to that word’s address

•  Connect inputs to: •  Connect outputs to:

Reconfiguring ROMs

•  To create a “taller” ROM, use 2 ROMs and use the high-order address bit to control a MUX that chooses between their outputs. The other address bits go to both individual ROMS.

•  To create a “wider” ROM, use 2 ROMs and combine words from both to create a single wider word. The address bits go to both ROMS.

Building ALU

•  2 inputs •  Operation code •  Based on code, performs operation on

the given inputs

1-Bit Logic Unit

•  Operation Codes: 0=AND, 1=OR

1-Bit Adder

a

b

carry out

carry in

sum

1-Bit ALU (Add, And, Or)

•  Carry in & out lines •  Bigger Multiplexor for

opcode •  Data inputs to

Multiplexor: –  AND –  OR –  Adder

ALU with Subtraction

•  Ainvert, Binvert operate on negated inputs

•  For subtraction, set both CarryIn and Binvert to true

Preparing for SLT

•  SLT sets low-order bit to 1 if a<b –  Subtract a and b –  Copy sign bit to “Set” –  Output “Set” as result of low-order bit, 0 for all

other) •  Updates:

–  Less is now an input to ALU (1-bit register) –  Set is an output from MSB (only) –  MSB also computes overflow

ALU Bits

MSB Bits 0-30

32-Bit ALU with Zero Test

Adders

•  Ripple-carry adder – Carry N = An*Bn + An*Cn-1+Bn*Cn-1 – Delay is O(N) in number of bits

•  Fastest possible adder – Compute all of carries simultaneously – Delay = O(1) – Cost (hardware) proportional to # bits

Equations for Ideal Adder

•  Start with c1 (isolate c0) c1 = a0*b0+a0*c0+b0*c0 = a0*b0+(a0+b0)*c0

•  Same formula for c2, substitute c1 c2 = a1*b1+(a1+b1)*c1 = a1*b1+(a1+b1)*(a0*b0+(a0+b0)*c0)

•  Repeat for c3, substitute c2, etc.

Propagate and Generate

c2 = a1*b1+ (a1+b1)*(a0*b0+(a0+b0)*c0) •  Two factors repeat in each expansion •  Generate: gi = ai*bi

– Generates a new carry for bit i+1 •  Propagate: pi = ai+bi

– Propagates an existing carry for bit i+1

New Equation for Carry

•  Carry out (ci+1) happens if: – A new carry is generated (gi) – An existing carry is propagated (pi*ci)

•  Therefore, the equation for carry bit ci is: ci+1 = gi + pi*ci

Expanded Equation for 4 bits

•  c1 = g0 + p0*c0 •  c2 = g1 + p1*(g0+p0*c0)

= g1 + p1*g0+p1*p0*c0 •  c3 = g2 + p2*g1+p2*p1*g0 +

p2*p1*p0*c0 •  c4 = g3 + p3*g2 + p3*p2*g1 +

p3*p2*p1*g0 + p3*p2*p1*p0*c0

Trading off speed for hardware

•  Create a set of 4-bit adders that generate as outputs p4 and g4 (now known as Pi and Gi, where the index denotes which block) – Compute all 4 output bits, p4 and g4

simultaneously •  Add carry-lookahead logic that takes

the Pi and Gi values and generates the carry-in value for each 4-bit adder

16-bit Adder from 4-bit Blocks

How Much Speedup?

•  Instead of 32 x delay for 32 bits, we have 8 x delay (of the carry-lookahead unit)

•  The base delay might also have changed – compute sum, carry for one bit vs. compute

sum, P, G for 4 bits

Carry-Lookahead Adder

•  Compromise between ripple-carry adder and ideal (high-speed, much hardware) adder

•  Build a “carry-lookahead block” that takes