CMOS Sequential Circuit Design Lec.-1

7/27/2019 CMOS Sequential Circuit Design Lec.-1

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Sequencing the static and dynamic circuits.

Static circuits : gates that have no clock input,

examples: complementary CMOS, pseudo-nMOS,pass transistor logic.

Dynamic circuits :gates that have a clock input, e.g.

domino logic.

Sequencing elements : static ordynamic.

Static storage : Feedback to retain its output value

indefinitely.

Dynamic storage: Maintains its value as charge ona capacitor that will leak away if not refreshed for a

long period of time.


3/22

Sequencing Static CircuitsSequential elements: flip-flops and latches.

3 terminals incorporated by both:data input (D), clock (elk), and data output (Q).

The latch is transparent when the clock is high and opaque when the

clock is lowlevel sensiti ve.

The flip-flop: an edge-tr iggered devicethat copies D to Q on the

rising edge of the clock and ignores D at all other times.


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Sequencing MethodsFlip-flops

2-Phase Latches

Pulsed Latches

Flip-Flops

Flop

L

atch

Flop

clk

1

2

p

clk clk

L

atch

L

atch

p

p

1

1

2

2-Phase

TransparentLatche

s

Pulsed

Latches

Combinational Logic

Combinational

Logic

Combinational

Logic

Combinational LogicLatch

Latch

Tc

Tc/2

tnonoverlap

tnonoverlap

tpw

Half-Cycle 1 Half-Cycle 1


5/22

Flip Flop viewed as back to back latch pair


6/22

Timing Diagrams

Flop

A

Y

tpd

Combinational

LogicA Y

D Q

clk clk

D

Q

Latch

D Q

clkclk

D

Q

tcd

tsetup t

hold

tccq

tpcq

tccq

tsetup

thold

tpcq

tpdq

tcdq

tpd Logic Prop. Delay

tcd Logic Cont. Delay

tpcq Latch/Flop Clk-Q PropDelay

tccq Latch/Flop Clk-Q Cont.

Delay

tpdq Latch D-Q Prop Delay

tpcq Latch D-Q Cont. Delay

tsetup Latch/Flop Setup Time

thold Latch/Flop Hold Time

Contamination and

Propagation Delays


7/22

Max-Delay ConstraintsIdeally, the entire clock cycle would be available for

computations in the combinational logic.The sequencing overhead of the latches or flip-flops cuts into

this time.

If the combinational logic delay is too great, the receiving

element will miss its setup time and sample the wrong value.This is called a setup time failure ormax-delay failure.

It can be solved by : redesigning the logic to be faster

or by increasing the clock period.

The computation of the actual time available for logic and thesequencing overhead of each of sequencing elements is done

in next slides: flip-flops, two-phase latches, and pulsed

latches.


8/22

Max-Delay: Flip-Flops

F1

F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tpd

tsetup

tpcq

sequencing overhead

pd ct T


9/22

Max-Delay: Flip-Flops

F1

F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tpd

tsetup

tpcq

setupsequencing overhead

pd c pcqt T t t


10/22

Max Delay: 2-Phase Latches

Tc

Q1L1

1

2

L2

L3

1

1

2

CombinationalLogic 1

CombinationalLogic 2

Q2 Q3D1 D2 D3

Q1

D2

Q2

D3

D1

tpd1

tpdq1

tpd2

tpdq2

1 2sequencing overhead

pd pd pd ct t t T


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Max Delay: 2-Phase LatchesSolving for the maximum logic delay, which is the

sum of the logic delays through each of the twophases.

The sequencing overhead is the two latch propagation

delays.The nonoverlap between clocks does not degrade

performance in the latch-based system because data

continues to propagate through the combinational

logic between latches even while both clocks are low.

A flip-flop can be made from two latches whose

delays determine the flop propagation delay and setup

time.


12/22

Max Delay: 2-Phase Latches

Tc

Q1

L1

1

2

L2

L3

1

1

2

Combinational

Logic 1

Combinational

Logic 2

Q2 Q3D1 D2 D3

Q1

D2

Q2

D3

D1

tpd1

tpdq1

tpd2

tpdq2

1 2sequencing overhead

2pd pd pd c pdqt t t T t


13/22

Max Delay: Pulsed Latches

Tc

Q1 Q2D1 D2

Q1

D2

D1

p

p

p

Combinational LogicL1

L2

tpw

(a) tpw > tsetup

Q1

D2

(b) tpw

< tsetup

Tc

tpd

tpdq

tpcq

tpd

tsetup

sequencing overhead

maxpd ct T


14/22

Max Delay: Pulsed Latches

Tc

Q1 Q2D1 D2

Q1

D2

D1

p

p

p

Combinational LogicL1 L2

tpw

(a) tpw > tsetup

Q1

D2

(b) tpw

< tsetup

Tc

tpd

tpdq

tpcq

tpd

tsetup

setupsequencing overhead

max ,pd c pdq pcq pwt T t t t t


15/22

Min-delay Constraints

Ideally, sequencing elements can be placed back to back without

intervening combinational logic and still function correctly.e.g. , a pipeline can use back-to-back registers to sequence along

an instruction opcode without modifying it.

However, if the hold time is large and the contamination delay is

small, data can incorrectly propagate through two successiveelements on one clock edge, corrupting the state of the system.

This is called a race condition, hold time failure, ormin-delay

failure.

It can only be fixed by : redesigning the logic,

not by slowing the clock.

Therefore, designers should be very conservative in avoiding

such failures because modifying and refabricating a chip is very

expensive and time-consuming.


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Min-Delay: Flip-Flops

cdt

CL

clk

Q1

D2

F1

clk

Q1

F2

clk

D2

tcd

thold

tccq


17/22


holdcd ccqt t t CL

clk

Q1

D2

F1

clk

Q1

F2

clk

D2

tcd

thold

tccq


18/22

If the contamination delay through the flip-flop

exceeds the hold time, back-to-back flip-flops

can be safely used.

If not, explicitly delay must be added between

the flip flops (e.g., with a buffer) or use specialslow flip-flops with greater than normal

contamination delay on paths that require back-

to-back flops.Scan chains are a common example of paths with

back-to-back flops.



19/22

Min-Delay: 2-Phase Latches

1, 2

cd cd t t

CL

Q1

D2

D2

Q1

1

L1

2

L2

1

2

tnonoverlap

tcd

thold

tccq

Hold time reduced by

nonoverlap

Paradox: hold applies

twice each cycle, vs.only once for flops.

But a flop is made of

two latches!


20/22

Min-Delay: 2-Phase Latches

1, 2 hold nonoverlapcd cd ccqt t t t t CL

Q1

D2

D2

Q1

1

L1

2

L2

1

2

tnonoverlap

tcd

thold

tccq

Hold time reduced by

nonoverlap

Paradox: hold applies

twice each cycle, vs.

only once for flops.

But a flop is made of two

latches!


21/22

Min-Delay: Pulsed Latches

cdt

CL

Q1

D2

Q1

D2

p t

pw

p

L1

p

L2

tcd

thold

tccq

Hold time

increased by pulse

width


22/22

Min-Delay: Pulsed Latches

holdcd ccq pwt t t t CL

Q1

D2

Q1

D2

p t

pw

p

L1

p

L2

tcd

thold

tccq

Hold time

increased by pulse

width

CMOS Sequential Circuit Design Lec.-1

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