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CMOS Design

Lab Manual

Developed By University Program Team

CoreEl Technologies (I) Pvt. Ltd.

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Objective Objective of this lab is to learn the Mentor Graphics HEP2 tools as well learn the flow of the Full

Custom IC design cycle. You will finish the lab by running DRC, LVS and Parasitic Extraction on

the various designs. In the process you will create various components like inverter, NAND

gate, XOR gate, Full adder, Latch, SRAM register cell and PLL, differential amplifier.

You will start the lab by creating a schematic and will attach the technology library called

“TSMC018”. Adding a technology library will ensure that you can do front to back design.

You will create a new cell called “Inverter” with schematic view and hence build the inverter

schematic by instantiating various components. Once inverter schematic is done, symbol for

“Inverter” is generated. Now you will create a new cell view called “Inverter_sim”, where you

will instantiate “Inverter” symbol. This circuit is verified by doing various simulations using

ELDO. In the process, you will learn to use EZviewer, waveform window options, waveform

calculator, etc...

You will learn the Pyxis Layout Editor basics by concentrating on designing an “Inverter”

through automatic layout generation. Then you will go ahead with completing the other layouts,

generating GDSII file. After that, by taking GDSII file as reference you will run DRC, LVS checks

on the layout, Extract parasitic and back-annotate them to the simulation environment.

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1. To open the Mentor Server from client machine, one should open the Xmanager tool

from Windows Desktop.

2. This opens the terminal as below and follow the steps shown in the below screen shot.

3. Run the commands displayed in the above picture and run “da_ic &” to open Pyxis

Schematic tool for design entry.

Open

Server IP

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4. In order to create new schematic select new � Schematic and specify the name for the

design in file name tab

Click OK. It opens a new schematic page.

File name

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5. Select Library � Device Lib then add Pmos Transistor (4-pin) and Nmos Transistor (4-

pin) on to the schematic area.

6. After adding the transistors create the connections as per the screen shot and also add

the ports.

7. Click on the worksheet and select the following options from the palette Library � Device Library

8. Add a 4-pin PMOS and NMOS from the device lib. 9. Connect the PMOS and NMOS as shown in the figure below to connect from one

node to another node select “w” to select wire. 10. Click on “back” tab on device lib palette. Select generic lib and add a input port

and output port by selecting the portin and portout tabs. 11. Select the input NET, and right click the mouse button and select “Name

Nets:”.Change the net names. 12. Change the properties of transistors by selecting the transistor and pressing

‘Q’.or right click and select edit properties, Change the ASIM_Model from NCH to N for NMOS & PCH to P for PMOS

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13. Change the W & L values of the Transistors to For PMOS : L = 2u; W=10u

For NMOS : L = 2u; W =5u

14. After editing the schematic check for errors by selecting check & save option.

15. Go to Add � Generate Symbol

16. Select Replace existing & activate symbol options

17. Click Ok. Symbol gets generated for you. Change the shape of symbol if

required. Save the symbol.

Test Bench Creation 1. Close all schematics & symbols. 2. Create a new schematic inv_sim by selecting new schematic from session. 3. Add symbol of the schematic made.

Add� Instance� Choose Symbol. 4. Add a Pulse Source at the input to inverter and a DC Voltage source VDD port. And do the necessary connections as per the figure given below.

** (from sources library we can pick various sources) 5. Right click on the Pulse Generator Source and select Edit Properties. 6. Change the values of the below mentioned parameters and apply the changes.

Once you change the values that have to be reflected once you click on OK tab. Initial = 0V Pulse = 5V Delay = 1nS Rise = 1nS Fall = 1nS Width = 25nS Period = 50ns.

7. Also change the magnitude of the Voltage Source from 1V to 5V by following the below step.

8. Right Click on the Voltage source adjacent to VDD and then Edit properties

Add wire

Add Ports

Check & Save

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9. Now from the menu bar click on check and save button. This will report if any errors

present. 10. Now click on “back” tab and then select ‘Simulation’ from the palette to run the simulation and select ok. 11. Select a New configuration (Give a new name for simulation). 12. Now select the Session tab _simulator/viewer from Setup on the palette and ensure That the following options are set. Simulator � Eldo and Viewer � EZwave and then Ok. 13. Select Lib/Temp/In � “include files”provide the following path by selecting the browsebutton. $ADK/technology/ic/models/ami05.mod. 14. Select Analyses �and enable “DC” and ”Transient”.

15. Drop down the Analysis setup and select DC setup give the parameters as

Select option Source

Select the voltage source as V1

Start: 0 stop: 5 Step 0.1

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16. Select Transient Setup and change the stop time to 1000N.

17. Select the input path A and then hold CTRL key and then output path Y and click on“ Probes” from the palette. Select DC in Analysis tab, Plot from Task tab Select add. Similarly select TRAN from Analysis tab and select add and close the window

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18. Now click on Run Eldo tab from the palette where it opens 2 windows showing various steps running in command line. Once it finishes it will invoke the EZWave waveform viewer. If it is not invoked Click on the View Waves Tab from the palette to invoke the EZWave Waveform Viewer.

19. Now the EZWave displays the input and output signals. 20. Here if you go and explore the folders and search for spi file in the simulation folder

inside test bench folder. It will be something like the below path /home/student/inv/inverter_sim/simulation_name/inverter.spi This .spi file will be used at post layout simulation

Inverter Layout Generation 1. Before Layout generation, change the ASIM_Model of PMOS from P to PMOS

and NMOS 2. from N to NMOS in inverter schematic. 3. Invoke the IC station tool by typing the following command_ ic & on command

prompt 4. Now choose the “create” option from the palette. 5. Select Component. 6. Component� to the path of inverter schematic Cell name_ name of inverter

schematic

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7. Process�$ADK/technology/ic/process/ami05 8. Rules�$ADK/technology/ic/process/ami05.rules

9. MGC � setup � select left right tiling 10. Set Grid to 0.5. (select the layout window)

Setup � Pyxis Assemble, and set the parameters as shown below 11. Setup� SDL

In Component Subtype change ‘model ‘to ‘asim _model’ Choose SDL portstyles.Prompt user

Click setup and select layer 49 (METAL 1 as default layer)

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12. Go to Place�Inst in Palate Area. 13. This will place transistor in Layout view. 14. Similarly do for NMOS transistor and ports.

15. Select POLY for Layer Palate and connect the two gates of Transistors. Easy Edit � Shape

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16. Similarly connect the Drain of PMOS and Drain of NMOS with Metal-1. 17. Extend the Metal-1 layer that connects drains with IRoute option

Tools�IRoute� IRoute the after extending a layer of metal from M-1 layer that connects drains & press Space barwhich adds a via on which the port has to be placed.

18. Draw a square of 6X6 at POLY layer connecting two gates. At 1.5 distance from

sides of square 19. Draw a square with CONTACT TO PLOY as an inner square with 2Lx2L to

POLY. 20. Now connect input pin to Via drawn with Metal 1 layer using IRoute method.

21. Connect VDD to Source of PMOS and VSS to Source of NMOS using M1 layer. Easy Edit� shape (M1 from Layer palate).

22. Draw M1 layer above PMOS & below NMOS to keep NWELL and PSUB contacts.

23. Rightclick on the layout area Add � Layout

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Go to $ADK/technology/ic/process/ami05_via Add Pwell_contact at M1 layer below NMOS and also add on the top of PMOS transistor, now to change this Pwell to Nwell select the well contact and press ‘Q’ and browse the location to $ADK/technology/ic/process/ami05_via and select Nwell_contact.

DRC Checking DRC check using Calibre:

1. First we have to generate GDSII file: File� Export GDSII

2. Give the path where it has to be saved. Go Options. Check Replace Existing GDSII File & Add Text on Ports.

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3. Tools�Calibre� Run DRC 4. Give details as

Rules: $ADK/technology/ic/process/ami05.rules Inputs: To the gds file UnCheck ‘Export from layout Viewer’ Run DRC: It will report with no results when the design is error free.

Layout versus Schematic: 1. Tools � Calibre � Run LVS

Give details as Rules: $ADK/technology/ic/process/ami05.calibre.rules Inputs:� layout Browse for GDS file Inputs � netlist Browse for inverter.spi (in your simulation directory of testbench); Format:SPICE UnCheck ‘Export from layout Viewer’ & ‘Export from schematic Viewer’ Format: SPICE Run LVS

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Parasitic Extraction Tools� Calibre� Run PEX Give details as Rules: $ADK/technology/ic/process/ami05.calibre.rules DRC Run Directory: your directory Inputs:_ layout _GDSII file ;Format : GDSII Inputs _ netlist _ inverter.spi in your simulation directory; Format: SPICE UnCheck ‘Export from layout Viewer’ & ‘Export from schematic Viewer’ Outputs: Netlist _Format= DSPF Used Names for _Schematic Select only R+C instead of R+C+C Run LVS It will generate a Pex Netlist file has to be used in post layout simulation

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POST LAYOUT SIMULATION Open your Test Bench: by running da_ic & command in terminal window. Descend into your schematic and change the Asim_model of PMOS to P and NMOS to N Check and Save. Simulate your Test Bench. In Simulation Window on top palette, Tools�Parasitics�Add DSPF Go to the directory to find inverter.pex (inverter.pex.netlsit) Select RC, DSPF and click OK Now Simulate with Eldo. You can Add & Remove DSPF in Parasitic which show results with & without Parasitic.

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This ends the full custom IC design flow for an Inverter using HEP1 Design tools from Mentor

Graphics.