Department of Electrical and Computer EngineeringUniversity of Wisconsin - Madison

ECE/Comp. Sci. 352 { Digital System Fundamentals

Final Suggested Solution

1. (25 points) Short Questions

(a) (5 points) Convert (3A:B)12 into a decimal number. Round to the hundredth digit.

Answer: 46:92

(b) (5 points) Add the two hexadecimal numbers; leave the result in hexadecimal, of course.

0 9 8 7 6 h5 4 3 2 1 h

5 D B 9 7 hAnswer: 5DB97h

(c) (5 points) Mark each Boolean identity which is incorrect in the table below, and giveONE counter example on its right to illustrate that it is wrong. If it is correct, leave it alone.

Mark Boolean Identities

X A B +A B = 1

ABC + ABC + B = A+ B

Counter example: Let A = 1, and B = 0. Then A B +A B = 0 � 1 + 1 � 0 = 0 6= 1.

(d) (5 points) Express the following Boolean function in product-of-MAXTERMS canonicalform.

Solution: Use Karnaugh map, we have: f(w; x; y; z) = y(xz + z) + w x(y + yz) + xyz =Q(1; 2; 6; 7; 9; 10)

(e) (5 points) Express F in minimal sum-of-products form.

B

C

A

F

Answer: F = AB +AC

2. (10 points) Carry Look-Ahead Adder

As a compromise between hardware cost and speed a four-bit parallel adder is designed suchthat the carry-out of the fourth bit C4 is implemented with a two-level sum-of-products

function of G3, P3, G2, P2, G1, P1, and G0, P0 as well as carry-in C0. The remaining carriesC3, C2, and C1 are generated using conventional carry propagation (Ci+1 = Gi+PiCi). Alsorecall that Gi = Ai � Bi, Pi = AiBi, and Si = (Ai � Bi)� Ci.

(a) (5 points) Write C4 in sum-of-products form.

(b) (5 points) Assuming that AND, OR, NOT, as well as XOR gates all introduce unitpropagation delay. Also, assume that all the inputs fAi; Bi; 0 � i � 15g and C0 are madeavailable simultaneously at time 0.

Maximum gate delay when C4 is stablized is: 3

Maximum gate delay when s3 is stablized is: 7

3. (15 points) Synchronous Sequential Circuit

A two-bit counter has two control lines s1s0. Its function is described in the table below.

Two positive edge triggered ip- ops A and B are used toimplement this counter. A is the most signi�cant bit of acount.

s1s0 Function

00 unchanged01 count up10 count down11 clear (synchronous)

(a) (5 points) Sketch the state diagram. Label each state with A(t)B(t) = 00; 01; 10; 11respectively.

(b) (5 points) Carefully draw the waveforms for A and B for the given initial values andcontrol signals. Show ip- op propagation delay (1/16th of an inch or so).

clock

A

B

1s

0s

(c) (5 points) Flip- op A is a JK- ip- op; B is a D- ip- op. Derive input equations for thetwo ip- ops.

JA =

KA =

DB =

4. (15 points) More Short Subjects

(a) (8 points) A system is to perform the following register transfers in response to the controlvariables shown.

Ka : R1 R2Kb : R2 R3Kc : R3 R2Kd : R4 R1

Each of the four registers has bidirectional input-output lines with load and three-state outputEnable controls. These registers are connected to the bus as shown below. Write Booleanexpressions for all control signals to all registers so that the above four register transferoperations are realized.

Solution: Connections to the load control of each registers R1, R2, R3 and R4 are, respec-tively, Ka, Kb, Kc, and Kd. Connections to the Enable signals to each registers are: Kd toR1 Enable, Ka +Kc to R2 Enable, Kb to R3 Enable, and 0 to R4 Enable.

(b) (7 points) A computer has a 64-bit word length with 64-bit instruction format. It contains14 bits OP code, 3 register �elds with 10 bits each, and a 20 bit immediate operand �eld. Inthe following three questions, you may leave your answer in exponential form (e.g. 23).

Answer: The maximum number of operations that can be speci�ed is: 214

The maximum number of registers can be addressed is: 210

The largest algebraic value of signed 2's complement binary number that can be accommo-

dated as an immediate operand is 219 � 1

5. (10 point) ASM Chart Design

s0

X0

s2 s1

1

A

YY0

1

0

B

G0 1

1

A;B;G;X; Y are input or output Boolean variables in the ASM chart on the facing page.Draw the logic diagram of a one ip- op per state implementation of this ASM chart. OnlyNAND gates and inverters are available in addition to the ip- ops shown. Anactive-low input RESET must asynchronously force the FSM to state s0.

R

SD

R

SD

R

SD

6. (15 points) Single-Cycle Computer

Refer to the single cycle computer documented on the facing page.

(a) (5 points) Complete the following table to determine the opcode of the shift-right instruc-tion shown.

Instruction Register Transfer FS MB MD RW MW Opcode

R[DR] srR[SA] 10000 0 0 1 0 0010000

(b) (10 points) Simulate the single cycle computer for the �rst two of the instructions shownin the table below. IM [PC] is the contents of the Instruction Memory at the address held bythe PC register shown in binary for your convenience. All register entries are in hexadecimal;all results should be in hexadecimal. Each line represent one clock cycle.

Micro-operation IM [PC] [R0] [R1] [R2] [R3]

R0 R0 + 7 1000010000000111 0000 0004 0002 0001

R1 R2 + 1 0000001001010000 0007

R3 R2 0001110011010000 0003

7. (10 points) Multi-Cycle Microprogrammed Computer

Instruction ASR (add and shift-right) for the micro-programmed computer documented onthe facing page performs the operation

R[DR] sr[R[SA] +R[SB]]

Derive the symbolic microprogram for this instruction starting at microprogram controlmemory address ASR. You may not need all of the rows provided in the table below. If a�eld in a microinstruction is not signi�cant place a dash in its box. The execution of thisinstruction will be at consecutive address in the control memory starting from ASR as labeledin the table below. The address for instruction fetch microinstruction is IF. Use the temporaryregister R8 to store intermediate result.

To save space, the following abbreviations may be used:

� TD, TA, TB { the entries may be either R8 or DR, SA, SB respectively.

� PI { I (increment), N (no change)

� IL { L (load), N (no load)

� MD { the entries may be F (function unit) or D (Data)

� RW, MW { WR (write), or NW (do not write)

� MM { PC (program counter), MA (memory address from bus A)

Other symbols refer to tables 8-9 and 8-10 in the back of the cover page.

Addr.NXT

ADDMS MC IL PI TD TA TB MB FS MD RW MM MW

ASR ASR1 NXT NXA N N R8 SA SB R F=A+B F WR { NW

ASR1 IF NXT NXA N N DR R8 { { F=sr A F WR { NW

or if we assume ASR1 = ASR+ 1 in the control memory, we may also use CNT in the MS

�eld:

Addr.NXT

ADDMS MC IL PI TD TA TB MB FS MD RW MM MW

ASR { CNT { N N R8 SA SB R F=A+B F WR { NW

ASR1 IF NXT NXA N N DR R8 { { F=sr A F WR { NW