LAB 912

Analog Integrated Chip Design

Ke-Horng ChenNCTU EE

2011 Autumn

Teaching Material: Text Book

Design of Analog CMOS Integrated Circuits, by BehzadRazavi, McGRAW-HILL, 2001

References CMOS Analog Circuit Design, by Phillip E. Allen, Oxford

University Press, 2002 Analysis and Design of Analog Integrated Circuits, Paul R.

Gray, John Wiley & Sons, Inc., 2001 Grade

50% Homework 50% Mid-exam, Final-exam

TA: , , , (912) English TA time: Monday AM10:00~12:00

Analog Integrated Chip Design

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Outline Introduction Basic MOS Device Physics Single-Stage Amplifiers Differential Amplifiers Passive and Active Current Mirrors Frequency Response of Amplifiers Noise Feedback Operational Amplifiers Stability and Frequency Voltage Reference Circuits Switched-Capacitor Circuits

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Introduction

While silicon bipolar and III-V device still find niche applications, only CMOS processes have emerged as a viable choice for the integration of todays complex mixed-signal systems

In the past two decades, CMOS technology has rapidly embraced the field of the analog integrated circuits, providing low-cost, high-performancesolutions and rising to dominate the market

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Why Analog ? Processing of natural signals

Digital communication

Attenuation and distortion of data through a lossy cable

Use of multi-level signaling to reduce the required bandwidth

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Why Analog ? (contd) Disk drive electronics Sensors

Microprocessors and memories High-speed (digital) circuit

design is in fact analog design

Wireless receivers

Optical receiver

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Why is analog design difficult? Digital circuits entail primarily one trade-off between speed and

power dissipation Analog design must deal with a multi-dimensional tradeoff consisting

of speed, power dissipation, gain, precision, supply voltage, etc. With the speed and precision required in processing analog signals, analog

circuits are much more sensitive to noise, crosstalk, and other interferersthan are digital circuits

Second-order effects in devices influence the performance of analog circuits much more heavily than that of digital circuits

The design of high-performance analog circuits can rarely be automated, usually requiring that every device be hand-crafted.

Despite tremendous progress, modeling and simulation of many effects in analog circuits continue to pose difficulties, forcing the designers to draw upon experience and intuition when analyzing the results of a simulation

Developed and characterized for digital applications, such technologies do not easily lend themselves to analog design, requiring novel circuits and architectures to achieve a high performance

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Comparison of Analog and Digital Circuits

Analog Circuits Signals are continuous in amplitude and can be

continuous or discrete in time Designed at the circuit level Components must have a continuum of values Customized CAD tools are difficult to apply Requires precision modeling Performance optimized Irregular block Difficult to route automatically Dynamic range limited by power supplies and

noise (and linearity)

Digital Circuits Signal are discontinuous in amplitude and

time-binary signals have two amplitude states Designed at the systems level Component have fixed values Standard CAD tools have been extremely successful Timing models only Programmable by software Regular blocks Easy to route automatically Dynamic range unlimited

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Skills Required for Analog IC Design In general, analog circuits are more complex than digital

Requires an ability to grasp multiple concepts simultaneously Must be able to make appropriate simplifications and

assumptions Requires a good grasp of both modeling and technology Have a wide range of skills - breadth (analog only is rare)

Be able to learn from failure Be able to use simulation correctly

Simulation truths:

(Usage of a simulator) x (Common sense) Constant

Simulators are only as good as the models and the knowledge of those models by the designer

Simulators are only good if you already know the answers

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Analog Integrated Circuit Design What is Analog IC Design?

Analog IC design is the successful implementation of analog circuits and systems using integrated circuit technology

Unique Features of Analog IC Design Geometry is an important part of the design

Electrical Design Physical Design Test Design Usually implemented in a mixed analog-digital circuit Analog is 20% and digital 80% of the chip area Analog requires 80% of the design time Analog is designed at the circuit level Passes for success: 2-3 for analog, 1 for digital

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The Analog IC Design Flow

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Basic MOS Device Physics

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Introduction In studying the design of integrated circuits, one of two

extreme approaches can be taken: Begin with quantum mechanics and understand solid-state,

semiconductor device physics, device modeling, and finally the design of circuits

Treat each semiconductor device as a black box whose behavior is described in terms of its terminal voltages and currents and design circuits with little attention to the internal operation of the device

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General considerations MOSFET as a switch

If the gate voltage, VG, is high, the transistor connects the source and the drain together

If the gate voltage, VG, is low, the transistor isolates the source and the drain

MOSFET structure

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MOS device Simple NMOS device

Cross section of CMOS n-well technology

MOS symbols

Simple PMOS device

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Operation of MOSFET A MOSFET driven by a gate voltage Formation of depletion region

Onset of inversion Formation of inversion layer

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Threshold voltage In semiconductor physics, the VTH of an NFET is defined as the

gate voltage for which the interface is as much n-type as the substrate is p-type

The threshold voltage can be provided that

2 depTH MSox

F

QV

C The work function is defined as the energy required to remove an electron from Fermi

level Ef to a position just outside the material (the vacuum level)

FMS Fsubstrate gate MS is the difference between the work functions of the polysilicon

gate and the silicon substrate F = (kT / q)ln(Nsub / ni), q is electron charge, Nsub is the doping

concentration of the substrate Qdep is the charge in the depletion region Cox is the gate oxide capacitance per unit area

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I/V characteristics Triode region

0 0

22,max

1 1, 2 2

DS

D d ox GS TH ox GS TH

L V

D ox n GS THx V

D n ox GS TH DS DS D n ox G

n

S TH

I Q x v WC V V x V WC V V x V

I dx WC V V x V dV

W WI C V V V V and I C V VL

dV xv

d

L

x

2:, mFCVVWCQ oxTHGSoxd d ox GS THQ x W V VV xC

(VD VG VTH) Condition: VDS VGS VTH Equal source and drain voltage Unequal source and drain voltage

Derivation

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212D n ox GS TH DS DS

WI C V V V VL

I/V characteristics Triode region (contd) Drain current versus drain-source

voltage

Linear operation in deep triode region

With the condition VDS

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I/V characteristics Saturation region Condition: VDS VGS VTH

' 212D n ox GS THW VL

I C V

Pinch-off behavior

Saturated MOSFETs operating as current sources

221

THGSoxnD VVLWCI

(VD VG VTH)

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Transconductance For amplification purposes, the transconductance of the device is

calculated

MOS transconductance as a function

constant

|

22 2 , where =

DS

Dm V n ox GS TH

GS

Dn ox D D n ox

GS TH

I Wg C V VV L

IW WC I I CL V V L

m G THn Sox WLg VC V 2 om Dn xCg IWL

2

mS TH

D

G

gV

IV

2'21

THGSoxnD VVLWCI

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Conceptual visualization of saturation and triode regions

Saturation Edge of Triode Region

Edge of Triode Region Saturation

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Second-order effects1. Body effect

0 2 2TH TH F SB FV V V

No body effect Body effect

where denotes the body effect coefficient

oxsubSi CNq /2

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Example: Source follower with (a) no body effect and (b) body effect

(a) Ignore body effect: As Vin varies, Vout closely follows the input because the drain current

remains equal to I1 It can be written by

Second-order effects (contd)

21 12 n ox in out THWI C V V VL

no body effect body effect

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Second-order effects (contd)2. Channel-length modulation

' 212D n ox G S T HW VL

I C V L is a function of VDS

Writing L= L L, i.e., 1/L (1+ L/ L)/L, and assuming L/L=VDS

: the channel-length modulation coefficient

22

11D n ox GS TH DSWI C V V VL

11 1 1 1(1 / ) (1 / ) (1 )' D S

L L L L VL L L L

4:1

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Second-order effects (contd)

3. Subthreshold conduction, VGS < VTH

If W increases while ID remains constant, then VGSVTH and the device enters the subthreshold region As a result, the transconductance is calculated to revealing that

MOSFETs are inferior to bipolar transistors The exponential dependence of ID upon VGS in subthreshold operation may

suggestion the use of MOS devices in this regime so as to achieve a higher gain

However, since such conditions are met by only a large device width or low drain current, the speed of subthreshold circuits is severely limited

exp

where > 1 is a nonideality factor and /

GSD o

T

T

VI IV

V kT q

212D n ox GS TH DS DS

WI C V V V VL

constant

Dm

T

IgV

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MOS devices Birds eye of a MOS device

Vertical views of a MOS device

Show the overlap between the

source or drain and the gate

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Oxide capacitance between the gate and the channel, C1 = WLCox Depletion capacitance between the channel and the substrate,

Capacitance due to the overlap of the gate poly with the source and drain areas, C3 and C4 The overlap capacitance per unit width is denoted by Cov (per unit width)

Junction capacitance between the source/drain areas and the substrate Bottom-plate capacitance associated with the bottom of the junction,

Sidewall capacitance due to the perimeter of the junction, CjSW (note: CjSW : F/m)

MOS device capacitances

2 / 4Si sub FC WL q N

20 / 1 / 2 Note: : /mj j R F jC C V C F m

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MOS device capacitances (contd) Example: Calculate the source and drain junction capacitances

The geometry of the folded structure in Fig. (b) exhibits substantially less drain junction capacitance than that in Fig. (a) while providing the same W/L

jswjSBDB CEWWECCC 2

Folded structure:

2 2

2 22 2

22 2

SB j jsw

j js

B

w

D j jsw

W W

W WC EC E

C EC E C

WEC W E

C

C

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Variation of CGS and CGD versus VGS

Example For VX 0, M1 is in the triode region,

CEN CEF = (1/2)WLCox + WCov, and CFB is maximumVX is higher than 1V

VTH=0.6V

Triode Saturation

Why?

C7 C7 OFF: CGB=[C1C2/(C1+C2)]+2C7 ON: CGB=2C7

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Voltage dependence of CGS, CGD, and CGB as a function of VGS with VDS constant and VBS=0

7

3 1

4 1

2

1 0.52

0

N onsatur

.5

1 0.52

0 .5

ated

eff

ox eff eff

ox ef

G D

G S

f eff

ox eff eff

ox eff eff

G B C C G B O L

C C C LD L W

C G SO C L W

C C C LD L W

C G D O

C

C

C

W

C

L

C1+2C7

C3+2/3C1

C3+1/2C1

C3,C42C7

1 7

3

4

7

3 1

4

OFF

Saturation

2

2

2 0.673

0.67

ox eff eff eff

ox eff eff

ox eff eff

eff

ox eff eff

eff ox eff eff

ox

GB

GD

G eff e

G

D

GS

GB

S

C C C W L CGBO L

C C LD W CGSO W

C C LD W CGDO W

C CGBO L

C C C LD L W

CGSO W C W

C

C

L

C C LD W C

C

C

O

C

D W

C

G

ff

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NMOS Terminal Capacitances, L=0.35ummn dn gn 0 0 nch L=0.35u W=10uvdn dn 0 dc 0.5Vvgn gn 0 dc 1.2Vm1 dn gn 0 0 nch L=0.35u W=10u geo=1m2 dn gn 0 0 nch L=0.35u W=10u geo=2m3 dn gn 0 0 nch L=0.35u W=10u geo=3.op.dc vgn 0V 3.5V 10mV.probe+ cgs = par('-cgsbo(mn)')+ cgd = par('-cgdbo(mn)')+ cdtot = par('cddbo(mn)') $ cgd + cdb+ cgtot = par('cggbo(mn)') $ cgs + cgd + cgb+ colgs = par('covlgs(mn)') $ col at source+ colgd = par('covlgd(mn)') $ col at drain.options dccap post=2 brief.option ingold=2 numdgt=2 accurate .option absmos=1e-15 absv=1e-12 relmos=1e-7 absi=1e-14.lib 'mm0355v.l' TT.end

OPTION DCCAP: turn on capacitance calculations for a DC sweep

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Behavior of MOS Device as a Capacitor Accumulation region: VG

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Behavior of MOS Device as a Capacitor (contd)

Bulk tuning of the polysilicon-oxide-channel capacitor (0.35m CMOS)

m ax m in/ 4C C

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MOS small-signal model Basic MOS small-signal model

Channel-length modulation represented by a depend current source

Channel-length modulation represented by a resistor

GS

Dm V

Ig

21 1

12

1DSD D DS

n ox GS TH

oD

VWI I V C V V

rI

L

VDS

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Body effect represented by a dependent current source

In the saturation region, gmb can be expressed as

MOS small-signal model (contd)

mmb ggThus

where

Dmb n ox GS THB

TH

SS B

I Wg C V V VVV L

1 222

THF SB

SB

TH

BS

VV

V VV

2 2D

mb m mF BBS S

Ig g gV V

gm

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MOS small-signal model (contd) Example: Sketch gm and gmb of M1 as a function of the bias

current I1

Since , we have The dependence of gmb upon I1 is less straightforward As I1 increases, VX decreases and so does VSB

1Igm Doxnm ILWCg 2

VXVSB

2 2mb SBm

F

gV

g

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MOS small-signal model (contd) Complete MOS small-signal model

Req=RG/4

Reduction of gate resistance by folding

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MOS SPICE models

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MOS SPICE models (contd) The parameters of Spice models are defined as below: