Charge transfer on porous silicon membranes studied by

current-sensing atomic force microscopy

Bing Xia a,b, Qiang Miao a, Jie Chao a, Shou Jun Xiao a,*,Hai Tao Wang b, Zhong Dang Xiao b

a State Key Laboratory of Coordination Chemistry, School of Chemistry and Chemical Engineering,

Nanjing University, Nanjing 210093, Chinab State Key Laboratory of Molecular and Biomolecular Electronics, Southeast University, Nanjing 210096, China

Received 10 July 2007

Abstract

A visible rectification effect on the current–voltage curves of metal/porous silicon/p-silicon has been observed by current-

sensing atomic force microscopy. The current–voltage curves of porous silicon membranes with different porosities, prepared

through variation of etching current density for a constant time, indicate that a higher porosity results in a higher resistance and thus

a lower rectification, until the current reaches a threshold at a porosity>55%. We propose that the conductance mode in the porous

silicon membrane with porosities >55% is mainly a hopping mechanism between nano-crystallites and an inverse static electric

field between the porous silicon and p-Si interface blocks the electron injection from porous silicon to p-Si, but with porosities

�55%, electron flows through a direct continuous channel between nano-crystallites.

# 2007 Shou Jun Xiao. Published by Elsevier B.V. on behalf of Chinese Chemical Society. All rights reserved.

Keywords: Porous silicon; Current sensing AFM; Electron transfer; Porosity

The potential uses of porous silicon (PS) as base materials for light emitting devices, sensors, and microelectronic

devices lead to an intensive investigation of its electrical properties [1]. Previous papers reported notable rectifying I–V

characters of the metal/PS/Si junction, and the rectification phenomenon was affected by their substrates (p- or n-type

and doped degree) and porous layers (porosity, thickness, and oxidation) [2–5]. It was also influenced by the

experimental environment, including moisture, gas, and temperature, etc. [6,7]. Regarding its mechanism, some initial

investigations considered the formation of a Schottky barrier between metal and PS (metal/PS diode) [8]. Subsequent

studies suggested that two junctions exist in these diodes: one at the metal/PS interface and the other at the PS/silicon

interface [9]. Then more and more people accept that the rectification effect comes from the depletion layer between

PS and the c-Si substrate, but the detailed mechanism is still under debate. It is necessary to get more information about

electrical properties of the depletion layer to explain the unique rectification phenomenon.

The characteristics of the depletion layer are tightly relative with the nano-structure of PS (such as porosity,

thickness, pore diameter, etc.), so it is important to measure the electrical property of the porous layer in nano-size. As

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Chinese Chemical Letters 19 (2008) 199–202

* Corresponding author.

E-mail address: sjxiao@nju.edu.cn (S.J. Xiao).

1001-8417/$ – see front matter # 2007 Shou Jun Xiao. Published by Elsevier B.V. on behalf of Chinese Chemical Society. All rights reserved.

doi:10.1016/j.cclet.2007.12.003

far as we know, until now there is no report about the I–V relationship of PS measured by current-sensing atomic force

microscopy (CSAFM), which has been used to study the electrical properties of molecular junctions [10]. In this letter,

the I–V curves of the junction of Pt-coated AFM tip/PS/p-Si were recorded by sweeping the sample bias. A visible

rectification effect reported in the past literature on the I–V curves had been observed [2–7]. More, we first observed (1)

the ‘‘blocking effect’’ on the electron injection from PS to p-Si in the reverse bias is explained by an inverse static

electric field between the PS and p-Si interface, (2) the higher porosity resulting in the higher resistance, and (3) the

current threshold at a porosity >55% with CSAFM in the forward bias.

The single side polished, (1 0 0) oriented, and p-type Si wafers (boron doped, �0.02 V cm resistivity) were boiled

in 3:1 (v/v) concentrated H2SO4/30% H2O2 for 30 min and then rinsed copiously with Milli-Q water (�18 MV cm

resistivity). The PS samples (1.54 cm2) with about 30 mm thick porous layer were electrochemically etched in an

ethanolic HF solution (HF(40%)/EtOH (1:1 v/v)) at 5 mA cm�2 for 8 min. To investigate the electrical properties of

PS samples, the I–V curves were measured on a multimode SPM with the PicroSPM II controller (Molecular Imaging)

using the Pt-coated commercial Si3N4 cantilevers (Mikromash). All operations were done under a purged nitrogen

atmosphere with a relative humidity of 20% at 26 8C. To avoid the oxidation of the silicon surface, the positive and

negative branches of I–V curves were obtained by scanning the sample bias from 0!�10 V or 0! +10 V,

respectively. Before the tip contacted the silicon substrate, essentially no current in excess of the noise (�0.3 pA) was

detected. The I–V measurements were run at different locations on the same sample, and on samples from different

batches. After the tip stress was increased to a certain value to meet the contacting criteria between tip and sample

surface, the current signal was recorded.

The representative I–V curves of oxide-free flat silicon and PS samples measured by the Pt tip were recorded in

Fig. 1. From Fig. 1, three main results can be concluded and discussed.

(1) In curve (a), a near symmetric behavior is observed in the Pt/p-Si junction. It can be ascribed to the highly doped

degree of p-Si substrate, which leads to little difference of the work function between Pt and Si substrate. In curve (b), a

clear diode-like behavior appears in the Pt/PS/p-Si junction. In this case, the positive branch is reverse and the negative

branch is forward. Relative to the plane Pt/p-Si junction, the rectification ratio of the Pt/PS/p-Si junction becomes

much larger. It is because the free carriers are partially depleted due to quantum-confinement or trapping in the PS

layer. The depletion of free carriers leads to an inverse static electric field between the PS and p-Si interface. So the

band level of PS decreases because of the inverse layer and the band gap increases between PS and p-Si, which results

in a big barrier (fb) at the interface of PS/p-Si (the schematic band model is drawn in Fig. 2). The barrier leads to a

‘‘blocking effect’’ on the electron injection from PS to p-Si in the reverse bias.

(2) We defined the resistance, as the reciprocal of the slope between a linear extrapolation of the exponential tails at

the forward bias. According to curves (a and b), the resistances of Pt/p-Si and Pt/PS/p-Si junctions are about 0.1 and

2.5 GV, respectively. The PS layer has a higher resistance than the flat silicon (25 times higher), which is also

attributed to the depletion of free carriers in the PS layers.

(3) We defined the forward threshold voltage, VT, as the absolute value of the intercept between a linear

extrapolation of the exponential tails and the zero-current axis. Because of high doping in the p-silicon substrate, the

value of VT of Pt/p-Si is small (�0.15 V) in curve (a). And it increases to�2.6 V in the junction of Pt/PS/p-Si (curve b).

B. Xia et al. / Chinese Chemical Letters 19 (2008) 199–202200

Fig. 1. The typical I–V curves on freshly prepared hydrogen-terminated (a) flat silicon and (b) PS etched at 5 mA cm�2.

Relative to the Pt/p-Si junction, the excess inverse layer must be overcome at the forward bias in the Pt/PS/p-Si

junction, which results in the increase of VT.

To further prove our proposed mechanism, we also carried out the I–V measurement on PS layers with different

porosities. The porosity of samples can be regulated by changing the etching current density [1]. Herein we prepared

PS samples at etching current densities of 5, 20, 35, 50, and 75 mA cm�2 for 8 min, respectively. While from the low to

high current density, a trend of color change from black (5 mA cm�2), to dark green (20 mA cm�2), dark orange

(35 mA cm�2), and dark red (75 mA cm�2) was observed. Their AFM (Multimode Nanoscope IIIa, Veeco/Digital

Instruments) and SEM (FESEM LEO 1530 VP) images of two typical samples (5 and 75 mA cm�2) are shown in

Fig. 3. It is obvious that the high current density results in larger pores and higher roughness on the PS surface. The

porosity versus current density in Fig. 4b was cited from the literature [11].

Their corresponding I–V curves were recorded in Fig. 4a. From the measurement, we noticed the great impression

of the porosity on the rectification effect. When the porosity is larger than 55%, the rectification effect nearly

disappears. We further derived the relationship of resistance and porosity versus current density in Fig. 4b, where the

resistance increases with the porosity. We propose that the disappearance of rectification is due to the huge resistance

of the PS membrane (porosity > 55%), which was also predicted by Koch et al. in their theory [12]. In Fig. 4b, the

resistance increases with increasing porosity when the porosity is less than 55%. However the resistance reaches a

threshold at the porosity around 55%. The wider energy band of a PS membrane with higher porosity will bear a higher

B. Xia et al. / Chinese Chemical Letters 19 (2008) 199–202 201

Fig. 2. A schematic diagram of a band model for the Pt/PS/p-Si structure.

Fig. 3. The SEM and AFM images of PS samples etched at different current densities. (SEM (a) 5 mA cm�2 and (b) 75 mA cm�2; AFM (c)

5 mA cm�2 and (d) 75 mA cm�2).

barrier for free carriers to move through and this leads to the higher resistance. Another suggestion is that there are two

different conductance modes in the PS membrane with different porosities [13]. The conductance mode in PS with

porosity >55% is mainly hopping between nano-crystallites. But in PS with porosity �55%, electron flows through

direct continuous channels among nano-crystallites.

In summary, CSAFM is a simple and reliable method to study the electrical properties of PS, relative to the

traditional method of metal electrodes by the thermal evaporation. According to our experimental measurements, we

qualitatively describe the process of electron transfer as: (1) When the porosity of PS is lower than 55%, electron

transfer in the junction of Pt/PS/p-Si is dominated by the inverse layer between PS and p-Si despite of at the forward

bias or at the reverse bias. In the PS layer, electron directly flows through a continuous channel between nano-

crystallites. (2) When the porosity of PS is higher than 55%, the resistance is very high due to the increase of interface

barrier (fb) and the Pt/PS/p-Si junction can be simply treated as an Ohmic contact. The process of conductivity takes

place via a hopping mechanism between the crystallites in the PS layer.

Acknowledgments

The authors thank the financial support of NNSFC (No. 20571042) and of the National Basic Research Program of

China (No. 2007CB925101).

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B. Xia et al. / Chinese Chemical Letters 19 (2008) 199–202202

Fig. 4. (a) The I–V curves of the PS samples with different etching current densities (5, 20, 35, 50 and 75 mA cm�2), (b) resistance and porosity of

PS vs. etching current density (*, for resistance; *, for porosity).