APR IL 1976

IEEE COMPUTER SOCIETY2 25 YEARtS OO SERVICE

INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS

I,=r=

tion can be stored in the shift register. Since CCD'soperate in the thermal non-equilibrium state, theleakage current generated tends to fill up the chargewells and thus limits the storage time.Transfer inefficiency of 1o-3 to 1O-5 have been

reported for different CCD technologies. So, shiftregisters in lengths of tens of bits to thousands ofbits can be built without including any refreshamplifier in the middle of the shift register.Storage time of 2ms to lOms in the operating

temperature range can be obtained depending uponthe device and process techniques.

Charge-Coupled Memory Interface Circuits

Circuits that are required for a functional charge-coupled memory device are described below. Inaddition to the basic shift register, the followingcircuits are needed.

Charge Injection Circuits. Charge is injectedinto the CCD strings as packets of minority carriers.This is generally done by gating a bias line connectedto the N+ diffusion region or by controlling an inde-pendent gate in series with the CCD string thatforms an electron inversion channel between the N+source region and the CCD channel. This is illus-trated in Figures 2a and 2b.

Charge Detection and Regeneration Circuits.Charge is detected at the output of the CCD stringas a change in surface potential and capacitance. Afloating diffusion adapts its potential to the surfacedepletion potential, and this change in potential canbe detected and/or connected to the injection-controlgate of another CCD string, thus regenerating thesignal. Each charge regeneration results in signalinversion, and an even number of such regenerationsare incorporated in closed loop serpentine shiftregisters. Output detection and regeneration cir-cuits are shown in Figures 2c and 2d.

Read/Write Circuits. Charge detection andregeneration circuits are equivalent to read andwrite circuits. When data is read, the charge fromone end of the shift register loop is detected, and thesame signal controls the charge injection into thebeginning of the shift register. If a write is intended,the charge injection is controlled by data input. Sim-ultaneous read and write can be executed. This logicis shown in Figure 3.

Data Buffers. Data buffers at both the input andthe output of the chip are desirable. TTL compati-bility at the input/output may be another desirableoption depending upon the memory environmentwhere the application is intended.

-i

CONTROL SWITCH

A. Charge injection

CONTROL GATE

-1|4 PHASE ELECTRODES_- 1-- --

~~~~--1-IwNN+LDIFFUSION P-Si

I

B. Charge injectionVDD

OUT

C. Charge detection

Decoder Circuits. For a decoded CCD memory ofN shift registers, we require an n-bit decoder (2n = N).The input data is applied to the input gate of eachloop, and-depending on the loop address applied to

34

D. Charge regeneration

Figure 2. Charge injection and detection circuits

COMPUTER

DATAINPUT

VDD

DATAOUT

STROBE

WRITE READ

Figure 3. CCD shift register loop inputloutput logic

the write input-the particular loop is enabled bythe decoder. As shown in Figure 3, "read" anc"write" are strobed properly for the selected shifiregister.

Clock Drivers. The clock drivers can be includecon the chip for ease of system design. The clocdcapitance per phase per chip will be of the order o:200-1000 pf for large LSI memories; for high-speecoperation, the power dissipation may be considerabl(CV2 X f). The high current drivers may take uplarge amounts of chip area, in which case separatEdrivers may be included at the systems level.

Technology Considerations

Low cost and high circuit density are the prim(considerations in the design of charge-couplecdevices and systems. To be cost-competitive ancuseful, charge-coupled memories should have th4following characteristics:

Large Scale Integration. Level of integratiorshould be at least 2 to 5 times that per MOEN-channel RAM. This, in turn, translates into a cosadvantage ratio of roughly 2 to 5 for CCD's. Yet, th4chip size may not be larger than 200 X 200 milP Largchip size results in lower yield and, thus, higher costThe memory cells and peripheral circuits should bdesigned for high bit density. Which of the man'CCD technologies will be chosen depends upoiresulting bit density, processing complexity, an(yield.

April 1976

CHARGE INJECTOR CHARGE DETECTOR

CHARGE DETECTOR CHARGE INJECTOR

Common Usage Memory Organization. Morethan any other memory like RAM or ROM, the CCDchip organization is very much linked to the par-ticular memory system applications; hence, the chipdesigner has to be closely associated with computersystems application. On the other hand, to achievelarge volume market, CCD LSI memories have to beorganized so that they can cater to the needs of

y many different applications.

Low Power and Low Capacitance. The charge-coupled memory devices must be designed so as tominimize chip power dissipation. Since off-chipclock driver dissipation is directly proportional tothe amount of clock capacitance, it is very desirablethat the input clock capacitance should be kept to aminimum.All the above factors should be judiciously com-

bined for any charge-coupled memory design andapplication.

Charge-Coupled Memory Applications

The areas of application for charge-coupledmemory can be broadly divided into the followingfive categories:

Block Organized Random Access Memory(BORAM). Such devices are organized into ran-domly accessible blocks of information, each blockcontaining few bits/bytes to hundreds of bits/bytes.This is the type that will satisfy the bulk of the CCDmemory applications, such as main memory andpaging memory. One special application of BORAMwould be as microprogramming memory whereinlong words are stored in the CCD shift registers.

Serial Memory. Such devices are needed forapplications similar to that of head-per-track disksas second-level mass memories. Serial-parallel-serial(SPS) shift registers, as explained later, having high

35

density, low power dissipation, and slower randomaccess time (200 psec-2 msec) but high data rate(5-10 MHz), are suitable for these applications. TheSPS blocks should be of 1K to 16K bits each.

Content-Addressable Memories (CAM) or PartiallyAssociative Memories (PAM). The idea of content-addressing the memories is attractive for systemarchitects and designers because of the elegancewith which information processing and informationretrieval can be performed. It has not been readilyand widely implemented in present technologiesbecause of the enormous amount of wiring and logicinvolved at every memory site and the consequentexcessive cost. However, partially associativememories that are processed in word-parallel andbit-serial fashion or in word-set parallel and bit/byteserial fashion can be readily and economically imple-mented with charge-coupled memories and beapplied to such applications as sorting, data filing,and retrieval.

Stacks and Queues. Stacks and queues are em-ployed very often as elements in computer sys-tems. In the present practice random access mem-ories are used as LIFO or FIFO by softwareprograms. This results in high overhead as well asdelay. LIFO and FIFO can be economically imple-mented in CCD technology, using unidirectionalor bidirectional CCD shift registers. Though theyare similar to the dynamic MOS shift registers,large stacks can be economically built with CCDtechnology due to the large packing density ofCCD's.

Data Buffer and Other Special Applications. Mostmodern computing systems have on-line memoryand storage hierarchies where data from one level tothe other is transferred in large blocks and somedata buffering is necessary. Such data buffers canbe made by employing charge-coupled shift registersthat have different input and output clock rates tointerface correspondingly with input and outputends.

Charge-Coupled Memory Device Organization

A wide number of organizations can be workedout for LSI charge-coupled memories dependingupon their intended usage and performance. InFigure 4, we show an organization of shift registersbuilt with straight electrode layout, whereby data isshifted in one direction only. Figure 5 shows a serial-parallel-serial (SPS) organization, wherein the datais serially inputted and shifted with fast clock,shifted as parallel blocks by applying slow shiftclock, and then gated out serially with fast clock.Figure 6 shows an organization of closed-loopserpentine shift registers4'5 where data moves inalternate directions in adjoining shift registersections.

36

M BITS t °1-I - C R

I *- CHANNEL REGIONI

I

12 * ICHANNEL STOPPER REGION

[- °2

I- z!I I uz z I13

l

l

IN ; !

Ir*03

I4 PHASE ELECTRODEI LINE

LO ONi!I lh.

,_ COMMON CLOCKPHASES

COMMON CLOCK

N SHIFT REGISTERS OF m BITS

NUMBER OF I/O TERMINALS LIMITED(N-8/9)

M = 128-2024 BITS

APPLICATIONS:SMALL DATA BUFFER REGISTERSFIFOLIFO, IF BIDIRECTIONAL

Figure 4. Arrayed CCD shift registers

In the memory organizations discussed above, theclocklines are common to the same phase electrodeseither with a straight layout or serpentine layout.We will now show the necessity and justification forhaving partitioned clocks. The chip may be organ-ized so that each group of shift registers has anindividual set of clock electrode lines. If these clockphases are to be externally supplied, then the extentto which the chip can be partitioned is pin-limitedand may be divided into two to four independentsections. More interesting is the case where the chipis partitioned into 32 to 128 sets of shift registerblocks having individual internal clocklines. All theclocks are internally generated for driving theindividual shift register sets. Since all the shiftregister sections have independent clocklines, onlythe ones that are called for refresh or access need tobe moved. Others may stay idle or move at aconstant low frequency, and this results in lowerpower dissipation for the entire chip. Of course, eachshift register has to be refreshed/accessed at leastonce during the storage time, which is 2 msec to

COMPUTER

11 4---ip r -11

- * CHANNEL REGIONCHANNEL STOPPER REGION

PHASEELECTRODES

COMMON CLOCKI L ' PHASES

CLOCK

STRAIGHT LAYOUT

LOW POWER DISSIPATION

HIGH PACKING DENSITY

2/3 SETS OF CLOCKS OF 2/3/4/PHASES HIGH INPUT/OUTPUT DATA RATE

SLOW ACCESS TO DATA

SERPENTINE LAYOUT

HIGH POWER DISSIPATION (ALL BITSMOVE SIMULTANEOUSLY)

FAST BLOCK ACCESS

APPLICATIONS:BLOCK ORGANIZED RANDOM ACCESSMEMORY (BORAM)

APPLICATIONS:SERIAL MASS MEMORYLARGE DATA BUFFERS

Figure 5. Serial-parallel.serial memory organization

10 msec depending on the circuit design and processtechniques. Figure 7 shows the block diagram ofsuch a memory organized with N number ofseparately controlled shift register loops. Figure 8shows a device consisting of a number of open endedshift registers with individual clocklines.6 The shiftregisters share a common input diffusion andoutput sensing diffusion. Only one of the shiftregisters is shifting data at any particular moment,and the same data is fed back in case of read andrefresh operations.

Refresh and Access Techniques

Charge-coupled memory sites store minority car-

riers; hence, they have to be refreshed periodicallyto retain data. The minority carrier storage time de-pends upon the amount of surface and bulk genera-tion centers and is temperature-dependent. This re-

fresh time could run from 2 to 10 msec dependingupon the particular process and sense amplifier

Figure 6. Closed loop serpentine shift registers

design. There are refresh, access, and data synchron-ization techniques that are applicable to the opera-tion of the memory devices and systems. Possibletechniques for charge-coupled memory operation areenumerated below.

Continuously Circulating Clock. All the shiftregisters in all the chips move continuously at aclock frequency, typically 1-5 MHz. Particular shiftregisters are accessed when requested. Averageaccess to any bit position is equal to l/2 X number ofbits/shift register X clock period. Power dissipationis high since all the shift register elements are movingconstantly. A power down mode of operation may beselected when the whole memory moves at a low fre-quency, say, 10-100 KHz. Power dissipation can below for SPS organization, because data frequency ishigher than the clock frequency.

High- and Low-Frequency Clock. All the shiftregisters in all the chips move continuously for

April 1976

DATA OUT- REFRESH

AMPLIFIER

INPUTCLOCK4 IN

OUTPUTCLOCK

37

- I

* a S

* 0 0

* 0 S

-~~~M

]-

SERPENTINE LAYOUT

CLOCK SELECTION CIRCUITS

DATA MOVES AT HIGH FREQUENCYIN SELECTED LOOP

LOW POWER DISSIPATION

PARTITIONED CLOCK DRIVE

APPLICATIONS:FAST LOW-POWER BORAM

02 01

Figure 7. Charge-coupled memory loops with individual clock lines

refreshing at a lower clock frequency, typically10-100 KHz selected for lower power dissipation.When particular shift registers are accessed, theyare only shifted at high frequency, typically,1-10 MHz. This needs distributed clock drivers andclock selection circuits. If the clock circuitry isincluded on the chip, the systems design will besimple. This is practical for the case when shiftregisters on the chips have individually controlledclocklines as shown earlier in Figure 7. Synchroniza-tion of the accessed shift registers can be accom-plished easily by a synchronization counter.The two-frequency approach can also be applied

to the design of systems using chips with commonclocklines. In such a case, the clock drivers and theselection circuits will be included on the memorycards. A large number of clock drivers capable ofdriving 500-2000 pf at high frequency will berequired.

Burst Clock. All the shift registers are refreshedby periodically recirculating at a high frequency,say 1-10 MHz. To access particular shift registers, a

burst clock is applied to those segments for circu-lating the data through a complete revolution. Thismethod is particularly suitable for fast CCD BORAMchips having individually controlled clocklines

38

(shown earlier in Figures 7 and 8). For the latter onewith common sense line, this is the only availabletechnique.The burst clock technique is similar to the one

adopted for dynamic MOS memories where the datais refreshed in row by row fashion. One of the signifi-cant advantages of this technique is that whenemployed as BORAM, non-skewed block data wouldbe immediately available for access during the non-refresh period. The major disadvantage is that a

considerable amount of time is spent for refreshoperations (10-50% of time for 128 X 256 bits run-

ning at 2-10 MHz and having a refresh time of about10 msec). The memory system has to be configuredso that access may be allowed to shift registersections that are not being refreshed. Because ofnon-uniformity in the leakage current, the minimumlow-frequency operation limit is higher for this modeof clocking.

Horizontal and Vertical Modes. In the horizontalmode of operation, clock phases are applied so thatdata moves in the registers in the horizontal direc-tion. For devices with common clocklines, data in allthe registers moves simultaneously, but we access

a particular register as selected by the decoder. Ifsuccessive registers are to be accessed, one continues

COMPUTER

k11

02 L

CHANNELCHANNEL STOP REGION

2

E-

LOG N

01 N

N

02 L .0 16

DATAR/W IN

LOGNBITS

CLOCKDECODER

2

N

_1

1i

02 01

@1

02

42COMMON

CHARGE INJECTOR

STRAIGHT LAYOUT

CLOCK SELECTION CIRCUITS

DATA MOVES AT HIGH FREQ.IN SELECTED REGISTER

LOW POWER DISSIPATION

PARTITIONED CLOCK DRIVE

EACH REGISTER MUST MOVEONCE DURING REFRESH INT.

APPLICATIONS:FAST LOW-POWER BORAM

COMMONCHARGE DETECTOR

Figure 8. Charge-coupled parallel registers with common 110 circuits and individual clock lines

applying the clock and selects the access to succes-sive registers. For devices with individually clockedshift registers, a horizontal mode of operation is thepreferred one. One register at a time is selected andmoved around completely to align it with the restof the registers.In the vertical mode of operation, one accesses

the data from the output end of all the registers bysequencing through all the register addresses. Fordevices with common clocklines, one moves the datahorizontally in all the registers by one position andthen sequentially reads out the data while keepingthe registers stationary. The shift clock applied tothe registers is a low frequency, so that enough timeis provided to access a group of shift registers.Devices having individual registers may beoperated in the vertical mode also. In that case,data in successive registers is moved one bit at atime, and a vertical segment of the data is takenfrom the output end of the registers. If operated in

April 1976

this mode, the average bit access time is muchlonger. This mode of operation is not recommended,unless high-frequency shifting is employed to accessthe beginning of the data block.

Charge-Coupled Memory System Organization

Charge-coupled memories are quasi-serial orpseudo-random by nature. So, charge-coupledmemory system operation has similarity with serial-access head-per-track disk systems and random-access semiconductor memory systems. Figure 9shows the block-schematic of the charge-coupledmemory system organized with the following sub-systems: storage array, control circuitry, interfacebuffer and distribution circuitry, and the powersupply unit. The storage array consists of a numberof printed circuit storage boards. The control cir-cuitry includes data-in and data-out registers and

39

L

circuits for generating all the system clocks. Datatransfer is generally started from a given addressand continued to successive addresses. So, addresssearch comparator and address sequence logic arealso provided.

Design Considerations. The memory system ismainly characterized by its cost, operational flexi-bility, and power dissipation. Fault-tolerance,encompassing different aspects of reliability, errorrecovery, and maintainability of the memorysystem, is another important design consideration.

Cost. One prime consideration in designing acharge-coupled memory system is the selection ofthe memory device that has the minimum cost andstill satisfies the performance requirements of thesystem.

Speed. Speed of the memory system is charac-terized by both the random access time to any wordand the data rate after the initial access.

Operational Flexibility. The memory systemshould have the provision for different operationalmodes, such as low-frequency idling mode, high-frequency search mode, fast data access mode, etc.Another useful provision is to have all the threeaccess modes: random word access mode, blockaccess mode, and serial access mode. Block accessmode is useful in applications as swapping memory.

CONTROL CIRCUITRY

DATA INREGISTERS

DATA OUTREGISTERS

MUTLIPLEXINGCIRCUITRY

ADDRESSSEQUENCEGENERATOR

ADDRESSSEARCHCOMPARATOR

TIMING ANDCLOCK

GENERATORS

CARD #N

cr

T

CD,~-I

cn

Cl,m

C)

C=

C.,

F-

ZLUJIL-z3

CLOCK DRIVERS I

ADDRESSI CONTROL DATABUFFERS BUFFERS UFFERS

CHIPDECODER

STORAGE ARRAY

Figure 9. Block schematic of a charge-coupled memorysystem

Power Dissipation. Most of the system power isdissipated in the storage array, mainly in memorydevices and clock drivers. Since the clock driverdissipation is directly proportional to frequency, itis desirable to minimize the system dissipation bylimiting the time of high-frequency search operations.

Memory Hierarchies WithCharge-Coupled Memories

The design goal of any memory hierarchy is tominimize the cost and maximize the performance sothat the performance of the memory hierarchy willapproach that of the fastest (and most expensive)level and the hierarchy cost per bit will approachthat of the cheapest (and the slowest) level. Multi-level hierarchies7-10 using charge-coupled memoriescan be designed if the overall system architecture-both hardware and software-is tailored to thespecial characteristics of these memories.Since their cost and performance fall in between

random access (MOS and bipolar) memories andSince their cost and performance fall in between

random access (MOS and bipolar) memories andserial access disk memories, one expects them to becost-performance competitive in the middle of thehierarchy. Figure 10 shows such a memory hierarchyhaving a combination of bipolar, MOS, CCD, anddisk-type memories.Each level in the hierarchy is characterized by its

size (Sn) in bytes, cost (CW) per byte, and the access

CENTRAL PROCESSING UNIT

SiC2 = 16¢0-1.6¢0/BYTET2 = 10NS-100NS

S2C2 = 2000 Me/- 600 M¢/BYTE

T2 = 400 NS-1,uS

S3C3 = 400 M¢- 160 M¢/BYTE

T3 = 1O.S - 5OO,S

S4 rC4 = 40 M¢-160 Mt/ BYTE

T4= 1 MS-50MMS

COMPUTER

RCARD #1

MEMORY CHIP ARRAY

POWER SUPPLY UNIT

LEVEL II

LEVEL IlIl

DISK LEVEL IV

Figure 10. Four-level memory hierarchy

LI -i

40

time (Tn).* Another important parameter ihit-ratio (Hn) for each level and refers to the Ibility of hitting the requested data at thatThe memory hierarchy can be evaluated in tercost (Ch), performance (Th), and cost-perfornproduct (CPh) of the complete hierarchy:

Oh = C11+ C22+ 8 3+- CCS

Th = HIT, + (H2-Hi)T2+ (H3 - H2)T3 + (H4 -H3)T4

CPh = Ch X Th

Our design goal is to optimize the size oflevel given a set of memory technologiesT1; C2, T2; C3, T3; and C4, T4). The memory rements for a normal mix of user programs c;represented by the hit-ratio characteristic. Ibeen observed that the hit-ratio vs. memor3has saturation characteristics'1'2 similar to thshown in Figure 11. The hit ratios H1, H2and H4 corresponding to sizes S1. S2, S3, arrespectively, can be determined from this clteristic. One calculates the cost, performancEcost-performance of the complete hierarchy fcdifferent configurations and chooses the coordion the hit-ratio characteristic to meet hisperformance goals.

*T,, T2, T., and T4 correspond to the access times of the hilevels I, II, III, and IV, respectively. The access timesT., and T4 include the time for address relocation, haccess, and data transfer from the particular level andponding lower levels until the data is available at the proThese hierarchy access times are also determined by thihierarchy management techniques employed.

1.0 7

0.98 -

0.9t

- 0.94 -

o-= 0.92 -

0.90 -

III

H,)

80KB 80OKB

MEMORY SIZE(S) IN KBYTES

Figure 11. Hit ratio vs. memory size

s theproba-level.ms ofaance

I eachs (C1,quire-an bet hasT sizeLe one:, H3,id S4,iarac-

Three-level and two-level CCD-based mnemoryhierarchies like bipolar-CCD-disk, MOS-CCD-disk,and CCD-disk are special cases of the general four-level hierarchy, and may be appropriate for manyapplications. The size and speed of the fastest levelis determined to match the processor speed, whereasthe disk configuration is decided by the file sizesand the volume of input/output traffic. The size ofthe inner level is optimized to achieve the particularcost and performance objectives. In general, theimprovement in the hierarchy performance withCCD memories is due to "disk buffering," wherebythe data is mostly accessed from the CCD memorylevel rather than directly from the disk.

Conclusion

, and New developments in electron beam pattern gen-or the eration and fabrication are drastically reducing thenates dimensions of semiconductor devices. Combiningcost- the electron beam technology with ion-implantation,

one can manufacture high-density CCD memories ofcell-size an order smaller than the present devices.Fault-tolerant designs including hardware redun-

erarchy dancy are anticipated at such a high level of integra-T,, T., tion, and this may further reduce the memory cost.atency, The application of charge-coupled memories incorres- computer systems design is proceeding slowlye exact because charge-coupled memories are not direct

replacements but, rather, new systems componentsthat the systems designer must understand andexploit. As charge-coupled memory devices becomemore readily available, memory management hard-ware/software techniques will be redefined to utilizethem. The magnitude of their impact on computer

Iv systems architecture will then be evident. -

(S4, H4)

G. Panigrahi is manager of Advanced Sys-tems Engineering at Burroughs Corporation,Computer Systems Group, Piscataway, NewJersey, and directs a group involved in thesystems application of new technologies such

< as CCD's, bubbles, etc., to computer sys-tems. Since 1973, he has been employed byBurroughs Corporation as senior and projectengineer, working on systems architecture,memory hierarchies, and charge coupled

memories. His other interests include associative processing,serial architecture, man-machine communication, and informa-tion networks.Dr. Panigrahi has several publications on MOS devices, charge

coupled memories, and computer architecture, and has fourpatents on charge coupled memories pending.

8MB He received the B. Tech. Hons. (communication engineering)in 1968, from the Indian Institute of Technology, Khatagpur;the MS and Ph.D in 1970 and 1973, respectively, from theUniversity of Illinois, Urbana. At the University of Illinois, heworked in the Solid State Electronics Lab and later with theComputer Hardware Research Group.

April 1976

11 (S3, H3)S,, H2)

4-LEVEL HIERARCHYS, = 8KB, H, =

11 S2 = 48KB, H2 =111 S3 = 48OKB, H3 =

I%/ C GRAD U.. 4 = uo1-, "-4 =

(EXAMPLE)950.990= .9991.0

41

-news&notes__Instantaneous on-line assessment of the dynamic or transientsecurity of a large electric power system could be accomplished byan automatic hybrid computer-based simulator proposed by EAI'sDr. Karel Janac. In a paper presented at the 1976 HawaiiInternational Conference on System Sciences Dr. Janac points outthat this can be done on the suggested computer where others havefailed. Part of the reason is in the hybrid computer itself, which isdesigned to truly calculate the power system's dynamic response 100times faster than real time.

Another feature of the new approach is use of "situation recogni-tion" to first determine the approximate state of the power system,followed by fast hybrid computation to check stability of the likelysituations that have been recognized. This is in sharp contrast withprevious pattern recognition methods, wherein the "classifier"decides whether the system is stable or not. This strains the classifiercomputer by demanding that it be at least 95% correct, usinginherently noise-corrupted signals from the power system andforcing it to decide what the system state might be from thousandsof possible patterns. The combination of the "situation recognition"technique and the hybrid computer would make possible correctiveaction prior to a serious system fault.

A simulated crash saves cash, helps cut down injurie& Ford WerkeAG makes extensive use of its PACER 600 hybrid computer systemin analysis of front end crashes on vehicles such as its "sexyEuropean" Capri. Data from crashes such as that pictured is acquiredand analyzed by the PACER system to assist engineers in design and

checkout of safety devicesthat reduce possible injur-ies to occupants. Otherhybrid computer uses at

~##'~'# ?1~#~ ~' ' ~ the Ford facility in WestGermany include totalsimulation of front endcrashes, examination ofside wind sensitivity, and

simulation of elastic engine mounts and transmission vibration.Simulation services are also offered to other organizations, alongwith development of any special programming packages required.

"Getting the most out of your hybrid computer" will be the themefor the Spring Meeting of the EAI Hybrid Computer Users' Group,April 20, 21 and 22 at Annapolis, Maryland, according to grouppresident Dr. C.J. Styers (Collins Radio Group, Rockwell Inter-national, Cedar Rapids, Iowa). The meeting is being hosted by theNaval Ships Research and Development Laboratory (NSDRL) inAnnapolis; a tour of their facilities is included in the meeting agenda.Persons interested in additional information on the meeting shouldcontact the group secretary, Mr. Robert Davison, at 201-229-1100.

For further information on developments of interest in hybridcomputation and simulation, contact. . .

Printed in U.S.A.

Dept. COM-04Electronic Associates, Inc.185 Monmouth ParkwayWest Long Branch, N.J. 07764

The Hybrid Computer People

Reader Service Number 422

References1. W. S. Boyle and G. E. Smith, "Charge

Coupled Semiconductor Devices,"Bell System Tech. J., Vol. 49, No. 4,1970, pp. 587-593.

2. G. F. Amelio, M. F. Tompsett and G.E. Smith, "Experimental Verificationof the Charge Coupled Device Con-cept," Bell System Tech. J., Vol. 49,No.4,1970, pp. 593-600.

3. M. F. Tompsett, "Charge TransferDevices," J. Vac. Science Technology,Vol. 9,1972, pp. 1166-1181.

4. W. F. Kosonocky, "Charge CoupledDigital Circuits," IEEE Journal ofSolid State Circuits, SC-6, No. 5, 1971,p.314.

5. N. G. Vogl and T. V. Harroun, "Oper-ating Memory System Using ChargeCoupled Devices, ISSCC Digest ofTechnical Papers, 1972, pp. 246-247.

6. G. F. Amelio, "Charge Coupled De-vices for Memory Applications,"AFIPS Conference Proc., 1975 NCC,pp. 515-522.

7. Y. S. Lin and R. L. Mattson, "Cost-Performance Evaluation of MemoryHierarchies," IEEE Trans. on Mag-netics, September 1972, p. 390.

8. I. L. Traiger and R. L. Mattson, "TheEvaluation and Selection of Technol-ogies for Computer Storage Systems,"AIP Conf. Proc. No. 5, 1972, pp. 1-9.

9. W. R. Beam, "Memory and StorageHierarchies-Rationale and Prospects,"1972 International Convention Digest;IEEE, March 1972.

10. W. Anacker, "Possible Uses of Charge-Transfer Devices and Magnetic-Domain Devices in Memory Hierar-chies," IEEE Trans. on Magnetics,September 1971, pp. 410-415.

11. C. K. Chow, "On Optimization ofStorage Hierarchies," IBM J. Res.Develop., May 1974, pp. 194-203.

12. G. Panigrahi, "Design and Analysisof Three-Level Memory Hierarchieswith Intermediate Level CCD SerialMemories," (presentation summar-ized in) 1975 Lake Arrowhead Work-shop, Summary, Computer, March1975, pp. 8-15.