Charge Coupled Device and Charge Injection Device ... Charge Coupled Device and Charge Injection

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Transcript of Charge Coupled Device and Charge Injection Device ... Charge Coupled Device and Charge Injection

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 1

Rochester Institute of TechnologyMicroelectronic Engineering

ROCHESTER INSTITUTE OF TECHNOLOGYMICROELECTRONIC ENGINEERING

Revision Date: 11-27-2003 lec_ccd.ppt

Charge Coupled Device and ChargeInjection Device Technology

George Lungu Dr. Lynn Fuller

Motorola Professor Microelectronic Engineering

Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041 LFFEEE@rit.edu

http://www.microe.rit.edu

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 2

Rochester Institute of TechnologyMicroelectronic Engineering

OUTLINE

Charge Generation in Semiconductors Potential Wells and Barriers Charge Transfer CCD Readout Channel Stops Overflow Drains (anti-blooming) Clocking Schemes CCD Sensor Architecture CIDs CID Sensor Architecture CID Readout Fabrication Processes for CCDs and

CIDs

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 3

Rochester Institute of TechnologyMicroelectronic Engineering

CONVERSION OF LIGHT TO ELECTRIC CURRENT INPN JUNCTION

B -

P+ Ionized Immobile Phosphorous donor atomIonized Immobile Boron acceptor atom

Phosphorous donor atom and electronP+-

B-+ Boron acceptor atom and hole

n-type

p-type

B - P+

B -B -

B -B -

P+ P+P+P+

P+

P+

P+-

B-+

B -B -

P+-

P+-

P+-

B-+

-+

-+

I

electronand hole

pair

-+

-+

space charge layer

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 4

Rochester Institute of TechnologyMicroelectronic Engineering

CHARGE COLLECTION IN MOS STRUCTURES

-+

-+

electronand hole

pair

-+

-+

depletion region

-+

-- -

p-type

+ V

B -

B -

B -

B -

1 3 42

thin poly gate

E = h = hc /

h = 6.625 e-34 j/s = (6.625 e-34/1.6e-19) eV/s

E = 1.55 eV (red)E = 2.50 eV (green)E = 4.14 eV (blue)

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 5

Rochester Institute of TechnologyMicroelectronic Engineering

POTENTIAL WELLS AND BARRIERS

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 6

Rochester Institute of TechnologyMicroelectronic Engineering

CHARGE TRANSFER

+ 15 + 5+ 10+ 5

- - - -- - -

- -

Gate 1 Gate 2 Gate 3 Gate 4

If a potential well is movedtogether with the surroundingbarrier, most of the electriccharge will move with it.

+ 10 +1 5+ 5+ 15

- - - -- - -

- -

Gate 1 Gate 2 Gate 3 Gate 4

+ 5 + 10+ 15+ 10

Gate 1 Gate 2 Gate 3 Gate 4

- - - -- - -

- - - -- - -

- -

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 7

Rochester Institute of TechnologyMicroelectronic Engineering

BURIED CHANNEL VS SURFACE CHANNEL CCDS

Depending on the doping profile in the channel the electrons (p-type substrate) may be drawn toward the surface or tend to stayslightly below the surface in a lower energy channel. An n-typeimplant that has a peak slightly below the surface will result in aburied channel device. Buried channel devices are preferredbecause less electrons will be lost at traps at the surface interface.

NA

X1 m

NA

X1 m

ND

NN Buried Channel Surface Channel

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 8

Rochester Institute of TechnologyMicroelectronic Engineering

READOUT

+ 15 + 5+ 10+ 5 + 15+ 10+ 5

n+

p-type

+ V

Vout

When electrons are emptied from the last gate the electricfield associated with the pn junction collects electrons thatmove to +V and Vout will drop to a level proportional tothe number of electrons in that packet.

- - - -- - -

- -- - - -- - -

- -

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 9

Rochester Institute of TechnologyMicroelectronic Engineering

Field Gate Channel Stop

CHANNEL STOP

The channel stop defines the width of the active region. Thebuilt in electric fields from pn junctions is such that electronswill be forced under the gates. Potential barriers created byField Gate Electrodes can also keep electrons under channelgates.

p-type

Gate 4

- - - -- - -

p+ channel stop

Gate 1

p-type

Gate 4

- - - -- - -

Gate 1

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 10

Rochester Institute of TechnologyMicroelectronic Engineering

OVERFLOW DRAINS (ANTI-BLOOMING)

Potential well decreases as thewell fills with electronseventually electrons will spillinto nearby wells.

p-type

Gate 4

- - - -- - -

p+ channel stop

Gate 1

Overflow Drain

Control Gate

n+

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 11

Rochester Institute of TechnologyMicroelectronic Engineering

FOUR PHASE CLOCKING SCHEME

p-type

4-phase, two voltage levels

1234

1234

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 12

Rochester Institute of TechnologyMicroelectronic Engineering

THREE PHASE CLOCKING SCHEME

p-type

3-phase, 3 voltage levels

V3V2V1

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 13

Rochester Institute of TechnologyMicroelectronic Engineering

TWO PHASE CLOCKING SCHEME

p-type

2-phase, 2 voltage levels

21

+++++ ++++++++++ +++++ +++++

ion implant under 1/2 of each gate

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 14

Rochester Institute of TechnologyMicroelectronic Engineering

CCD SENSOR ARCHITECTURE

Line Addressed Organization Interline Transfer Organization

Transfer Gate Line

PhotodiodesHorizontalShifting CCD

HorizontalShifting CCD

VerticalShifting CCD

VerticalShiftingCCD

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 15

Rochester Institute of TechnologyMicroelectronic Engineering

INTERLINE CCD

Unit cell cross section

Photo diode & photo shield

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 16

Rochester Institute of TechnologyMicroelectronic Engineering

CCD SENSOR ARCHITECTURE

Frame Transfer Organization

HorizontalShifting CCD

VerticalShiftingCCD

LightShieldedArea

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 17

Rochester Institute of TechnologyMicroelectronic Engineering

FRAME TRANSFER CCD

CMOS circuits for CCD

588 lines of 604 pixels, sensor areaon left and light shielded storage

area on right

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 18

Rochester Institute of TechnologyMicroelectronic Engineering

5000 ELEMENT LINEAR CCD IMAGER

High resolution, 5000 elementsWide dynamic range2V peak-to-peak outputHigh charge transfer efficiency2 phase clockingOn-chip dark referenceHigh speed operationOn-chip sample/hold

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 19

Rochester Institute of TechnologyMicroelectronic Engineering

5000 ELEMENT LINEAR CCD IMAGER

The KLI-500 devices are high resolution linear arrays designed for scanned imagingapplications. Each device contains a row of 5000 active photo elements, consistingof high performance diodes for improved sensitivity and lower noise. Readout of thepixel data is accomplished through the use of dual CCD shift registers, positioned oneither side of the diode array.

The sensors are positioned on 7 m centers with an associated 7 m aperture whichspans the length of the array. A dark reference consisting of 24 light shieldedelements is also located on each end of the array. The architecture and operation ofthe A and B versions are similar except the B device contains on-chip, correlateddouble sampling circuitry.

The devices are manufactured using NMOS, buried channel processing, and utilizedual layer polysilicon and dual layer metal technologies. The die size is 36.00mm x1.12 mm and the chip is housed in a 24-pin 0.600 wide, dual-in-line package.

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 20

Rochester Institute of TechnologyMicroelectronic Engineering

1320 (H) x 1035 (V) ElEMENT FULL FRAME CCD IMAGER

1,366,200 Pixels without interlacingOn-chip column format dark referenceAnti-blooming protection2/3 Inch format compatibilitySquare pixels for robotic visio