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© January 5, 2005 Dr. Lynn Fuller, Motorola Professor CCD and CID Technology Page 1 Rochester Institute of Technology Microelectronic Engineering ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Revision Date: 11-27-2003 lec_ccd.ppt Charge Coupled Device and Charge Injection Device Technology George Lungu Dr. Lynn Fuller Motorola Professor Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041 [email protected] http://www.microe.rit.edu

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January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 1

Rochester Institute of TechnologyMicroelectronic Engineering

ROCHESTER INSTITUTE OF TECHNOLOGYMICROELECTRONIC ENGINEERING

Revision Date: 11-27-2003 lec_ccd.ppt

Charge Coupled Device and ChargeInjection Device Technology

George Lungu Dr. Lynn Fuller

Motorola Professor Microelectronic Engineering

Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041 [email protected]

http://www.microe.rit.edu

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 2

Rochester Institute of TechnologyMicroelectronic Engineering

OUTLINE

Charge Generation in Semiconductors Potential Wells and Barriers Charge Transfer CCD Readout Channel Stops Overflow Drains (anti-blooming) Clocking Schemes CCD Sensor Architecture CIDs CID Sensor Architecture CID Readout Fabrication Processes for CCDs and

CIDs

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 3

Rochester Institute of TechnologyMicroelectronic Engineering

CONVERSION OF LIGHT TO ELECTRIC CURRENT INPN JUNCTION

B -

P+ Ionized Immobile Phosphorous donor atomIonized Immobile Boron acceptor atom

Phosphorous donor atom and electronP+-

B-+ Boron acceptor atom and hole

n-type

p-type

B - P+

B -B -

B -B -

P+ P+P+P+

P+

P+

P+-

B-+

B -B -

P+-

P+-

P+-

B-+

-+

-+

I

electronand hole

pair

-+

-+

space charge layer

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 4

Rochester Institute of TechnologyMicroelectronic Engineering

CHARGE COLLECTION IN MOS STRUCTURES

-+

-+

electronand hole

pair

-+

-+

depletion region

-+

-- -

p-type

+ V

B -

B -

B -

B -

1 3 42

thin poly gate

E = h = hc /

h = 6.625 e-34 j/s = (6.625 e-34/1.6e-19) eV/s

E = 1.55 eV (red)E = 2.50 eV (green)E = 4.14 eV (blue)

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 5

Rochester Institute of TechnologyMicroelectronic Engineering

POTENTIAL WELLS AND BARRIERS

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

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Rochester Institute of TechnologyMicroelectronic Engineering

CHARGE TRANSFER

+ 15 + 5+ 10+ 5

- - - -- - -

- -

Gate 1 Gate 2 Gate 3 Gate 4

If a potential well is movedtogether with the surroundingbarrier, most of the electriccharge will move with it.

+ 10 +1 5+ 5+ 15

- - - -- - -

- -

Gate 1 Gate 2 Gate 3 Gate 4

+ 5 + 10+ 15+ 10

Gate 1 Gate 2 Gate 3 Gate 4

- - - -- - -

- - - -- - -

- -

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 7

Rochester Institute of TechnologyMicroelectronic Engineering

BURIED CHANNEL VS SURFACE CHANNEL CCDS

Depending on the doping profile in the channel the electrons (p-type substrate) may be drawn toward the surface or tend to stayslightly below the surface in a lower energy channel. An n-typeimplant that has a peak slightly below the surface will result in aburied channel device. Buried channel devices are preferredbecause less electrons will be lost at traps at the surface interface.

NA

X1 m

NA

X1 m

ND

NN Buried Channel Surface Channel

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 8

Rochester Institute of TechnologyMicroelectronic Engineering

READOUT

+ 15 + 5+ 10+ 5 + 15+ 10+ 5

n+

p-type

+ V

Vout

When electrons are emptied from the last gate the electricfield associated with the pn junction collects electrons thatmove to +V and Vout will drop to a level proportional tothe number of electrons in that packet.

- - - -- - -

- -- - - -- - -

- -

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 9

Rochester Institute of TechnologyMicroelectronic Engineering

Field Gate Channel Stop

CHANNEL STOP

The channel stop defines the width of the active region. Thebuilt in electric fields from pn junctions is such that electronswill be forced under the gates. Potential barriers created byField Gate Electrodes can also keep electrons under channelgates.

p-type

Gate 4

- - - -- - -

p+ channel stop

Gate 1

p-type

Gate 4

- - - -- - -

Gate 1

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 10

Rochester Institute of TechnologyMicroelectronic Engineering

OVERFLOW DRAINS (ANTI-BLOOMING)

Potential well decreases as thewell fills with electronseventually electrons will spillinto nearby wells.

p-type

Gate 4

- - - -- - -

p+ channel stop

Gate 1

Overflow Drain

Control Gate

n+

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 11

Rochester Institute of TechnologyMicroelectronic Engineering

FOUR PHASE CLOCKING SCHEME

p-type

4-phase, two voltage levels

1234

1234

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 12

Rochester Institute of TechnologyMicroelectronic Engineering

THREE PHASE CLOCKING SCHEME

p-type

3-phase, 3 voltage levels

V3V2V1

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

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Rochester Institute of TechnologyMicroelectronic Engineering

TWO PHASE CLOCKING SCHEME

p-type

2-phase, 2 voltage levels

21

+++++ ++++++++++ +++++ +++++

ion implant under 1/2 of each gate

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 14

Rochester Institute of TechnologyMicroelectronic Engineering

CCD SENSOR ARCHITECTURE

Line Addressed Organization Interline Transfer Organization

Transfer Gate Line

PhotodiodesHorizontalShifting CCD

HorizontalShifting CCD

VerticalShifting CCD

VerticalShiftingCCD

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 15

Rochester Institute of TechnologyMicroelectronic Engineering

INTERLINE CCD

Unit cell cross section

Photo diode & photo shield

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 16

Rochester Institute of TechnologyMicroelectronic Engineering

CCD SENSOR ARCHITECTURE

Frame Transfer Organization

HorizontalShifting CCD

VerticalShiftingCCD

LightShieldedArea

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 17

Rochester Institute of TechnologyMicroelectronic Engineering

FRAME TRANSFER CCD

CMOS circuits for CCD

588 lines of 604 pixels, sensor areaon left and light shielded storage

area on right

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 18

Rochester Institute of TechnologyMicroelectronic Engineering

5000 ELEMENT LINEAR CCD IMAGER

High resolution, 5000 elementsWide dynamic range2V peak-to-peak outputHigh charge transfer efficiency2 phase clockingOn-chip dark referenceHigh speed operationOn-chip sample/hold

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 19

Rochester Institute of TechnologyMicroelectronic Engineering

5000 ELEMENT LINEAR CCD IMAGER

The KLI-500 devices are high resolution linear arrays designed for scanned imagingapplications. Each device contains a row of 5000 active photo elements, consistingof high performance diodes for improved sensitivity and lower noise. Readout of thepixel data is accomplished through the use of dual CCD shift registers, positioned oneither side of the diode array.

The sensors are positioned on 7 m centers with an associated 7 m aperture whichspans the length of the array. A dark reference consisting of 24 light shieldedelements is also located on each end of the array. The architecture and operation ofthe A and B versions are similar except the B device contains on-chip, correlateddouble sampling circuitry.

The devices are manufactured using NMOS, buried channel processing, and utilizedual layer polysilicon and dual layer metal technologies. The die size is 36.00mm x1.12 mm and the chip is housed in a 24-pin 0.600 wide, dual-in-line package.

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 20

Rochester Institute of TechnologyMicroelectronic Engineering

1320 (H) x 1035 (V) ElEMENT FULL FRAME CCD IMAGER

1,366,200 Pixels without interlacingOn-chip column format dark referenceAnti-blooming protection2/3 Inch format compatibilitySquare pixels for robotic vision Two-phase clockingHigh dynamic range and S/NNo image lag or burn-in4.3 Aspect ratio

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 21

Rochester Institute of TechnologyMicroelectronic Engineering

1320 (H) x 1035 (V) ELEMENT FULL FRAME CCD IMAGER

The KAF-1400 is a 1320(H) x 1035(V) element, solid state charge-coupled device,full frame imager. It is designed for high resolution monochrome imaging and hassquare pixels for robotic vision applications. The devices optically active areameasures 8.98(H) x 7.04(V) mm. Each element in the array measures 6.8m by6.8m.

An image is obtained by collecting the electrons generated when incident imagephotons create electron hole pairs within the silicon. The amount of charge storedper pixel is a linear function of the localized light intensity and the integration time,and a non-linear function of wavelength. The signal charge is then transferred out ofthe image area by two-phase complementary clocking. The dark reference consistsof 20 columns, each spanning the entire height of the image area, and is located atthe left side of the sensor. The first and last row is also dark. During integration therows are shifted vertically and read out horizontally.

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 22

Rochester Institute of TechnologyMicroelectronic Engineering

CMOS-I/CCD PROCESS CROSS-SECTIONAL VIEW

N-Channel FET

P-Channel FETN-Well

Buried Channel2 Level Poly

CCD

Poly-to-PolyCapacitor

P+ SourceDrain, Substrate

Contact

Isolated Vertical NPNBipolar Transistor

P-type siliconN-well

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 23

Rochester Institute of TechnologyMicroelectronic Engineering

CIDS

Charge Injection Devices

Random readout of image information is possible

Nondestructive readout is also possible

Suitable for use in pattern recognition, targettracking and other forms of image processing

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 24

Rochester Institute of TechnologyMicroelectronic Engineering

PHYSICAL STRUCTURE

Each pixel consists of a pair of MOS capacitors

The two capacitors run perpendicularly to eachother and are know as collection and sense pads

ThinOxide

p substrate

n epitaxy

poly 2

poly 1poly 1

poly 2

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 25

Rochester Institute of TechnologyMicroelectronic Engineering

CID ARCHITECTURE

The collection pad is common for all the pixels in a row.

The sense pad is common for all the pixels in a column.

Both collection and sensepads are controlled bydemultiplexers orshift registers.

Y X

Y X

Y X

Y X

Y X

Y X

Horizontal Scan

Ver

tical

Sca

n

VrefReset

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 26

Rochester Institute of TechnologyMicroelectronic Engineering

PHOTON COLLECTION AND READOUT IN A CID

p substrate

n epipoly 1 poly 2

- +sense

- +collection

+ +++ +

Photons generate electrons andholes. Holes are collected in thedepletion region (potential well)under the poly2 gate.

Sense at -5, Collection at -7

Accumulation

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 27

Rochester Institute of TechnologyMicroelectronic Engineering

ZERO LEVEL SENSE AND SIGNAL SENSE

p substrate

n epipoly 1 poly 2

- +sense

- +collection

+ +++ +

Zero Level Sense(floating gate readout)

p substrate

n epipoly 1 poly 2

- +sense

- +collection

+ +++ +

Signal SenseV = Q/C

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 28

Rochester Institute of TechnologyMicroelectronic Engineering

INJECTION (DESTRUCIVE READOUT)

p substrate

n epipoly 1 poly 2

- +sense

- +collection

+

++

++

Injection

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 29

Rochester Institute of TechnologyMicroelectronic Engineering

RIT CID PROCESS

PMOS on n-type epitaxial substrate6 micron gate, 4 micron contact cutDouble poly-silicon, one metal level15 V process, 50 nm gate oxide

8 Photo levelsActivePoly-1Poly-2p+ D/S Implantn+ Substrate ContactPinning ImplantContact CutMetal

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 30

Rochester Institute of TechnologyMicroelectronic Engineering

CELL LAYOUT

RowSelect

ColumnSelect

Vreset-5 to collect+5 to reset

Reset Select

Out

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 31

Rochester Institute of TechnologyMicroelectronic Engineering

TEST BLOCK DIAGRAM

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 32

Rochester Institute of TechnologyMicroelectronic Engineering

ARRAY and CLOCKING WAVEFORM

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 33

Rochester Institute of TechnologyMicroelectronic Engineering

OUTPUT WAVEFORM

Output of vertical slit illumination

Output for horizontal slit illumination

Output for point illumination

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 34

Rochester Institute of TechnologyMicroelectronic Engineering

DISPLAY OUTPUT BY COLUMN

Wire blocking rows in array

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 35

Rochester Institute of TechnologyMicroelectronic Engineering

DISPLAY OUTPUT BY COLUMN

Wire blocking columns in array

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 36

Rochester Institute of TechnologyMicroelectronic Engineering

NEW PIXEL DESIGN

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 37

Rochester Institute of TechnologyMicroelectronic Engineering

ACTIVE PIXEL ARRAY

output

buffer

preamp

LightSensitive Area

Light Sensitive Area

buffer

output

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 38

Rochester Institute of TechnologyMicroelectronic Engineering

32 X 32 PIXEL ARRAY

32 X 32 Array Fabricated at RIT

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 39

Rochester Institute of TechnologyMicroelectronic Engineering

128 x 128 PIXEL DESIGN

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 40

Rochester Institute of TechnologyMicroelectronic Engineering

RESULTS

128 x 128 Array Fabricated atOrbit Semiconductor Includes onChip Electronics for Addressing

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 41

Rochester Institute of TechnologyMicroelectronic Engineering

RESULTS

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 42

Rochester Institute of TechnologyMicroelectronic Engineering

RESULTS

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 43

Rochester Institute of TechnologyMicroelectronic Engineering

RESULTS

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 44

Rochester Institute of TechnologyMicroelectronic Engineering

FIRST PICTURES FROM RIT 128 X 128 CID

April 16, 1999

Objects were placeddirectly on the glasscover over the CID chip

0.3 msec timed exposurefrom a red LED

CID output stored in gifformat and then printed

Cleanroom Fly

Nut &Washer

RIT CID chip128 x 128

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 45

Rochester Institute of TechnologyMicroelectronic Engineering

FIRST PICTURES FROM RIT 128 X 128 CID

April 16, 1999

Images projected ontoCID from a 35 mm slideusing a 50 mm lense100 msec timed exposurefrom a red LED

CID output stored in gifformat and then printed

George Lungu

Mom

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 46

Rochester Institute of TechnologyMicroelectronic Engineering

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 47

Rochester Institute of TechnologyMicroelectronic Engineering

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 48

Rochester Institute of TechnologyMicroelectronic Engineering

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 49

Rochester Institute of TechnologyMicroelectronic Engineering

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 50

Rochester Institute of TechnologyMicroelectronic Engineering

REFERENCES

1. Imaging Devices Using the Charge-Coupled Concept,David f. Barbe, Proceedings of the IEEE, Vol.63, No. 1,January 1975. 2. B.S.T.J. Briefs, Charge Coupled Semiconductor Devices,

W.S. Boyle and G.E. Smith, January 29, 1970, The Bell SystemTechnical Journal, Vol.49, April 1970. 3. Solid State Image Sensors Using the Charge Transfer

Principle, J.G. van Santen, Proceedings of the 8th Conferenceon solid State Devices, Tokyo, 1976, Japanese Journal ofApplied Physics, Volume 16 (1877) Supplement 16-1, pp 365-371. 4. Eastman Kodak Company, Electronic Imaging,

Microelectronics Technology Division, Products Literature.

January 5, 2005 Dr. Lynn Fuller, Motorola Professor

CCD and CID Technology

Page 51

Rochester Institute of TechnologyMicroelectronic Engineering

HOMEWORK - CCDS AND CIDS

1. Describe how charge is generated in a CCD. 2. How is charge transferred in a two phase CCD. 3. How does a CID work?