[AEEMT] [Zhao YU] [20170588]

Characterisation and Modelling of Nanoelectronics

Individual switches or transistors on microchips are now made on lengths of a few billionth of a metre or on the ‘nanoscale’. Computer models of transistors or ‘compact models’ are needed to design new microchips. Compact models must describe complex behaviour for emerging transistors due to new physical effects arising on the nanoscale. An artificial neural network (ANN) approach is proposed to provide a simplified compact models to describe transistor operation.

Introduction

2#2

2#4

2#6

2#8

2#10

0

0.05

0.1

0.15

0.2

1#2 1#3 1#4 1#5 1#6 1#7 1#8 1#9 1#10 1#11

Output error with different neuron combination

0-0.05 0.05-0.1 0.1-0.15 0.15-0.2

MOSFET Drain Current Compact Model

Figure 2 Output error (RMS error) for each combination of neurons from Table 1. Most combinations come out with large training loss, only a few combinations can be chosen as suitable neural network structure

with loss < 4%

Figure 1 Basic transistor structure for modeling independent double-gate MOSFETs

Objectives

The above calculations are only part of a compact model of a MOSFET and are part of a physics based compact model. Similar equations are performed for a surface potential calculation, a capacitance model, as well as other required physical properties. There are also emerging effects newly needed to be considered such as quantum mechanical effects, short channel effects, effective width model and treatment of bulk/SOI substrate models. Each term requires significant effort to measure or to ‘fit’. The models rely on a large number of parameterized equations that are requiring large amounts of computational design when compact models are combined for microchip design.

An alternative way for MOSFET compact modeling via artificial neuron network with training with IV

datasets of existing advanced transistors.

Methodology & Results

LOSS 1#2 1#3 … 1#10 1#11

2#2 2.5% 9.6% … 9.9% 8.0%

2#3 4.4% 7.4% … 8.4% 12.3%

… … … … … …

2#10 9.9% 10.1% … 12.4% 15.1%

2#11 8.7% 11.1% … 12.6% 13.3%

Table 1 Output error (RMS error) for each combination of neurons

Acceptable with error < 4%, unacceptable for error >10%

An artificial neural network approach is proposed by basing compact models on ANN. The current and

voltage relations for MOSFETs are used to train the network, and to allow the network to predict the

performance of transistors with different geometries.

The purpose of the Design of Experiments

is to determine the optimal architecture for

hidden neuron layer with minimum output error. With reasonable

training dataset and input variables

initialization, predictive results are obtained

with low error.

Conclusion

As the transistor size shrinks down to nanoscale, unexpected physical phenomena emerges which makes the traditional analytical way losing their validation. ANN approaches were proposed as a possible solution

for compact modeling in nanoscale, considering output IV characteristics as regression problem and has the capability of adding more variables,

making the IV characteristics of emerging device predictable, more accurate and more computational efficient.

Traditional BSIM $ Compact Model Process

Example of traditional physical based equations for compact model description of a transistor :